1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * Copyright 2011, Marvell Semiconductor Inc.
4 * Lei Wen <leiwen@marvell.com>
5 *
6 * Back ported to the 8xx platform (from the 8260 platform) by
7 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
8 */
9 #ifndef __SDHCI_HW_H
10 #define __SDHCI_HW_H
11
12 #include <asm/io.h>
13 #include <mmc.h>
14 #include <asm-generic/gpio.h>
15
16 /*
17 * Controller registers
18 */
19
20 #define SDHCI_DMA_ADDRESS 0x00
21
22 #define SDHCI_BLOCK_SIZE 0x04
23 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
24
25 #define SDHCI_BLOCK_COUNT 0x06
26
27 #define SDHCI_ARGUMENT 0x08
28
29 #define SDHCI_TRANSFER_MODE 0x0C
30 #define SDHCI_TRNS_DMA BIT(0)
31 #define SDHCI_TRNS_BLK_CNT_EN BIT(1)
32 #define SDHCI_TRNS_ACMD12 BIT(2)
33 #define SDHCI_TRNS_READ BIT(4)
34 #define SDHCI_TRNS_MULTI BIT(5)
35
36 #define SDHCI_COMMAND 0x0E
37 #define SDHCI_CMD_RESP_MASK 0x03
38 #define SDHCI_CMD_CRC 0x08
39 #define SDHCI_CMD_INDEX 0x10
40 #define SDHCI_CMD_DATA 0x20
41 #define SDHCI_CMD_ABORTCMD 0xC0
42
43 #define SDHCI_CMD_RESP_NONE 0x00
44 #define SDHCI_CMD_RESP_LONG 0x01
45 #define SDHCI_CMD_RESP_SHORT 0x02
46 #define SDHCI_CMD_RESP_SHORT_BUSY 0x03
47
48 #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
49 #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
50
51 #define SDHCI_RESPONSE 0x10
52
53 #define SDHCI_BUFFER 0x20
54
55 #define SDHCI_PRESENT_STATE 0x24
56 #define SDHCI_CMD_INHIBIT BIT(0)
57 #define SDHCI_DATA_INHIBIT BIT(1)
58 #define SDHCI_DOING_WRITE BIT(8)
59 #define SDHCI_DOING_READ BIT(9)
60 #define SDHCI_SPACE_AVAILABLE BIT(10)
61 #define SDHCI_DATA_AVAILABLE BIT(11)
62 #define SDHCI_CARD_PRESENT BIT(16)
63 #define SDHCI_CARD_STATE_STABLE BIT(17)
64 #define SDHCI_CARD_DETECT_PIN_LEVEL BIT(18)
65 #define SDHCI_WRITE_PROTECT BIT(19)
66
67 #define SDHCI_HOST_CONTROL 0x28
68 #define SDHCI_CTRL_LED BIT(0)
69 #define SDHCI_CTRL_4BITBUS BIT(1)
70 #define SDHCI_CTRL_HISPD BIT(2)
71 #define SDHCI_CTRL_DMA_MASK 0x18
72 #define SDHCI_CTRL_SDMA 0x00
73 #define SDHCI_CTRL_ADMA1 0x08
74 #define SDHCI_CTRL_ADMA32 0x10
75 #define SDHCI_CTRL_ADMA64 0x18
76 #define SDHCI_CTRL_8BITBUS BIT(5)
77 #define SDHCI_CTRL_CD_TEST_INS BIT(6)
78 #define SDHCI_CTRL_CD_TEST BIT(7)
79
80 #define SDHCI_POWER_CONTROL 0x29
81 #define SDHCI_POWER_ON 0x01
82 #define SDHCI_POWER_180 0x0A
83 #define SDHCI_POWER_300 0x0C
84 #define SDHCI_POWER_330 0x0E
85
86 #define SDHCI_BLOCK_GAP_CONTROL 0x2A
87
88 #define SDHCI_WAKE_UP_CONTROL 0x2B
89 #define SDHCI_WAKE_ON_INT BIT(0)
90 #define SDHCI_WAKE_ON_INSERT BIT(1)
91 #define SDHCI_WAKE_ON_REMOVE BIT(2)
92
93 #define SDHCI_CLOCK_CONTROL 0x2C
94 #define SDHCI_DIVIDER_SHIFT 8
95 #define SDHCI_DIVIDER_HI_SHIFT 6
96 #define SDHCI_DIV_MASK 0xFF
97 #define SDHCI_DIV_MASK_LEN 8
98 #define SDHCI_DIV_HI_MASK 0x300
99 #define SDHCI_PROG_CLOCK_MODE BIT(5)
100 #define SDHCI_CLOCK_PLL_EN BIT(3)
101 #define SDHCI_CLOCK_CARD_EN BIT(2)
102 #define SDHCI_CLOCK_INT_STABLE BIT(1)
103 #define SDHCI_CLOCK_INT_EN BIT(0)
104
105 #define SDHCI_TIMEOUT_CONTROL 0x2E
106
107 #define SDHCI_SOFTWARE_RESET 0x2F
108 #define SDHCI_RESET_ALL 0x01
109 #define SDHCI_RESET_CMD 0x02
110 #define SDHCI_RESET_DATA 0x04
111
112 #define SDHCI_INT_STATUS 0x30
113 #define SDHCI_INT_ENABLE 0x34
114 #define SDHCI_SIGNAL_ENABLE 0x38
115 #define SDHCI_INT_RESPONSE BIT(0)
116 #define SDHCI_INT_DATA_END BIT(1)
117 #define SDHCI_INT_DMA_END BIT(3)
118 #define SDHCI_INT_SPACE_AVAIL BIT(4)
119 #define SDHCI_INT_DATA_AVAIL BIT(5)
120 #define SDHCI_INT_CARD_INSERT BIT(6)
121 #define SDHCI_INT_CARD_REMOVE BIT(7)
122 #define SDHCI_INT_CARD_INT BIT(8)
123 #define SDHCI_INT_ERROR BIT(15)
124 #define SDHCI_INT_TIMEOUT BIT(16)
125 #define SDHCI_INT_CRC BIT(17)
126 #define SDHCI_INT_END_BIT BIT(18)
127 #define SDHCI_INT_INDEX BIT(19)
128 #define SDHCI_INT_DATA_TIMEOUT BIT(20)
129 #define SDHCI_INT_DATA_CRC BIT(21)
130 #define SDHCI_INT_DATA_END_BIT BIT(22)
131 #define SDHCI_INT_BUS_POWER BIT(23)
132 #define SDHCI_INT_ACMD12ERR BIT(24)
133 #define SDHCI_INT_ADMA_ERROR BIT(25)
134
135 #define SDHCI_INT_NORMAL_MASK 0x00007FFF
136 #define SDHCI_INT_ERROR_MASK 0xFFFF8000
137
138 #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
139 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
140 #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
141 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
142 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
143 SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR)
144 #define SDHCI_INT_ALL_MASK ((unsigned int)-1)
145
146 #define SDHCI_ACMD12_ERR 0x3C
147
148 #define SDHCI_HOST_CONTROL2 0x3E
149 #define SDHCI_CTRL_UHS_MASK 0x0007
150 #define SDHCI_CTRL_UHS_SDR12 0x0000
151 #define SDHCI_CTRL_UHS_SDR25 0x0001
152 #define SDHCI_CTRL_UHS_SDR50 0x0002
153 #define SDHCI_CTRL_UHS_SDR104 0x0003
154 #define SDHCI_CTRL_UHS_DDR50 0x0004
155 #define SDHCI_CTRL_HS400 0x0007 /* Non-standard */
156 #define SDHCI_CTRL_VDD_180 0x0008
157 #define SDHCI_CTRL_DRV_TYPE_MASK 0x0030
158 #define SDHCI_CTRL_DRV_TYPE_B 0x0000
159 #define SDHCI_CTRL_DRV_TYPE_A 0x0010
160 #define SDHCI_CTRL_DRV_TYPE_C 0x0020
161 #define SDHCI_CTRL_DRV_TYPE_D 0x0030
162 #define SDHCI_CTRL_EXEC_TUNING 0x0040
163 #define SDHCI_CTRL_TUNED_CLK 0x0080
164 #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000
165
166 #define SDHCI_CAPABILITIES 0x40
167 #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
168 #define SDHCI_TIMEOUT_CLK_SHIFT 0
169 #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
170 #define SDHCI_CLOCK_BASE_MASK 0x00003F00
171 #define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00
172 #define SDHCI_CLOCK_BASE_SHIFT 8
173 #define SDHCI_MAX_BLOCK_MASK 0x00030000
174 #define SDHCI_MAX_BLOCK_SHIFT 16
175 #define SDHCI_CAN_DO_8BIT BIT(18)
176 #define SDHCI_CAN_DO_ADMA2 BIT(19)
177 #define SDHCI_CAN_DO_ADMA1 BIT(20)
178 #define SDHCI_CAN_DO_HISPD BIT(21)
179 #define SDHCI_CAN_DO_SDMA BIT(22)
180 #define SDHCI_CAN_VDD_330 BIT(24)
181 #define SDHCI_CAN_VDD_300 BIT(25)
182 #define SDHCI_CAN_VDD_180 BIT(26)
183 #define SDHCI_CAN_64BIT BIT(28)
184
185 #define SDHCI_CAPABILITIES_1 0x44
186 #define SDHCI_SUPPORT_SDR50 0x00000001
187 #define SDHCI_SUPPORT_SDR104 0x00000002
188 #define SDHCI_SUPPORT_DDR50 0x00000004
189 #define SDHCI_USE_SDR50_TUNING 0x00002000
190
191 #define SDHCI_CLOCK_MUL_MASK 0x00FF0000
192 #define SDHCI_CLOCK_MUL_SHIFT 16
193
194 #define SDHCI_MAX_CURRENT 0x48
195
196 /* 4C-4F reserved for more max current */
197
198 #define SDHCI_SET_ACMD12_ERROR 0x50
199 #define SDHCI_SET_INT_ERROR 0x52
200
201 #define SDHCI_ADMA_ERROR 0x54
202
203 /* 55-57 reserved */
204
205 #define SDHCI_ADMA_ADDRESS 0x58
206 #define SDHCI_ADMA_ADDRESS_HI 0x5c
207
208 /* 60-FB reserved */
209
210 #define SDHCI_SLOT_INT_STATUS 0xFC
211
212 #define SDHCI_HOST_VERSION 0xFE
213 #define SDHCI_VENDOR_VER_MASK 0xFF00
214 #define SDHCI_VENDOR_VER_SHIFT 8
215 #define SDHCI_SPEC_VER_MASK 0x00FF
216 #define SDHCI_SPEC_VER_SHIFT 0
217 #define SDHCI_SPEC_100 0
218 #define SDHCI_SPEC_200 1
219 #define SDHCI_SPEC_300 2
220 #define SDHCI_SPEC_400 3
221 #define SDHCI_SPEC_420 5
222
223 /* 0x508 */
224 #define SDHCI_MSHC_CTRL 0x508
225 #define SDHCI_CMD_CONFLIT_CHECK 0x01
226
227 /* 0x510 */
228 #define SDHCI_AXI_MBIIU_CTRL 0x510
229 #define SDHCI_GM_WR_OSRC_LMT 0x03000000
230 #define SDHCI_GM_RD_OSRC_LMT 0x00030000
231 #define SDHCI_UNDEFL_INCR_EN 0x00000001
232
233 /* 0x52c */
234 #define SDHCI_EMMC_CTRL 0x52c
235 #define SDHCI_ENH_STROBE_EN 0x0100
236 #define SDHCI_CARD_IS_EMMC 0x0001
237
238 /* 0x540 */
239 #define SDHCI_AT_CTRL 0x540
240 #define SDHCI_SAMPLE_EN 0x00000010
241
242 /* 0x544 */
243 #define SDHCI_AT_STAT 0x544
244 #define SDHCI_PHASE_SEL_MASK 0x000000ff
245
246 /* 0x54c */
247 #define SDHCI_MULTI_CYCLE 0x54c
248 #define SDHCI_FOUND_EDGE 0x00000800
249 #define SDHCI_DOUT_EN_F_EDGE 0x00000040
250 #define SDHCI_EDGE_DETECT_EN 0x00000100
251 #define SDHCI_DATA_DLY_EN 0x00000008
252 #define SDHCI_CMD_DLY_EN 0x00000004
253
254 #define SDHCI_GET_VERSION(x) (x->version & SDHCI_SPEC_VER_MASK)
255
256 /*
257 * End of controller registers.
258 */
259
260 #define SDHCI_MAX_DIV_SPEC_200 256
261 #define SDHCI_MAX_DIV_SPEC_300 2046
262
263 #define SDHCI_DMA_BOUNDARY_SIZE (0x1 << 27)
264
265 /*
266 * quirks
267 */
268 #define SDHCI_QUIRK_32BIT_DMA_ADDR (1 << 0)
269 #define SDHCI_QUIRK_REG32_RW (1 << 1)
270 #define SDHCI_QUIRK_BROKEN_R1B (1 << 2)
271 #define SDHCI_QUIRK_NO_HISPD_BIT (1 << 3)
272 #define SDHCI_QUIRK_BROKEN_VOLTAGE (1 << 4)
273 /*
274 * SDHCI_QUIRK_BROKEN_HISPD_MODE
275 * the hardware cannot operate correctly in high-speed mode,
276 * this quirk forces the sdhci host-controller to non high-speed mode
277 */
278 #define SDHCI_QUIRK_BROKEN_HISPD_MODE BIT(5)
279 #define SDHCI_QUIRK_WAIT_SEND_CMD (1 << 6)
280 #define SDHCI_QUIRK_USE_WIDE8 (1 << 8)
281 #define SDHCI_QUIRK_NO_1_8_V (1 << 9)
282
283 /* to make gcc happy */
284 struct sdhci_host;
285
286 /*
287 * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
288 */
289 #define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024)
290 #define SDHCI_DEFAULT_BOUNDARY_ARG (7)
291 struct sdhci_ops {
292 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
293 u32 (*read_l)(struct sdhci_host *host, int reg);
294 u16 (*read_w)(struct sdhci_host *host, int reg);
295 u8 (*read_b)(struct sdhci_host *host, int reg);
296 void (*write_l)(struct sdhci_host *host, u32 val, int reg);
297 void (*write_w)(struct sdhci_host *host, u16 val, int reg);
298 void (*write_b)(struct sdhci_host *host, u8 val, int reg);
299 #endif
300 int (*get_cd)(struct sdhci_host *host);
301 void (*set_control_reg)(struct sdhci_host *host);
302 int (*set_ios_post)(struct sdhci_host *host);
303 void (*set_clock)(struct sdhci_host *host, u32 div);
304 void (*set_delay)(struct sdhci_host *host);
305 };
306
307 #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
308 #define ADMA_MAX_LEN 65532
309 #ifdef CONFIG_DMA_ADDR_T_64BIT
310 #define ADMA_DESC_LEN 16
311 #else
312 #define ADMA_DESC_LEN 8
313 #endif
314 #define ADMA_TABLE_NO_ENTRIES (CONFIG_SYS_MMC_MAX_BLK_COUNT * \
315 MMC_MAX_BLOCK_LEN) / ADMA_MAX_LEN
316
317 #define ADMA_TABLE_SZ (ADMA_TABLE_NO_ENTRIES * ADMA_DESC_LEN)
318
319 /* Decriptor table defines */
320 #define ADMA_DESC_ATTR_VALID BIT(0)
321 #define ADMA_DESC_ATTR_END BIT(1)
322 #define ADMA_DESC_ATTR_INT BIT(2)
323 #define ADMA_DESC_ATTR_ACT1 BIT(4)
324 #define ADMA_DESC_ATTR_ACT2 BIT(5)
325
326 #define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2
327 #define ADMA_DESC_LINK_DESC (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
328
329 struct sdhci_adma_desc {
330 u8 attr;
331 u8 reserved;
332 u16 len;
333 u32 addr_lo;
334 #ifdef CONFIG_DMA_ADDR_T_64BIT
335 u32 addr_hi;
336 #endif
337 } __packed;
338 #endif
339 struct sdhci_host {
340 const char *name;
341 void *ioaddr;
342 unsigned int quirks;
343 unsigned int host_caps;
344 unsigned int version;
345 unsigned int max_clk; /* Maximum Base Clock frequency */
346 unsigned int clk_mul; /* Clock Multiplier value */
347 unsigned int clock;
348 struct mmc *mmc;
349 const struct sdhci_ops *ops;
350 int index;
351
352 int bus_width;
353 struct gpio_desc pwr_gpio; /* Power GPIO */
354 struct gpio_desc cd_gpio; /* Card Detect GPIO */
355
356 void (*set_control_reg)(struct sdhci_host *host);
357 int (*set_clock)(struct sdhci_host *host, unsigned int clk);
358 #ifdef MMC_SUPPORTS_TUNING
359 int (*execute_tuning)(struct sdhci_host *host, unsigned int opcode);
360 #endif
361 void (*priv_init)(struct sdhci_host *host);
362 uint voltages;
363
364 struct mmc_config cfg;
365 dma_addr_t start_addr;
366 int flags;
367 #define USE_SDMA (0x1 << 0)
368 #define USE_ADMA (0x1 << 1)
369 #define USE_ADMA64 (0x1 << 2)
370 #define USE_DMA (USE_SDMA | USE_ADMA | USE_ADMA64)
371 dma_addr_t adma_addr;
372 #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
373 struct sdhci_adma_desc *adma_desc_table;
374 uint desc_slot;
375 #endif
376 unsigned int type;
377 #define MMC_TYPE_MMC 0 /* MMC card */
378 #define MMC_TYPE_SD 1 /* SD card */
379 unsigned int is_tuning;
380 unsigned int tuning_phase;
381 };
382
383 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
384
sdhci_writel(struct sdhci_host * host,u32 val,int reg)385 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
386 {
387 if (unlikely(host->ops->write_l))
388 host->ops->write_l(host, val, reg);
389 else
390 writel(val, host->ioaddr + reg);
391 }
392
sdhci_writew(struct sdhci_host * host,u16 val,int reg)393 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
394 {
395 if (unlikely(host->ops->write_w))
396 host->ops->write_w(host, val, reg);
397 else
398 writew(val, host->ioaddr + reg);
399 }
400
sdhci_writeb(struct sdhci_host * host,u8 val,int reg)401 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
402 {
403 if (unlikely(host->ops->write_b))
404 host->ops->write_b(host, val, reg);
405 else
406 writeb(val, host->ioaddr + reg);
407 }
408
sdhci_readl(struct sdhci_host * host,int reg)409 static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
410 {
411 if (unlikely(host->ops->read_l))
412 return host->ops->read_l(host, reg);
413 else
414 return readl(host->ioaddr + reg);
415 }
416
sdhci_readw(struct sdhci_host * host,int reg)417 static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
418 {
419 if (unlikely(host->ops->read_w))
420 return host->ops->read_w(host, reg);
421 else
422 return readw(host->ioaddr + reg);
423 }
424
sdhci_readb(struct sdhci_host * host,int reg)425 static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
426 {
427 if (unlikely(host->ops->read_b))
428 return host->ops->read_b(host, reg);
429 else
430 return readb(host->ioaddr + reg);
431 }
432
433 #else
434
sdhci_writel(struct sdhci_host * host,u32 val,int reg)435 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
436 {
437 writel(val, host->ioaddr + reg);
438 }
439
sdhci_writew(struct sdhci_host * host,u16 val,int reg)440 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
441 {
442 writew(val, host->ioaddr + reg);
443 }
444
sdhci_writeb(struct sdhci_host * host,u8 val,int reg)445 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
446 {
447 writeb(val, host->ioaddr + reg);
448 }
sdhci_readl(struct sdhci_host * host,int reg)449 static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
450 {
451 return readl(host->ioaddr + reg);
452 }
453
sdhci_readw(struct sdhci_host * host,int reg)454 static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
455 {
456 return readw(host->ioaddr + reg);
457 }
458
sdhci_readb(struct sdhci_host * host,int reg)459 static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
460 {
461 return readb(host->ioaddr + reg);
462 }
463 #endif
464
465 #ifdef CONFIG_BLK
466 /**
467 * sdhci_setup_cfg() - Set up the configuration for DWMMC
468 *
469 * This is used to set up an SDHCI device when you are using CONFIG_BLK.
470 *
471 * This should be called from your MMC driver's probe() method once you have
472 * the information required.
473 *
474 * Generally your driver will have a platform data structure which holds both
475 * the configuration (struct mmc_config) and the MMC device info (struct mmc).
476 * For example:
477 *
478 * struct msm_sdhc_plat {
479 * struct mmc_config cfg;
480 * struct mmc mmc;
481 * };
482 *
483 * ...
484 *
485 * Inside U_BOOT_DRIVER():
486 * .platdata_auto_alloc_size = sizeof(struct msm_sdhc_plat),
487 *
488 * To access platform data:
489 * struct msm_sdhc_plat *plat = dev_get_platdata(dev);
490 *
491 * See msm_sdhci.c for an example.
492 *
493 * @cfg: Configuration structure to fill in (generally &plat->mmc)
494 * @host: SDHCI host structure
495 * @f_max: Maximum supported clock frequency in HZ (0 for default)
496 * @f_min: Minimum supported clock frequency in HZ (0 for default)
497 */
498 int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
499 u32 f_max, u32 f_min);
500
501 /**
502 * sdhci_bind() - Set up a new MMC block device
503 *
504 * This is used to set up an SDHCI block device when you are using CONFIG_BLK.
505 * It should be called from your driver's bind() method.
506 *
507 * See msm_sdhci.c for an example.
508 *
509 * @dev: Device to set up
510 * @mmc: Pointer to mmc structure (normally &plat->mmc)
511 * @cfg: Empty configuration structure (generally &plat->cfg). This is
512 * normally all zeroes at this point. The only purpose of passing
513 * this in is to set mmc->cfg to it.
514 * @return 0 if OK, -ve if the block device could not be created
515 */
516 int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);
517 #else
518
519 /**
520 * add_sdhci() - Add a new SDHCI interface
521 *
522 * This is used when you are not using CONFIG_BLK. Convert your driver over!
523 *
524 * @host: SDHCI host structure
525 * @f_max: Maximum supported clock frequency in HZ (0 for default)
526 * @f_min: Minimum supported clock frequency in HZ (0 for default)
527 * @return 0 if OK, -ve on error
528 */
529 int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min);
530 #endif /* !CONFIG_BLK */
531
532 void sdhci_set_uhs_timing(struct sdhci_host *host);
533 #ifdef CONFIG_DM_MMC
534 /* Export the operations to drivers */
535 int sdhci_probe(struct udevice *dev);
536 int sdhci_set_clock(struct mmc *mmc, unsigned int clock);
537 extern const struct dm_mmc_ops sdhci_ops;
538 #else
539 #endif
540
541 #endif /* __SDHCI_HW_H */
542