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/kernel/linux/linux-5.10/arch/arm/mach-davinci/
Dda850.c2 * TI DA850/OMAP-L138 chip specific setup
4 * Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com/
6 * Derived from: arch/arm/mach-davinci/da830.c
15 #include <linux/clk-provider.h>
22 #include <linux/irqchip/irq-davinci-cp-intc.h>
23 #include <linux/mfd/da8xx-cfgchip.h>
24 #include <linux/platform_data/clk-da8xx-cfgchip.h>
25 #include <linux/platform_data/clk-davinci-pll.h>
26 #include <linux/platform_data/davinci-cpufreq.h>
27 #include <linux/platform_data/gpio-davinci.h>
[all …]
/kernel/linux/linux-4.19/arch/arm/mach-davinci/
Dda850.c2 * TI DA850/OMAP-L138 chip specific setup
4 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
6 * Derived from: arch/arm/mach-davinci/da830.c
15 #include <linux/clk-provider.h>
21 #include <linux/mfd/da8xx-cfgchip.h>
22 #include <linux/platform_data/clk-da8xx-cfgchip.h>
23 #include <linux/platform_data/clk-davinci-pll.h>
24 #include <linux/platform_data/gpio-davinci.h>
41 #define DA850_PLL1_BASE 0x01e1a000
42 #define DA850_TIMER64P2_BASE 0x01f0c000
[all …]
/kernel/linux/linux-5.10/include/linux/mfd/wm831x/
Dotp.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * include/linux/mfd/wm831x/otp.h -- OTP interface for WM831x
17 * R30720 (0x7800) - Unique ID 1
19 #define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
20 #define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
21 #define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
24 * R30721 (0x7801) - Unique ID 2
26 #define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
27 #define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
28 #define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
[all …]
Dregulator.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/mfd/wm831x/regulator.h -- Regulator definitons for wm831x
14 * R16462 (0x404E) - Current Sink 1
16 #define WM831X_CS1_ENA 0x8000 /* CS1_ENA */
17 #define WM831X_CS1_ENA_MASK 0x8000 /* CS1_ENA */
18 #define WM831X_CS1_ENA_SHIFT 15 /* CS1_ENA */
20 #define WM831X_CS1_DRIVE 0x4000 /* CS1_DRIVE */
21 #define WM831X_CS1_DRIVE_MASK 0x4000 /* CS1_DRIVE */
24 #define WM831X_CS1_SLPENA 0x1000 /* CS1_SLPENA */
25 #define WM831X_CS1_SLPENA_MASK 0x1000 /* CS1_SLPENA */
[all …]
/kernel/linux/linux-4.19/include/linux/mfd/wm831x/
Dotp.h2 * include/linux/mfd/wm831x/otp.h -- OTP interface for WM831x
22 * R30720 (0x7800) - Unique ID 1
24 #define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
25 #define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
26 #define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
29 * R30721 (0x7801) - Unique ID 2
31 #define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
32 #define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
33 #define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
36 * R30722 (0x7802) - Unique ID 3
[all …]
Dregulator.h2 * linux/mfd/wm831x/regulator.h -- Regulator definitons for wm831x
19 * R16462 (0x404E) - Current Sink 1
21 #define WM831X_CS1_ENA 0x8000 /* CS1_ENA */
22 #define WM831X_CS1_ENA_MASK 0x8000 /* CS1_ENA */
23 #define WM831X_CS1_ENA_SHIFT 15 /* CS1_ENA */
25 #define WM831X_CS1_DRIVE 0x4000 /* CS1_DRIVE */
26 #define WM831X_CS1_DRIVE_MASK 0x4000 /* CS1_DRIVE */
29 #define WM831X_CS1_SLPENA 0x1000 /* CS1_SLPENA */
30 #define WM831X_CS1_SLPENA_MASK 0x1000 /* CS1_SLPENA */
33 #define WM831X_CS1_OFF_RAMP_MASK 0x0C00 /* CS1_OFF_RAMP - [11:10] */
[all …]
/kernel/linux/linux-5.10/sound/soc/codecs/
Dwm5100.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * wm5100.h -- WM5100 ALSA SoC Audio driver
26 #define WM5100_CLKSRC_MCLK1 0
34 #define WM5100_CLKSRC_ASYNCCLK 0x100
39 #define WM5100_FLL_SRC_MCLK1 0x0
40 #define WM5100_FLL_SRC_MCLK2 0x1
41 #define WM5100_FLL_SRC_FLL1 0x4
42 #define WM5100_FLL_SRC_FLL2 0x5
43 #define WM5100_FLL_SRC_AIF1BCLK 0x8
44 #define WM5100_FLL_SRC_AIF2BCLK 0x9
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Dwm9081.h1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * wm9081.c -- WM9081 ALSA SoC Audio driver
24 #define WM9081_SOFTWARE_RESET 0x00
25 #define WM9081_ANALOGUE_LINEOUT 0x02
26 #define WM9081_ANALOGUE_SPEAKER_PGA 0x03
27 #define WM9081_VMID_CONTROL 0x04
28 #define WM9081_BIAS_CONTROL_1 0x05
29 #define WM9081_ANALOGUE_MIXER 0x07
30 #define WM9081_ANTI_POP_CONTROL 0x08
31 #define WM9081_ANALOGUE_SPEAKER_1 0x09
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Drt5660.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5660.h -- RT5660 ALSA SoC audio driver
16 #define RT5660_RESET 0x00
17 #define RT5660_VENDOR_ID 0xfd
18 #define RT5660_VENDOR_ID1 0xfe
19 #define RT5660_VENDOR_ID2 0xff
20 /* I/O - Output */
21 #define RT5660_SPK_VOL 0x01
22 #define RT5660_LOUT_VOL 0x02
23 /* I/O - Input */
[all …]
/kernel/linux/linux-4.19/sound/soc/codecs/
Dwm5100.h2 * wm5100.h -- WM5100 ALSA SoC Audio driver
30 #define WM5100_CLKSRC_MCLK1 0
38 #define WM5100_CLKSRC_ASYNCCLK 0x100
43 #define WM5100_FLL_SRC_MCLK1 0x0
44 #define WM5100_FLL_SRC_MCLK2 0x1
45 #define WM5100_FLL_SRC_FLL1 0x4
46 #define WM5100_FLL_SRC_FLL2 0x5
47 #define WM5100_FLL_SRC_AIF1BCLK 0x8
48 #define WM5100_FLL_SRC_AIF2BCLK 0x9
49 #define WM5100_FLL_SRC_AIF3BCLK 0xa
[all …]
Dwm9081.h5 * wm9081.c -- WM9081 ALSA SoC Audio driver
27 #define WM9081_SOFTWARE_RESET 0x00
28 #define WM9081_ANALOGUE_LINEOUT 0x02
29 #define WM9081_ANALOGUE_SPEAKER_PGA 0x03
30 #define WM9081_VMID_CONTROL 0x04
31 #define WM9081_BIAS_CONTROL_1 0x05
32 #define WM9081_ANALOGUE_MIXER 0x07
33 #define WM9081_ANTI_POP_CONTROL 0x08
34 #define WM9081_ANALOGUE_SPEAKER_1 0x09
35 #define WM9081_ANALOGUE_SPEAKER_2 0x0A
[all …]
Drt5660.h2 * rt5660.h -- RT5660 ALSA SoC audio driver
19 #define RT5660_RESET 0x00
20 #define RT5660_VENDOR_ID 0xfd
21 #define RT5660_VENDOR_ID1 0xfe
22 #define RT5660_VENDOR_ID2 0xff
23 /* I/O - Output */
24 #define RT5660_SPK_VOL 0x01
25 #define RT5660_LOUT_VOL 0x02
26 /* I/O - Input */
27 #define RT5660_IN1_IN2 0x0d
[all …]
/kernel/linux/linux-5.10/arch/csky/abiv2/inc/abi/
Dckmmu.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
12 return mfcr("cr<0, 15>"); in read_mmu_index()
17 mtcr("cr<0, 15>", value); in write_mmu_index()
22 return mfcr("cr<2, 15>"); in read_mmu_entrylo0()
27 return mfcr("cr<3, 15>"); in read_mmu_entrylo1()
32 mtcr("cr<6, 15>", value); in write_mmu_pagemask()
37 return mfcr("cr<4, 15>"); in read_mmu_entryhi()
42 mtcr("cr<4, 15>", value); in write_mmu_entryhi()
47 return mfcr("cr<30, 15>"); in read_mmu_msa0()
[all …]
/kernel/linux/linux-4.19/arch/s390/include/asm/
Dvx-insn.h1 /* SPDX-License-Identifier: GPL-2.0 */
20 /* GR_NUM - Retrieve general-purpose register number
28 \opd = 0
73 \opd = 15
80 /* VX_NUM - Retrieve vector register number
92 \opd = 0
137 \opd = 15
192 /* RXB - Compute most significant bit used vector registers
200 .macro RXB rxb v1 v2=0 v3=0 v4=0
201 \rxb = 0
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/kernel/linux/linux-5.10/arch/s390/include/asm/
Dvx-insn.h1 /* SPDX-License-Identifier: GPL-2.0 */
20 /* GR_NUM - Retrieve general-purpose register number
28 \opd = 0
73 \opd = 15
80 /* VX_NUM - Retrieve vector register number
92 \opd = 0
137 \opd = 15
192 /* RXB - Compute most significant bit used vector registers
200 .macro RXB rxb v1 v2=0 v3=0 v4=0
201 \rxb = 0
[all …]
/kernel/linux/linux-5.10/drivers/video/fbdev/nvidia/
Dnv_dma.h8 |* hereby granted a nonexclusive, royalty-free copyright license to *|
11 |* Any use of this source code must include, in the user documenta- *|
19 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
21 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
23 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
24 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
33 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
35 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
42 * GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/
43 * XFree86 'nv' driver, this source code is provided under MIT-style licensing
[all …]
/kernel/linux/linux-4.19/drivers/video/fbdev/nvidia/
Dnv_dma.h8 |* hereby granted a nonexclusive, royalty-free copyright license to *|
11 |* Any use of this source code must include, in the user documenta- *|
19 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
21 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
23 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
24 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
33 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
35 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
42 * GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/
43 * XFree86 'nv' driver, this source code is provided under MIT-style licensing
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Domap3-echo.dts1 // SPDX-License-Identifier: GPL-2.0-only
5 /dts-v1/;
9 #include <dt-bindings/input/input.h>
13 compatible = "amazon,omap3-echo", "ti,omap3630", "ti,omap3";
16 cpu@0 {
17 cpu0-supply = <&vdd1_reg>;
23 reg = <0x80000000 0xc600000>; /* 198 MB */
27 compatible = "regulator-fixed";
28 regulator-name = "vcc5v";
29 regulator-min-microvolt = <5000000>;
[all …]
/kernel/linux/linux-5.10/arch/csky/kernel/probes/
Dsimulate-insn.c1 // SPDX-License-Identifier: GPL-2.0+
7 #include "decode-insn.h"
8 #include "simulate-insn.h"
15 *ptr = *(&regs->a0 + index); in csky_insn_reg_get_val()
17 if (index > 15 && index < 31) in csky_insn_reg_get_val()
18 *ptr = *(&regs->exregs[0] + index - 16); in csky_insn_reg_get_val()
22 *ptr = regs->usp; in csky_insn_reg_get_val()
24 case 15: in csky_insn_reg_get_val()
25 *ptr = regs->lr; in csky_insn_reg_get_val()
28 *ptr = regs->tls; in csky_insn_reg_get_val()
[all …]
/kernel/linux/linux-5.10/Documentation/ABI/testing/
Dsysfs-class-rapidio3 On-chip RapidIO controllers and PCIe-to-RapidIO bridges
15 KernelVersion: v3.15
21 0 = small (8-bit destination ID, max. 256 devices),
23 1 = large (16-bit destination ID, max. 65536 devices).
27 KernelVersion: v3.15
33 RapidIO mport device. If value 0xFFFFFFFF is returned this means
46 [rio@rapidio ~]$ ls /sys/class/rapidio_port/rapidio0/ -l
47 total 0
48 drwxr-xr-x 3 root root 0 Feb 11 15:10 00:e:0001
49 drwxr-xr-x 3 root root 0 Feb 11 15:10 00:e:0004
[all …]
/kernel/linux/linux-4.19/Documentation/ABI/testing/
Dsysfs-class-rapidio3 On-chip RapidIO controllers and PCIe-to-RapidIO bridges
14 KernelVersion: v3.15
19 0 = small (8-bit destination ID, max. 256 devices),
20 1 = large (16-bit destination ID, max. 65536 devices).
24 KernelVersion: v3.15
29 RapidIO mport device. If value 0xFFFFFFFF is returned this means
42 [rio@rapidio ~]$ ls /sys/class/rapidio_port/rapidio0/ -l
43 total 0
44 drwxr-xr-x 3 root root 0 Feb 11 15:10 00:e:0001
45 drwxr-xr-x 3 root root 0 Feb 11 15:10 00:e:0004
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
Dintel_vdsc.c1 // SPDX-License-Identifier: MIT
15 ROW_INDEX_6BPP = 0,
24 COLUMN_INDEX_8BPC = 0,
56 { 768, 15, 6144, 3, 13, 11, 11, {
57 { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
58 { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
59 { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
60 { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
64 { 768, 15, 6144, 7, 17, 15, 15, {
65 { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
[all …]
/kernel/linux/linux-4.19/drivers/infiniband/hw/i40iw/
Di40iw_register.h3 * Copyright (c) 2015-2016 Intel Corporation. All rights reserved.
15 * - Redistributions of source code must retain the above
19 * - Redistributions in binary form must reproduce the above
38 #define I40E_GLGEN_STAT 0x000B612C /* Reset: POR */
40 #define I40E_PFHMC_PDINV 0x000C0300 /* Reset: PFR */
41 #define I40E_PFHMC_PDINV_PMSDIDX_SHIFT 0
42 #define I40E_PFHMC_PDINV_PMSDIDX_MASK (0xFFF << I40E_PFHMC_PDINV_PMSDIDX_SHIFT)
44 #define I40E_PFHMC_PDINV_PMPDIDX_MASK (0x1FF << I40E_PFHMC_PDINV_PMPDIDX_SHIFT)
46 #define I40E_PFHMC_SDCMD_PMSDWR_MASK (0x1 << I40E_PFHMC_SDCMD_PMSDWR_SHIFT)
47 #define I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT 0
[all …]
/kernel/linux/linux-5.10/drivers/infiniband/hw/i40iw/
Di40iw_register.h3 * Copyright (c) 2015-2016 Intel Corporation. All rights reserved.
15 * - Redistributions of source code must retain the above
19 * - Redistributions in binary form must reproduce the above
38 #define I40E_GLGEN_STAT 0x000B612C /* Reset: POR */
40 #define I40E_PFHMC_PDINV 0x000C0300 /* Reset: PFR */
41 #define I40E_PFHMC_PDINV_PMSDIDX_SHIFT 0
42 #define I40E_PFHMC_PDINV_PMSDIDX_MASK (0xFFF << I40E_PFHMC_PDINV_PMSDIDX_SHIFT)
44 #define I40E_PFHMC_PDINV_PMPDIDX_MASK (0x1FF << I40E_PFHMC_PDINV_PMPDIDX_SHIFT)
46 #define I40E_PFHMC_SDCMD_PMSDWR_MASK (0x1 << I40E_PFHMC_SDCMD_PMSDWR_SHIFT)
47 #define I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT 0
[all …]
/kernel/linux/linux-5.10/arch/arm64/include/asm/
Darm_dsu_pmu.h1 /* SPDX-License-Identifier: GPL-2.0-only */
18 #define CLUSTERPMCR_EL1 sys_reg(3, 0, 15, 5, 0)
19 #define CLUSTERPMCNTENSET_EL1 sys_reg(3, 0, 15, 5, 1)
20 #define CLUSTERPMCNTENCLR_EL1 sys_reg(3, 0, 15, 5, 2)
21 #define CLUSTERPMOVSSET_EL1 sys_reg(3, 0, 15, 5, 3)
22 #define CLUSTERPMOVSCLR_EL1 sys_reg(3, 0, 15, 5, 4)
23 #define CLUSTERPMSELR_EL1 sys_reg(3, 0, 15, 5, 5)
24 #define CLUSTERPMINTENSET_EL1 sys_reg(3, 0, 15, 5, 6)
25 #define CLUSTERPMINTENCLR_EL1 sys_reg(3, 0, 15, 5, 7)
26 #define CLUSTERPMCCNTR_EL1 sys_reg(3, 0, 15, 6, 0)
[all …]

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