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/kernel/linux/linux-5.10/drivers/mtd/spi-nor/
Dmicron-st.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/mtd/spi-nor.h>
12 { "mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512,
15 { "mt35xu02g", INFO(0x2c5b1c, 0, 128 * 1024, 2048,
21 { "n25q016a", INFO(0x20bb15, 0, 64 * 1024, 32,
23 { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64,
25 { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64,
27 { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128,
29 { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128,
31 { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256,
[all …]
Dwinbond.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/mtd/spi-nor.h>
19 * Unfortunately, Winbond has re-used the same JEDEC ID for both in w25q256_post_bfpt_fixups()
25 if (bfpt_header->major == SFDP_JESD216_MAJOR && in w25q256_post_bfpt_fixups()
26 bfpt_header->minor == SFDP_JESD216A_MINOR) in w25q256_post_bfpt_fixups()
27 nor->flags |= SNOR_F_4B_OPCODES; in w25q256_post_bfpt_fixups()
29 return 0; in w25q256_post_bfpt_fixups()
37 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
38 { "w25x05", INFO(0xef3010, 0, 64 * 1024, 1, SECT_4K) },
39 { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
[all …]
Dmacronix.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/mtd/spi-nor.h>
19 * Unfortunately, Macronix has re-used the same JEDEC ID for both in mx25l25635_post_bfpt_fixups()
23 * seems that the F version advertises support for Fast Read 4-4-4 in in mx25l25635_post_bfpt_fixups()
26 if (bfpt->dwords[BFPT_DWORD(5)] & BFPT_DWORD5_FAST_READ_4_4_4) in mx25l25635_post_bfpt_fixups()
27 nor->flags |= SNOR_F_4B_OPCODES; in mx25l25635_post_bfpt_fixups()
29 return 0; in mx25l25635_post_bfpt_fixups()
38 { "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) },
39 { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },
40 { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
[all …]
Dspansion.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/mtd/spi-nor.h>
18 * The S25FS-S chip family reports 512-byte pages in BFPT but in s25fs_s_post_bfpt_fixups()
23 params->page_size = 256; in s25fs_s_post_bfpt_fixups()
25 return 0; in s25fs_s_post_bfpt_fixups()
33 /* Spansion/Cypress -- single (large) sector size only, at least
36 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64,
38 { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128,
40 { "s25fl128s0", INFO6(0x012018, 0x4d0080, 256 * 1024, 64,
43 { "s25fl128s1", INFO6(0x012018, 0x4d0180, 64 * 1024, 256,
[all …]
Deon.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/mtd/spi-nor.h>
12 /* EON -- en25xxx */
13 { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) },
14 { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) },
15 { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
16 { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
17 { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
18 { "en25q80a", INFO(0x1c3014, 0, 64 * 1024, 16,
20 { "en25qh16", INFO(0x1c7015, 0, 64 * 1024, 32,
[all …]
Dissi.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/mtd/spi-nor.h>
22 if ((bfpt->dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) == in is25lp256_post_bfpt_fixups()
24 nor->addr_width = 4; in is25lp256_post_bfpt_fixups()
26 return 0; in is25lp256_post_bfpt_fixups()
35 { "is25cd512", INFO(0x7f9d20, 0, 32 * 1024, 2, SECT_4K) },
36 { "is25lq040b", INFO(0x9d4013, 0, 64 * 1024, 8,
38 { "is25lp016d", INFO(0x9d6015, 0, 64 * 1024, 32,
40 { "is25lp080d", INFO(0x9d6014, 0, 64 * 1024, 16,
42 { "is25lp032", INFO(0x9d6016, 0, 64 * 1024, 64,
[all …]
Datmel.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/mtd/spi-nor.h>
19 return -EOPNOTSUPP; in atmel_at25fs_lock()
27 if (ofs || len != nor->params->size) in atmel_at25fs_unlock()
28 return -EINVAL; in atmel_at25fs_unlock()
30 /* Write 0x00 to the status register to disable write protection */ in atmel_at25fs_unlock()
31 ret = spi_nor_write_sr_and_check(nor, 0); in atmel_at25fs_unlock()
33 dev_dbg(nor->dev, "unable to clear BP bits, WP# asserted?\n"); in atmel_at25fs_unlock()
40 return -EOPNOTSUPP; in atmel_at25fs_is_locked()
51 nor->params->locking_ops = &atmel_at25fs_locking_ops; in atmel_at25fs_default_init()
[all …]
/kernel/linux/linux-4.19/drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_8822b/
Dhalmac_func_8822b.c1 // SPDX-License-Identifier: GPL-2.0
105 {HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 64, 1},
107 {HALMAC_TRX_MODE_WMM, 64, 64, 64, 64, 1},
108 {HALMAC_TRX_MODE_P2P, 64, 64, 64, 64, 1},
109 {HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 64, 640},
110 {HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 64, 640},
116 {HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 64, 1},
117 {HALMAC_TRX_MODE_TRXSHARE, 64, 64, 64, 64, 1},
118 {HALMAC_TRX_MODE_WMM, 64, 64, 64, 64, 1},
119 {HALMAC_TRX_MODE_P2P, 64, 64, 64, 64, 1},
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dtegra30-cpu-opp.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 compatible = "operating-points-v2";
6 opp-shared;
9 clock-latency-ns = <100000>;
10 opp-supported-hw = <0x1F 0x31FE>;
11 opp-hz = /bits/ 64 <51000000>;
15 clock-latency-ns = <100000>;
16 opp-supported-hw = <0x1F 0x0C01>;
17 opp-hz = /bits/ 64 <51000000>;
21 clock-latency-ns = <100000>;
[all …]
Dtegra20-cpu-opp.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 compatible = "operating-points-v2";
6 opp-shared;
9 clock-latency-ns = <400000>;
10 opp-supported-hw = <0x0F 0x0003>;
11 opp-hz = /bits/ 64 <216000000>;
15 clock-latency-ns = <400000>;
16 opp-supported-hw = <0x0F 0x0004>;
17 opp-hz = /bits/ 64 <216000000>;
21 clock-latency-ns = <400000>;
[all …]
/kernel/linux/linux-5.10/arch/arm/crypto/
Dsha512-core.S_shipped1 @ SPDX-License-Identifier: GPL-2.0
21 @ by gcc 3.4 and it spends ~72 clock cycles per byte [on single-issue
26 @ Rescheduling for dual-issue pipeline resulted in 6% improvement on
31 @ Profiler-assisted and platform-specific optimization resulted in 7%
37 @ one byte in 23.3 cycles or ~60% faster than integer-only code.
43 @ Technical writers asserted that 3-way S4 pipeline can sustain
45 @ not be observed, see https://www.openssl.org/~appro/Snapdragon-S4.html
46 @ for further details. On side note Cortex-A15 processes one byte in
52 @ h[0-7], namely with most significant dword at *lower* address, which
53 @ was reflected in below two parameters as 0 and 4. Now caller is
[all …]
/kernel/linux/linux-4.19/arch/arm/crypto/
Dsha512-core.S_shipped1 @ SPDX-License-Identifier: GPL-2.0
21 @ by gcc 3.4 and it spends ~72 clock cycles per byte [on single-issue
26 @ Rescheduling for dual-issue pipeline resulted in 6% improvement on
31 @ Profiler-assisted and platform-specific optimization resulted in 7%
37 @ one byte in 23.3 cycles or ~60% faster than integer-only code.
43 @ Technical writers asserted that 3-way S4 pipeline can sustain
45 @ not be observed, see http://www.openssl.org/~appro/Snapdragon-S4.html
46 @ for further details. On side note Cortex-A15 processes one byte in
52 @ h[0-7], namely with most significant dword at *lower* address, which
53 @ was reflected in below two parameters as 0 and 4. Now caller is
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/opp/
Dkryo-cpufreq.txt8 defines the voltage and frequency value based on the msm-id in SMEM
10 The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC
13 operating-points-v2 table when it is parsed by the OPP framework.
16 --------------------
18 - operating-points-v2: Phandle to the operating-points-v2 table to use.
20 In 'operating-points-v2' table:
21 - compatible: Should be
22 - 'operating-points-v2-kryo-cpu' for apq8096 and msm8996.
23 - nvmem-cells: A phandle pointing to a nvmem-cells node representing the
27 Please refer the for nvmem-cells
[all …]
/kernel/linux/linux-5.10/tools/testing/selftests/drivers/net/mlxsw/
Dfib_offload.sh2 # SPDX-License-Identifier: GPL-2.0
6 lib_dir=$(dirname $0)/../../../net/forwarding
43 __addr_add_del $spine_p1 add 2001:db8:1::1/64
44 __addr_add_del $spine_p2 add 2001:db8:2::1/64
49 __addr_add_del $spine_p2 del 2001:db8:2::1/64
50 __addr_add_del $spine_p1 del 2001:db8:1::1/64
65 num=$(ip -6 route show match ${pfx} | grep "offload" | wc -l)
67 if [ $num -eq $expected_num ]; then
68 return 0
76 RET=0
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/opp/
Dqcom-nvmem-cpufreq.txt8 defines the voltage and frequency value based on the msm-id in SMEM
10 The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC
13 operating-points-v2 table when it is parsed by the OPP framework.
16 --------------------
18 - operating-points-v2: Phandle to the operating-points-v2 table to use.
20 In 'operating-points-v2' table:
21 - compatible: Should be
22 - 'operating-points-v2-kryo-cpu' for apq8096, msm8996, msm8974,
26 --------------------
28 - power-domains: A phandle pointing to the PM domain specifier which provides
[all …]
/kernel/linux/linux-5.10/tools/testing/selftests/net/forwarding/
Dfib_offload_lib.sh1 # SPDX-License-Identifier: GPL-2.0
13 ip -n $ns -j -p -$family route show $route \
14 | jq -e '.[]["flags"] | contains(["trap"])' &> /dev/null
17 if [[ $ret -ne 0 ]]; then
18 return 0
60 RET=0
63 ip -n $ns link add name dummy$i type dummy
64 ip -n $ns link set dev dummy$i up
67 ip -n $ns route add 192.0.2.0/24 dev dummy1 tos 0 metric 1024
68 fib4_trap_check $ns "192.0.2.0/24 dev dummy1 tos 0 metric 1024" false
[all …]
/kernel/linux/linux-5.10/drivers/mtd/nand/raw/
Dnand_ids.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #define LP_OPTIONS 0
20 * If page size and eraseblock size are 0, the sizes are taken from the
29 {"TC58NVG0S3E 1G 3.3V 8-bit",
30 { .id = {0x98, 0xd1, 0x90, 0x15, 0x76, 0x14, 0x01, 0x00} },
31 SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), },
32 {"TC58NVG2S0F 4G 3.3V 8-bit",
33 { .id = {0x98, 0xdc, 0x90, 0x26, 0x76, 0x15, 0x01, 0x08} },
34 SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) },
35 {"TC58NVG2S0H 4G 3.3V 8-bit",
[all …]
/kernel/linux/linux-4.19/drivers/mtd/nand/raw/
Dnand_ids.c12 #define LP_OPTIONS 0
22 * If page size and eraseblock size are 0, the sizes are taken from the
31 {"TC58NVG0S3E 1G 3.3V 8-bit",
32 { .id = {0x98, 0xd1, 0x90, 0x15, 0x76, 0x14, 0x01, 0x00} },
33 SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512),
35 {"TC58NVG2S0F 4G 3.3V 8-bit",
36 { .id = {0x98, 0xdc, 0x90, 0x26, 0x76, 0x15, 0x01, 0x08} },
37 SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) },
38 {"TC58NVG2S0H 4G 3.3V 8-bit",
39 { .id = {0x98, 0xdc, 0x90, 0x26, 0x76, 0x16, 0x08, 0x00} },
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/amazon/
Dalpine-v3.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "amazon,al-alpine-v3";
14 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 #address-cells = <1>;
21 #size-cells = <0>;
23 cpu@0 {
[all …]
/kernel/linux/linux-4.19/drivers/mtd/spi-nor/
Dspi-nor.c25 #include <linux/mtd/spi-nor.h>
30 * For everything but full-chip erase; probably could be much smaller, but kept
36 * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up
65 #define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */
80 * Xilinx Spartan 3AN In-System Flash
96 #define JEDEC_MFR(info) ((info)->id[0])
110 ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1); in read_sr()
111 if (ret < 0) { in read_sr()
129 ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1); in read_fsr()
130 if (ret < 0) { in read_fsr()
[all …]
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/ivytown/
Duncore-cache.json4 "Counter": "0,1,2,3",
10 … "BriefDescription": "All LLC Misses (code+ data rd + data wr - including demand and prefetch)",
11 "Counter": "0,1",
12 "EventCode": "0x34",
14 "Filter": "filter_state=0x1",
16 "ScaleUnit": "64Bytes",
17 "UMask": "0x11",
22 "Counter": "0,1",
23 "EventCode": "0x37",
26 "ScaleUnit": "64Bytes",
[all …]
/kernel/linux/linux-4.19/tools/perf/pmu-events/arch/x86/ivytown/
Duncore-cache.json4 "Counter": "0,1,2,3",
10 … "BriefDescription": "All LLC Misses (code+ data rd + data wr - including demand and prefetch)",
11 "Counter": "0,1",
12 "EventCode": "0x34",
14 "Filter": "filter_state=0x1",
16 "ScaleUnit": "64Bytes",
17 "UMask": "0x11",
22 "Counter": "0,1",
23 "EventCode": "0x37",
26 "ScaleUnit": "64Bytes",
[all …]
/kernel/linux/linux-5.10/arch/arm64/lib/
Dcsum.c1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2019-2020 Arm Ltd.
5 #include <linux/kasan-checks.h>
10 /* Looks dumb, but generates nice-ish code */
14 return tmp + (tmp >> 64); in accumulate()
18 * We over-read the buffer and this makes KASAN unhappy. Instead, disable
25 u64 data, sum64 = 0; in do_csum()
27 if (unlikely(len == 0)) in do_csum()
28 return 0; in do_csum()
34 * should absolutely not be pointing to anything read-sensitive. We do, in do_csum()
[all …]
/kernel/linux/linux-4.19/lib/
Ddiv64.c1 // SPDX-License-Identifier: GPL-2.0
5 * Based on former do_div() implementation from asm-parisc/div64.h:
6 * Copyright (C) 1999 Hewlett-Packard Co
7 * Copyright (C) 1999 David Mosberger-Tang <davidm@hpl.hp.com>
10 * Generic C version of 64bit/32bit division and modulo, with
11 * 64bit result and 32bit remainder.
13 * The fast case for (n>>32 == 0) is handled inline by do_div().
16 * for some CPUs. __div64_32() can be overridden by linking arch-specific
25 /* Not needed on 64bit architectures */
37 res = 0; in __div64_32()
[all …]
/kernel/linux/linux-5.10/lib/raid6/
Drecov_avx512.c1 // SPDX-License-Identifier: GPL-2.0-only
30 const u8 x0f = 0x0f; in raid6_2data_recov_avx512()
32 p = (u8 *)ptrs[disks-2]; in raid6_2data_recov_avx512()
33 q = (u8 *)ptrs[disks-1]; in raid6_2data_recov_avx512()
43 ptrs[disks-2] = dp; in raid6_2data_recov_avx512()
46 ptrs[disks-1] = dq; in raid6_2data_recov_avx512()
53 ptrs[disks-2] = p; in raid6_2data_recov_avx512()
54 ptrs[disks-1] = q; in raid6_2data_recov_avx512()
57 pbmul = raid6_vgfmul[raid6_gfexi[failb-faila]]; in raid6_2data_recov_avx512()
64 asm volatile("vpbroadcastb %0, %%zmm7" : : "m" (x0f)); in raid6_2data_recov_avx512()
[all …]

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