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/kernel/linux/linux-5.10/arch/powerpc/include/asm/
Dmpic.h14 #define MPIC_GREG_BASE 0x01000
16 #define MPIC_GREG_FEATURE_0 0x00000
17 #define MPIC_GREG_FEATURE_LAST_SRC_MASK 0x07ff0000
19 #define MPIC_GREG_FEATURE_LAST_CPU_MASK 0x00001f00
21 #define MPIC_GREG_FEATURE_VERSION_MASK 0xff
22 #define MPIC_GREG_FEATURE_1 0x00010
23 #define MPIC_GREG_GLOBAL_CONF_0 0x00020
24 #define MPIC_GREG_GCONF_RESET 0x80000000
27 * 0b00 = pass through (interrupts routed to IRQ0)
28 * 0b01 = Mixed mode
[all …]
/kernel/linux/linux-4.19/arch/powerpc/include/asm/
Dmpic.h14 #define MPIC_GREG_BASE 0x01000
16 #define MPIC_GREG_FEATURE_0 0x00000
17 #define MPIC_GREG_FEATURE_LAST_SRC_MASK 0x07ff0000
19 #define MPIC_GREG_FEATURE_LAST_CPU_MASK 0x00001f00
21 #define MPIC_GREG_FEATURE_VERSION_MASK 0xff
22 #define MPIC_GREG_FEATURE_1 0x00010
23 #define MPIC_GREG_GLOBAL_CONF_0 0x00020
24 #define MPIC_GREG_GCONF_RESET 0x80000000
27 * 0b00 = pass through (interrupts routed to IRQ0)
28 * 0b01 = Mixed mode
[all …]
/kernel/linux/linux-5.10/drivers/media/common/b2c2/
Dflexcop-sram.c28 return 0; in flexcop_sram_init()
55 return 0; in flexcop_sram_set_dest()
75 #if 0
81 for (i = 0; i < len; i++) {
82 command = bank | addr | 0x04000000 | (*buf << 0x10);
86 while (((read_reg_dw(adapter, 0x700) & 0x80000000) != 0) && (retries > 0)) {
91 if (retries == 0)
94 write_reg_dw(adapter, 0x700, command);
106 for (i = 0; i < len; i++) {
107 command = bank | addr | 0x04008000;
[all …]
/kernel/linux/linux-4.19/drivers/media/common/b2c2/
Dflexcop-sram.c28 return 0; in flexcop_sram_init()
55 return 0; in flexcop_sram_set_dest()
75 #if 0
81 for (i = 0; i < len; i++) {
82 command = bank | addr | 0x04000000 | (*buf << 0x10);
86 while (((read_reg_dw(adapter, 0x700) & 0x80000000) != 0) && (retries > 0)) {
91 if (retries == 0)
94 write_reg_dw(adapter, 0x700, command);
106 for (i = 0; i < len; i++) {
107 command = bank | addr | 0x04008000;
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/arm/
Dmalidp_regs.h24 #define MALIDP_DE_IRQ_UNDERRUN (1 << 0)
38 #define MALIDP500_SE_IRQ_CONF_MODE (1 << 0)
54 #define MALIDP550_SE_IRQ_EOW (1 << 0)
58 #define MALIDP550_DC_IRQ_CONF_VALID (1 << 0)
71 #define MALIDP_CFG_VALID (1 << 0)
72 #define MALIDP_DISP_FUNC_GAMMA (1 << 0)
79 #define MALIDP_REG_STATUS 0x00000
80 #define MALIDP_REG_SETIRQ 0x00004
81 #define MALIDP_REG_MASKIRQ 0x00008
82 #define MALIDP_REG_CLEARIRQ 0x0000c
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/arm/
Dmalidp_regs.h20 #define MALIDP_DE_IRQ_UNDERRUN (1 << 0)
34 #define MALIDP500_SE_IRQ_CONF_MODE (1 << 0)
50 #define MALIDP550_SE_IRQ_EOW (1 << 0)
54 #define MALIDP550_DC_IRQ_CONF_VALID (1 << 0)
67 #define MALIDP_CFG_VALID (1 << 0)
68 #define MALIDP_DISP_FUNC_GAMMA (1 << 0)
75 #define MALIDP_REG_STATUS 0x00000
76 #define MALIDP_REG_SETIRQ 0x00004
77 #define MALIDP_REG_MASKIRQ 0x00008
78 #define MALIDP_REG_CLEARIRQ 0x0000c
[all …]
/kernel/linux/linux-5.10/drivers/clk/imx/
Dclk-imx8qxp-lpcg.h11 #define LSIO_PWM_0_LPCG 0x00000
12 #define LSIO_PWM_1_LPCG 0x10000
13 #define LSIO_PWM_2_LPCG 0x20000
14 #define LSIO_PWM_3_LPCG 0x30000
15 #define LSIO_PWM_4_LPCG 0x40000
16 #define LSIO_PWM_5_LPCG 0x50000
17 #define LSIO_PWM_6_LPCG 0x60000
18 #define LSIO_PWM_7_LPCG 0x70000
19 #define LSIO_GPIO_0_LPCG 0x80000
20 #define LSIO_GPIO_1_LPCG 0x90000
[all …]
/kernel/linux/linux-5.10/tools/perf/trace/beauty/tracepoints/
Dx86_msr.sh13 # Just the ones starting with 0x00000 so as to have a simple
17 …[[:space:]]*define[[:space:]]+MSR_([[:alnum:]][[:alnum:]_]+)[[:space:]]+(0x00000[[:xdigit:]]+)[[:s…
24 regex='^[[:space:]]*#[[:space:]]*define[[:space:]]+MSR_([[:alnum:]][[:alnum:]_]+)[[:space:]]+(0xc00…
33 regex='^[[:space:]]*#[[:space:]]*define[[:space:]]+MSR_([[:alnum:]][[:alnum:]_]+)[[:space:]]+(0xc00…
/kernel/linux/linux-5.10/sound/soc/fsl/
Dfsl_audmix.c38 SOC_ENUM_SINGLE_S(FSL_AUDMIX_ATCR0, 0, endis_sel),
41 SOC_ENUM_SINGLE_S(FSL_AUDMIX_ATCR1, 0, endis_sel),
53 { .tdms = 0, .clk = 0, .msg = "" },
59 { .tdms = 3, .clk = 0, .msg = "DIS->MIX: Please start both TDMs!\n" }
61 { .tdms = 1, .clk = 0, .msg = "TDM1->DIS: TDM1 not started!\n" },
63 { .tdms = 0, .clk = 0, .msg = "" },
67 { .tdms = 3, .clk = 0, .msg = "TDM1->MIX: Please start both TDMs!\n" }
69 { .tdms = 2, .clk = 0, .msg = "TDM2->DIS: TDM2 not started!\n" },
73 { .tdms = 0, .clk = 0, .msg = "" },
75 { .tdms = 3, .clk = 0, .msg = "TDM2->MIX: Please start both TDMs!\n" }
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-mv78xx0/
Dmv78xx0.h20 * f0800000 PCIe #0 I/O space
32 * fee00000 f0800000 64K PCIe #0 I/O space
42 #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000
43 #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000
44 #define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000)
45 #define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000
48 #define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20))
51 #define MV78XX0_REGS_PHYS_BASE 0xf1000000
52 #define MV78XX0_REGS_VIRT_BASE IOMEM(0xfec00000)
55 #define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000
[all …]
/kernel/linux/linux-4.19/arch/arm/mach-mv78xx0/
Dmv78xx0.h20 * f0800000 PCIe #0 I/O space
32 * fee00000 f0800000 64K PCIe #0 I/O space
42 #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000
43 #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000
44 #define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000)
45 #define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000
48 #define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20))
51 #define MV78XX0_REGS_PHYS_BASE 0xf1000000
52 #define MV78XX0_REGS_VIRT_BASE IOMEM(0xfd000000)
55 #define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/v3d/
Dv3d_regs.h14 WARN_ON((fieldval & ~field##_MASK) != 0); \
23 #define V3D_HUB_AXICFG 0x00000
24 # define V3D_HUB_AXICFG_MAX_LEN_MASK V3D_MASK(3, 0)
25 # define V3D_HUB_AXICFG_MAX_LEN_SHIFT 0
26 #define V3D_HUB_UIFCFG 0x00004
27 #define V3D_HUB_IDENT0 0x00008
29 #define V3D_HUB_IDENT1 0x0000c
40 # define V3D_HUB_IDENT1_TVER_MASK V3D_MASK(3, 0)
41 # define V3D_HUB_IDENT1_TVER_SHIFT 0
43 #define V3D_HUB_IDENT2 0x00010
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-dove/
Ddove.h19 * e0000000 @runtime 128M PCIe-0 Memory space
23 * f2000000 fee00000 1M PCIe-0 I/O space
27 #define DOVE_CESA_PHYS_BASE 0xc8000000
28 #define DOVE_CESA_VIRT_BASE IOMEM(0xfdb00000)
31 #define DOVE_PCIE0_MEM_PHYS_BASE 0xe0000000
34 #define DOVE_PCIE1_MEM_PHYS_BASE 0xe8000000
37 #define DOVE_BOOTROM_PHYS_BASE 0xf8000000
40 #define DOVE_SCRATCHPAD_PHYS_BASE 0xf0000000
41 #define DOVE_SCRATCHPAD_VIRT_BASE IOMEM(0xfdd00000)
44 #define DOVE_SB_REGS_PHYS_BASE 0xf1000000
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/pci/
Dgk104.c29 return (nvkm_rd32(pci->subdev.device, 0x8c1c0) & 0x4) == 0x4 ? 2 : 1; in gk104_pcie_version_supported()
40 nvkm_mask(device, 0x8c1c0, 0x30000, 0x10000); in gk104_pcie_set_cap_speed()
44 nvkm_mask(device, 0x8c1c0, 0x30000, 0x20000); in gk104_pcie_set_cap_speed()
48 nvkm_mask(device, 0x8c1c0, 0x30000, 0x30000); in gk104_pcie_set_cap_speed()
58 if (speed == 0) in gk104_pcie_cap_speed()
62 int speed2 = nvkm_rd32(pci->subdev.device, 0x8c1c0) & 0x30000; in gk104_pcie_cap_speed()
64 case 0x00000: in gk104_pcie_cap_speed()
65 case 0x10000: in gk104_pcie_cap_speed()
67 case 0x20000: in gk104_pcie_cap_speed()
69 case 0x30000: in gk104_pcie_cap_speed()
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/nouveau/nvkm/subdev/pci/
Dgk104.c29 return (nvkm_rd32(pci->subdev.device, 0x8c1c0) & 0x4) == 0x4 ? 2 : 1; in gk104_pcie_version_supported()
40 nvkm_mask(device, 0x8c1c0, 0x30000, 0x10000); in gk104_pcie_set_cap_speed()
44 nvkm_mask(device, 0x8c1c0, 0x30000, 0x20000); in gk104_pcie_set_cap_speed()
48 nvkm_mask(device, 0x8c1c0, 0x30000, 0x30000); in gk104_pcie_set_cap_speed()
58 if (speed == 0) in gk104_pcie_cap_speed()
62 int speed2 = nvkm_rd32(pci->subdev.device, 0x8c1c0) & 0x30000; in gk104_pcie_cap_speed()
64 case 0x00000: in gk104_pcie_cap_speed()
65 case 0x10000: in gk104_pcie_cap_speed()
67 case 0x20000: in gk104_pcie_cap_speed()
69 case 0x30000: in gk104_pcie_cap_speed()
[all …]
/kernel/linux/linux-5.10/arch/powerpc/boot/dts/
Dtqm8548.dts31 #size-cells = <0>;
33 PowerPC,8548@0 {
35 reg = <0>;
38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
46 reg = <0x00000000 0x00000000>; // Filled in by U-Boot
53 ranges = <0x0 0xe0000000 0x100000>;
54 bus-frequency = <0>;
57 ecm-law@0 {
59 reg = <0x0 0x1000>;
[all …]
Dtqm8548-bigflash.dts31 #size-cells = <0>;
33 PowerPC,8548@0 {
35 reg = <0>;
38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
46 reg = <0x00000000 0x00000000>; // Filled in by U-Boot
53 ranges = <0x0 0xa0000000 0x100000>;
54 bus-frequency = <0>;
57 ecm-law@0 {
59 reg = <0x0 0x1000>;
[all …]
Dxpedite5200_xmon.dts18 boot-bank = <0x0>;
34 #size-cells = <0>;
36 PowerPC,8548@0 {
38 reg = <0>;
41 d-cache-size = <0x8000>; // L1, 32K
42 i-cache-size = <0x8000>; // L1, 32K
49 reg = <0x0 0x0>; // Filled in by boot loader
56 ranges = <0x0 0xef000000 0x100000>;
57 bus-frequency = <0>;
60 ecm-law@0 {
[all …]
/kernel/linux/linux-4.19/arch/powerpc/boot/dts/
Dtqm8548.dts35 #size-cells = <0>;
37 PowerPC,8548@0 {
39 reg = <0>;
42 d-cache-size = <0x8000>; // L1, 32K
43 i-cache-size = <0x8000>; // L1, 32K
50 reg = <0x00000000 0x00000000>; // Filled in by U-Boot
57 ranges = <0x0 0xe0000000 0x100000>;
58 bus-frequency = <0>;
61 ecm-law@0 {
63 reg = <0x0 0x1000>;
[all …]
Dtqm8548-bigflash.dts35 #size-cells = <0>;
37 PowerPC,8548@0 {
39 reg = <0>;
42 d-cache-size = <0x8000>; // L1, 32K
43 i-cache-size = <0x8000>; // L1, 32K
50 reg = <0x00000000 0x00000000>; // Filled in by U-Boot
57 ranges = <0x0 0xa0000000 0x100000>;
58 bus-frequency = <0>;
61 ecm-law@0 {
63 reg = <0x0 0x1000>;
[all …]
Dxpedite5200_xmon.dts21 boot-bank = <0x0>;
37 #size-cells = <0>;
39 PowerPC,8548@0 {
41 reg = <0>;
44 d-cache-size = <0x8000>; // L1, 32K
45 i-cache-size = <0x8000>; // L1, 32K
52 reg = <0x0 0x0>; // Filled in by boot loader
59 ranges = <0x0 0xef000000 0x100000>;
60 bus-frequency = <0>;
63 ecm-law@0 {
[all …]
/kernel/linux/linux-4.19/arch/arm/mach-mvebu/
Dkirkwood.h12 #define KIRKWOOD_REGS_PHYS_BASE 0xf1000000
13 #define DDR_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x00000)
14 #define BRIDGE_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x20000)
16 #define DDR_OPERATION_BASE (DDR_PHYS_BASE + 0x1418)
18 #define CPU_CONFIG_PHYS (BRIDGE_PHYS_BASE + 0x0100)
19 #define CPU_CONFIG_ERROR_PROP 0x00000004
21 #define CPU_CONTROL_PHYS (BRIDGE_PHYS_BASE + 0x0104)
22 #define MEMORY_PM_CTRL_PHYS (BRIDGE_PHYS_BASE + 0x0118)
/kernel/linux/linux-5.10/arch/arm/mach-mvebu/
Dkirkwood.h12 #define KIRKWOOD_REGS_PHYS_BASE 0xf1000000
13 #define DDR_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x00000)
14 #define BRIDGE_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x20000)
16 #define DDR_OPERATION_BASE (DDR_PHYS_BASE + 0x1418)
18 #define CPU_CONFIG_PHYS (BRIDGE_PHYS_BASE + 0x0100)
19 #define CPU_CONFIG_ERROR_PROP 0x00000004
21 #define CPU_CONTROL_PHYS (BRIDGE_PHYS_BASE + 0x0104)
22 #define MEMORY_PM_CTRL_PHYS (BRIDGE_PHYS_BASE + 0x0118)
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/display/panel/
Darm,versatile-tft-panel.txt18 sysreg@0 {
20 reg = <0x00000 0x1000>;
22 panel: display@0 {
/kernel/linux/linux-4.19/arch/arm/mach-ux500/
Ddb8500-regs.h11 #define U8500_ESRAM_BASE 0x40000000
12 #define U8500_ESRAM_BANK_SIZE 0x00020000
22 #define U8500_ESRAM_DMA_LCPA_OFFSET 0x10000
29 #define U8500_PER3_BASE 0x80000000
30 #define U8500_STM_BASE 0x80100000
31 #define U8500_STM_REG_BASE (U8500_STM_BASE + 0xF000)
32 #define U8500_PER2_BASE 0x80110000
33 #define U8500_PER1_BASE 0x80120000
34 #define U8500_B2R2_BASE 0x80130000
35 #define U8500_HSEM_BASE 0x80140000
[all …]

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