| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | tegra124-nyan-blaze-emc.dtsi | 78 nvidia,emc-auto-cal-config = <0xa1430000>; 79 nvidia,emc-auto-cal-config2 = <0x00000000>; 80 nvidia,emc-auto-cal-config3 = <0x00000000>; 81 nvidia,emc-auto-cal-interval = <0x001fffff>; 82 nvidia,emc-bgbias-ctl0 = <0x00000008>; 83 nvidia,emc-cfg = <0x73240000>; 84 nvidia,emc-cfg-2 = <0x000008c5>; 85 nvidia,emc-ctt-term-ctrl = <0x00000802>; 86 nvidia,emc-mode-1 = <0x80100003>; 87 nvidia,emc-mode-2 = <0x80200008>; [all …]
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| D | tegra20-acer-a500-picasso.dts | 36 memory@0 { 37 reg = <0x00000000 0x40000000>; 47 reg = <0x2ffe0000 0x10000>; /* 64kB */ 48 console-size = <0x8000>; /* 32kB */ 49 record-size = <0x400>; /* 1kB */ 55 alloc-ranges = <0x30000000 0x10000000>; 56 size = <0x10000000>; /* 256MiB */ 67 port@0 { 91 pinctrl-0 = <&state_default>; 406 shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; [all …]
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| D | tegra124-apalis-emc.dtsi | 94 nvidia,emc-auto-cal-config = <0xa1430000>; 95 nvidia,emc-auto-cal-config2 = <0x00000000>; 96 nvidia,emc-auto-cal-config3 = <0x00000000>; 97 nvidia,emc-auto-cal-interval = <0x001fffff>; 98 nvidia,emc-bgbias-ctl0 = <0x00000008>; 99 nvidia,emc-cfg = <0x73240000>; 100 nvidia,emc-cfg-2 = <0x000008c5>; 101 nvidia,emc-ctt-term-ctrl = <0x00000802>; 102 nvidia,emc-mode-1 = <0x80100003>; 103 nvidia,emc-mode-2 = <0x80200008>; [all …]
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| D | tegra124-jetson-tk1-emc.dtsi | 89 nvidia,emc-auto-cal-config = <0xa1430000>; 90 nvidia,emc-auto-cal-config2 = <0x00000000>; 91 nvidia,emc-auto-cal-config3 = <0x00000000>; 92 nvidia,emc-auto-cal-interval = <0x001fffff>; 93 nvidia,emc-bgbias-ctl0 = <0x00000008>; 94 nvidia,emc-cfg = <0x73240000>; 95 nvidia,emc-cfg-2 = <0x000008c5>; 96 nvidia,emc-ctt-term-ctrl = <0x00000802>; 97 nvidia,emc-mode-1 = <0x80100003>; 98 nvidia,emc-mode-2 = <0x80200008>; [all …]
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| D | tegra30-asus-nexus7-grouper-memory-timings.dtsi | 5 emc-timings-0 { 6 nvidia,ram-code = <0>; /* Elpida EDJ2108EDBG-DJL-F */ 12 0x00020001 /* MC_EMEM_ARB_CFG */ 13 0xc0000020 /* MC_EMEM_ARB_OUTSTANDING_REQ */ 14 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ 15 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ 16 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ 17 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ 18 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ 19 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ [all …]
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| D | tegra124-nyan-big-emc.dtsi | 229 nvidia,emc-auto-cal-config = <0xa1430000>; 230 nvidia,emc-auto-cal-config2 = <0x00000000>; 231 nvidia,emc-auto-cal-config3 = <0x00000000>; 232 nvidia,emc-auto-cal-interval = <0x001fffff>; 233 nvidia,emc-bgbias-ctl0 = <0x00000008>; 234 nvidia,emc-cfg = <0x73240000>; 235 nvidia,emc-cfg-2 = <0x000008c5>; 236 nvidia,emc-ctt-term-ctrl = <0x00000802>; 237 nvidia,emc-mode-1 = <0x80100003>; 238 nvidia,emc-mode-2 = <0x80200008>; [all …]
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| /kernel/linux/linux-4.19/arch/arm/boot/dts/ |
| D | tegra124-nyan-blaze-emc.dtsi | 78 nvidia,emc-auto-cal-config = <0xa1430000>; 79 nvidia,emc-auto-cal-config2 = <0x00000000>; 80 nvidia,emc-auto-cal-config3 = <0x00000000>; 81 nvidia,emc-auto-cal-interval = <0x001fffff>; 82 nvidia,emc-bgbias-ctl0 = <0x00000008>; 83 nvidia,emc-cfg = <0x73240000>; 84 nvidia,emc-cfg-2 = <0x000008c5>; 85 nvidia,emc-ctt-term-ctrl = <0x00000802>; 86 nvidia,emc-mode-1 = <0x80100003>; 87 nvidia,emc-mode-2 = <0x80200008>; [all …]
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| D | tegra124-nyan-big-emc.dtsi | 78 nvidia,emc-auto-cal-config = <0xa1430000>; 79 nvidia,emc-auto-cal-config2 = <0x00000000>; 80 nvidia,emc-auto-cal-config3 = <0x00000000>; 81 nvidia,emc-auto-cal-interval = <0x001fffff>; 82 nvidia,emc-bgbias-ctl0 = <0x00000008>; 83 nvidia,emc-cfg = <0x73240000>; 84 nvidia,emc-cfg-2 = <0x000008c5>; 85 nvidia,emc-ctt-term-ctrl = <0x00000802>; 86 nvidia,emc-mode-1 = <0x80100003>; 87 nvidia,emc-mode-2 = <0x80200008>; [all …]
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| D | tegra124-jetson-tk1-emc.dtsi | 89 nvidia,emc-auto-cal-config = <0xa1430000>; 90 nvidia,emc-auto-cal-config2 = <0x00000000>; 91 nvidia,emc-auto-cal-config3 = <0x00000000>; 92 nvidia,emc-auto-cal-interval = <0x001fffff>; 93 nvidia,emc-bgbias-ctl0 = <0x00000008>; 94 nvidia,emc-cfg = <0x73240000>; 95 nvidia,emc-cfg-2 = <0x000008c5>; 96 nvidia,emc-ctt-term-ctrl = <0x00000802>; 97 nvidia,emc-mode-1 = <0x80100003>; 98 nvidia,emc-mode-2 = <0x80200008>; [all …]
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| D | tegra124-apalis-emc.dtsi | 129 nvidia,emc-auto-cal-config = <0xa1430000>; 130 nvidia,emc-auto-cal-config2 = <0x00000000>; 131 nvidia,emc-auto-cal-config3 = <0x00000000>; 132 nvidia,emc-auto-cal-interval = <0x001fffff>; 133 nvidia,emc-bgbias-ctl0 = <0x00000008>; 134 nvidia,emc-cfg = <0x73240000>; 135 nvidia,emc-cfg-2 = <0x000008c5>; 136 nvidia,emc-ctt-term-ctrl = <0x00000802>; 137 nvidia,emc-mode-1 = <0x80100003>; 138 nvidia,emc-mode-2 = <0x80200008>; [all …]
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| /kernel/linux/linux-4.19/drivers/soc/atmel/ |
| D | soc.h | 35 #define AT91RM9200_CIDR_MATCH 0x09290780 37 #define AT91SAM9260_CIDR_MATCH 0x019803a0 38 #define AT91SAM9261_CIDR_MATCH 0x019703a0 39 #define AT91SAM9263_CIDR_MATCH 0x019607a0 40 #define AT91SAM9G20_CIDR_MATCH 0x019905a0 41 #define AT91SAM9RL64_CIDR_MATCH 0x019b03a0 42 #define AT91SAM9G45_CIDR_MATCH 0x019b05a0 43 #define AT91SAM9X5_CIDR_MATCH 0x019a05a0 44 #define AT91SAM9N12_CIDR_MATCH 0x019a07a0 46 #define AT91SAM9M11_EXID_MATCH 0x00000001 [all …]
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| /kernel/linux/linux-5.10/drivers/soc/atmel/ |
| D | soc.h | 35 #define AT91RM9200_CIDR_MATCH 0x09290780 37 #define AT91SAM9260_CIDR_MATCH 0x019803a0 38 #define AT91SAM9261_CIDR_MATCH 0x019703a0 39 #define AT91SAM9263_CIDR_MATCH 0x019607a0 40 #define AT91SAM9G20_CIDR_MATCH 0x019905a0 41 #define AT91SAM9RL64_CIDR_MATCH 0x019b03a0 42 #define AT91SAM9G45_CIDR_MATCH 0x019b05a0 43 #define AT91SAM9X5_CIDR_MATCH 0x019a05a0 44 #define AT91SAM9N12_CIDR_MATCH 0x019a07a0 45 #define SAM9X60_CIDR_MATCH 0x019b35a0 [all …]
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| /kernel/linux/linux-4.19/tools/testing/selftests/powerpc/vphn/ |
| D | test-vphn.c | 29 0xffffffffffffffff, 30 0xffffffffffffffff, 31 0xffffffffffffffff, 32 0xffffffffffffffff, 33 0xffffffffffffffff, 34 0xffffffffffffffff, 37 0x00000000 43 0x8001ffffffffffff, 44 0xffffffffffffffff, 45 0xffffffffffffffff, [all …]
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| /kernel/linux/linux-5.10/tools/testing/selftests/powerpc/vphn/ |
| D | test-vphn.c | 29 0xffffffffffffffff, 30 0xffffffffffffffff, 31 0xffffffffffffffff, 32 0xffffffffffffffff, 33 0xffffffffffffffff, 34 0xffffffffffffffff, 37 0x00000000 43 0x8001ffffffffffff, 44 0xffffffffffffffff, 45 0xffffffffffffffff, [all …]
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| /kernel/linux/patches/linux-4.19/prebuilts/usr/include/sound/ |
| D | compress_params.h | 13 #define SND_AUDIOCODEC_PCM ((__u32) 0x00000001) 14 #define SND_AUDIOCODEC_MP3 ((__u32) 0x00000002) 15 #define SND_AUDIOCODEC_AMR ((__u32) 0x00000003) 16 #define SND_AUDIOCODEC_AMRWB ((__u32) 0x00000004) 17 #define SND_AUDIOCODEC_AMRWBPLUS ((__u32) 0x00000005) 18 #define SND_AUDIOCODEC_AAC ((__u32) 0x00000006) 19 #define SND_AUDIOCODEC_WMA ((__u32) 0x00000007) 20 #define SND_AUDIOCODEC_REAL ((__u32) 0x00000008) 21 #define SND_AUDIOCODEC_VORBIS ((__u32) 0x00000009) 22 #define SND_AUDIOCODEC_FLAC ((__u32) 0x0000000A) [all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/ |
| D | vega10_enum.h | 51 GDS_PERF_SEL_DS_ADDR_CONFL = 0, 184 NO_FORCE_REQUEST = 0x00000000, 185 FORCE_LIGHT_SLEEP_REQUEST = 0x00000001, 186 FORCE_DEEP_SLEEP_REQUEST = 0x00000002, 187 FORCE_SHUT_DOWN_REQUEST = 0x00000003, 195 NO_FORCE_REQ = 0x00000000, 196 FORCE_LIGHT_SLEEP_REQ = 0x00000001, 204 ENABLE_MEM_PWR_CTRL = 0x00000000, 205 DISABLE_MEM_PWR_CTRL = 0x00000001, 213 DYNAMIC_SHUT_DOWN_ENABLE = 0x00000000, [all …]
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| D | navi10_enum.h | 51 GDS_PERF_SEL_DS_ADDR_CONFL = 0, 184 GATCL1_TYPE_NORMAL = 0x00000000, 185 GATCL1_TYPE_SHOOTDOWN = 0x00000001, 186 GATCL1_TYPE_BYPASS = 0x00000002, 194 UTCL1_TYPE_NORMAL = 0x00000000, 195 UTCL1_TYPE_SHOOTDOWN = 0x00000001, 196 UTCL1_TYPE_BYPASS = 0x00000002, 204 UTCL1_XNACK_SUCCESS = 0x00000000, 205 UTCL1_XNACK_RETRY = 0x00000001, 206 UTCL1_XNACK_PRT = 0x00000002, [all …]
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| /kernel/linux/linux-4.19/drivers/gpu/drm/amd/include/ |
| D | vega10_enum.h | 51 GDS_PERF_SEL_DS_ADDR_CONFL = 0, 184 NO_FORCE_REQUEST = 0x00000000, 185 FORCE_LIGHT_SLEEP_REQUEST = 0x00000001, 186 FORCE_DEEP_SLEEP_REQUEST = 0x00000002, 187 FORCE_SHUT_DOWN_REQUEST = 0x00000003, 195 NO_FORCE_REQ = 0x00000000, 196 FORCE_LIGHT_SLEEP_REQ = 0x00000001, 204 ENABLE_MEM_PWR_CTRL = 0x00000000, 205 DISABLE_MEM_PWR_CTRL = 0x00000001, 213 DYNAMIC_SHUT_DOWN_ENABLE = 0x00000000, [all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/include/nvhw/class/ |
| D | cla0b5.h | 27 #define NVA0B5_SET_SRC_PHYS_MODE (0x00000260) 28 #define NVA0B5_SET_SRC_PHYS_MODE_TARGET 1:0 29 #define NVA0B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) 30 #define NVA0B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) 31 #define NVA0B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) 32 #define NVA0B5_SET_DST_PHYS_MODE (0x00000264) 33 #define NVA0B5_SET_DST_PHYS_MODE_TARGET 1:0 34 #define NVA0B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) 35 #define NVA0B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) 36 #define NVA0B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) [all …]
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| D | cl917d.h | 28 #define NV917D_SOR_SET_CONTROL(a) (0x00000200 + (a)*0… 29 #define NV917D_SOR_SET_CONTROL_OWNER_MASK 3:0 30 #define NV917D_SOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) 31 #define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) 32 #define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) 33 #define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) 34 #define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) 36 #define NV917D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000) 37 #define NV917D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001) 38 #define NV917D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002) [all …]
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| /kernel/linux/patches/linux-5.10/prebuilts/usr/include/sound/ |
| D | compress_params.h | 26 #define SND_AUDIOCODEC_PCM ((__u32) 0x00000001) 27 #define SND_AUDIOCODEC_MP3 ((__u32) 0x00000002) 28 #define SND_AUDIOCODEC_AMR ((__u32) 0x00000003) 29 #define SND_AUDIOCODEC_AMRWB ((__u32) 0x00000004) 30 #define SND_AUDIOCODEC_AMRWBPLUS ((__u32) 0x00000005) 31 #define SND_AUDIOCODEC_AAC ((__u32) 0x00000006) 32 #define SND_AUDIOCODEC_WMA ((__u32) 0x00000007) 33 #define SND_AUDIOCODEC_REAL ((__u32) 0x00000008) 34 #define SND_AUDIOCODEC_VORBIS ((__u32) 0x00000009) 35 #define SND_AUDIOCODEC_FLAC ((__u32) 0x0000000A) [all …]
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| /kernel/linux/linux-5.10/sound/pci/cs46xx/ |
| D | cs46xx.h | 25 #define BA0_HISR 0x00000000 26 #define BA0_HSR0 0x00000004 27 #define BA0_HICR 0x00000008 28 #define BA0_DMSR 0x00000100 29 #define BA0_HSAR 0x00000110 30 #define BA0_HDAR 0x00000114 31 #define BA0_HDMR 0x00000118 32 #define BA0_HDCR 0x0000011C 33 #define BA0_PFMC 0x00000200 34 #define BA0_PFCV1 0x00000204 [all …]
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| /kernel/linux/linux-4.19/sound/pci/cs46xx/ |
| D | cs46xx.h | 40 #define BA0_HISR 0x00000000 41 #define BA0_HSR0 0x00000004 42 #define BA0_HICR 0x00000008 43 #define BA0_DMSR 0x00000100 44 #define BA0_HSAR 0x00000110 45 #define BA0_HDAR 0x00000114 46 #define BA0_HDMR 0x00000118 47 #define BA0_HDCR 0x0000011C 48 #define BA0_PFMC 0x00000200 49 #define BA0_PFCV1 0x00000204 [all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/bif/ |
| D | bif_3_0_sh_mask.h | 26 #define BACO_CNTL__BACO_ANA_ISO_DIS_MASK 0x00000080L 27 #define BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT 0x00000007 28 #define BACO_CNTL__BACO_BCLK_OFF_MASK 0x00000002L 29 #define BACO_CNTL__BACO_BCLK_OFF__SHIFT 0x00000001 30 #define BACO_CNTL__BACO_EN_MASK 0x00000001L 31 #define BACO_CNTL__BACO_EN__SHIFT 0x00000000 32 #define BACO_CNTL__BACO_HANG_PROTECTION_EN_MASK 0x00000020L 33 #define BACO_CNTL__BACO_HANG_PROTECTION_EN__SHIFT 0x00000005 34 #define BACO_CNTL__BACO_ISO_DIS_MASK 0x00000004L 35 #define BACO_CNTL__BACO_ISO_DIS__SHIFT 0x00000002 [all …]
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| /kernel/linux/linux-4.19/drivers/gpu/drm/amd/include/asic_reg/bif/ |
| D | bif_3_0_sh_mask.h | 26 #define BACO_CNTL__BACO_ANA_ISO_DIS_MASK 0x00000080L 27 #define BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT 0x00000007 28 #define BACO_CNTL__BACO_BCLK_OFF_MASK 0x00000002L 29 #define BACO_CNTL__BACO_BCLK_OFF__SHIFT 0x00000001 30 #define BACO_CNTL__BACO_EN_MASK 0x00000001L 31 #define BACO_CNTL__BACO_EN__SHIFT 0x00000000 32 #define BACO_CNTL__BACO_HANG_PROTECTION_EN_MASK 0x00000020L 33 #define BACO_CNTL__BACO_HANG_PROTECTION_EN__SHIFT 0x00000005 34 #define BACO_CNTL__BACO_ISO_DIS_MASK 0x00000004L 35 #define BACO_CNTL__BACO_ISO_DIS__SHIFT 0x00000002 [all …]
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