| /kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| D | regsnv04.h | 5 #define NV04_PFB_BOOT_0 0x00100000
6 # define NV04_PFB_BOOT_0_RAM_AMOUNT 0x00000003
7 # define NV04_PFB_BOOT_0_RAM_AMOUNT_32MB 0x00000000
8 # define NV04_PFB_BOOT_0_RAM_AMOUNT_4MB 0x00000001
9 # define NV04_PFB_BOOT_0_RAM_AMOUNT_8MB 0x00000002
10 # define NV04_PFB_BOOT_0_RAM_AMOUNT_16MB 0x00000003
11 # define NV04_PFB_BOOT_0_RAM_WIDTH_128 0x00000004
12 # define NV04_PFB_BOOT_0_RAM_TYPE 0x00000028
13 # define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT 0x00000000
14 # define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT 0x00000008
[all …]
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| /kernel/linux/linux-4.19/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| D | regsnv04.h | 5 #define NV04_PFB_BOOT_0 0x00100000
6 # define NV04_PFB_BOOT_0_RAM_AMOUNT 0x00000003
7 # define NV04_PFB_BOOT_0_RAM_AMOUNT_32MB 0x00000000
8 # define NV04_PFB_BOOT_0_RAM_AMOUNT_4MB 0x00000001
9 # define NV04_PFB_BOOT_0_RAM_AMOUNT_8MB 0x00000002
10 # define NV04_PFB_BOOT_0_RAM_AMOUNT_16MB 0x00000003
11 # define NV04_PFB_BOOT_0_RAM_WIDTH_128 0x00000004
12 # define NV04_PFB_BOOT_0_RAM_TYPE 0x00000028
13 # define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT 0x00000000
14 # define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT 0x00000008
[all …]
|
| /kernel/linux/linux-5.10/drivers/staging/media/rkisp1/ |
| D | rkisp1-regs.h | 12 #define RKISP1_CIF_ISP_CTRL_ISP_ENABLE BIT(0)
13 #define RKISP1_CIF_ISP_CTRL_ISP_MODE_RAW_PICT (0 << 1)
32 #define RKISP1_CIF_ISP_ACQ_PROP_POS_EDGE BIT(0)
35 #define RKISP1_CIF_ISP_ACQ_PROP_BAYER_PAT_RGGB (0 << 3)
40 #define RKISP1_CIF_ISP_ACQ_PROP_YCBYCR (0 << 7)
44 #define RKISP1_CIF_ISP_ACQ_PROP_FIELD_SEL_ALL (0 << 9)
47 #define RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_12B (0 << 12)
54 #define RKISP1_CIF_VI_DPCL_DMA_JPEG (0 << 0)
55 #define RKISP1_CIF_VI_DPCL_MP_MUX_MRSZ_MI BIT(0)
56 #define RKISP1_CIF_VI_DPCL_MP_MUX_MRSZ_JPEG (2 << 0)
[all …]
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/hdmi/ |
| D | hdmi.xml.h | 50 HDCP_KEYS_STATE_NO_KEYS = 0,
61 DDC_WRITE = 0,
66 ACR_NONE = 0,
72 #define REG_HDMI_CTRL 0x00000000
73 #define HDMI_CTRL_ENABLE 0x00000001
74 #define HDMI_CTRL_HDMI 0x00000002
75 #define HDMI_CTRL_ENCRYPTED 0x00000004
77 #define REG_HDMI_AUDIO_PKT_CTRL1 0x00000020
78 #define HDMI_AUDIO_PKT_CTRL1_AUDIO_SAMPLE_SEND 0x00000001
80 #define REG_HDMI_ACR_PKT_CTRL 0x00000024
[all …]
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| /kernel/linux/linux-4.19/drivers/gpu/drm/msm/hdmi/ |
| D | hdmi.xml.h | 50 HDCP_KEYS_STATE_NO_KEYS = 0,
61 DDC_WRITE = 0,
66 ACR_NONE = 0,
72 #define REG_HDMI_CTRL 0x00000000
73 #define HDMI_CTRL_ENABLE 0x00000001
74 #define HDMI_CTRL_HDMI 0x00000002
75 #define HDMI_CTRL_ENCRYPTED 0x00000004
77 #define REG_HDMI_AUDIO_PKT_CTRL1 0x00000020
78 #define HDMI_AUDIO_PKT_CTRL1_AUDIO_SAMPLE_SEND 0x00000001
80 #define REG_HDMI_ACR_PKT_CTRL 0x00000024
[all …]
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| /kernel/linux/linux-5.10/include/linux/amba/ |
| D | clcd-regs.h | 17 #define CLCD_TIM0 0x00000000
18 #define CLCD_TIM1 0x00000004
19 #define CLCD_TIM2 0x00000008
20 #define CLCD_TIM3 0x0000000c
21 #define CLCD_UBAS 0x00000010
22 #define CLCD_LBAS 0x00000014
24 #define CLCD_PL110_IENB 0x00000018
25 #define CLCD_PL110_CNTL 0x0000001c
26 #define CLCD_PL110_STAT 0x00000020
27 #define CLCD_PL110_INTR 0x00000024
[all …]
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| /kernel/linux/linux-4.19/include/linux/amba/ |
| D | clcd-regs.h | 17 #define CLCD_TIM0 0x00000000
18 #define CLCD_TIM1 0x00000004
19 #define CLCD_TIM2 0x00000008
20 #define CLCD_TIM3 0x0000000c
21 #define CLCD_UBAS 0x00000010
22 #define CLCD_LBAS 0x00000014
24 #define CLCD_PL110_IENB 0x00000018
25 #define CLCD_PL110_CNTL 0x0000001c
26 #define CLCD_PL110_STAT 0x00000020
27 #define CLCD_PL110_INTR 0x00000024
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/ |
| D | hsw_clear_kernel.c | 9 0x00000001, 0x26020128, 0x00000024, 0x00000000,
10 0x00000040, 0x20280c21, 0x00000028, 0x00000001,
11 0x01000010, 0x20000c20, 0x0000002c, 0x00000000,
12 0x00010220, 0x34001c00, 0x00001400, 0x00000160,
13 0x00600001, 0x20600061, 0x00000000, 0x00000000,
14 0x00000008, 0x20601c85, 0x00000e00, 0x0000000c,
15 0x00000005, 0x20601ca5, 0x00000060, 0x00000001,
16 0x00000008, 0x20641c85, 0x00000e00, 0x0000000d,
17 0x00000005, 0x20641ca5, 0x00000064, 0x00000003,
18 0x00000041, 0x207424a5, 0x00000064, 0x00000034,
[all …]
|
| D | ivb_clear_kernel.c | 9 0x00000001, 0x26020128, 0x00000024, 0x00000000,
10 0x00000040, 0x20280c21, 0x00000028, 0x00000001,
11 0x01000010, 0x20000c20, 0x0000002c, 0x00000000,
12 0x00010220, 0x34001c00, 0x00001400, 0x0000002c,
13 0x00600001, 0x20600061, 0x00000000, 0x00000000,
14 0x00000008, 0x20601c85, 0x00000e00, 0x0000000c,
15 0x00000005, 0x20601ca5, 0x00000060, 0x00000001,
16 0x00000008, 0x20641c85, 0x00000e00, 0x0000000d,
17 0x00000005, 0x20641ca5, 0x00000064, 0x00000003,
18 0x00000041, 0x207424a5, 0x00000064, 0x00000034,
[all …]
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/dp/ |
| D | dp_reg.h | 10 #define REG_DP_HW_VERSION (0x00000000)
12 #define REG_DP_SW_RESET (0x00000010)
13 #define DP_SW_RESET (0x00000001)
15 #define REG_DP_PHY_CTRL (0x00000014)
16 #define DP_PHY_CTRL_SW_RESET_PLL (0x00000001)
17 #define DP_PHY_CTRL_SW_RESET (0x00000004)
19 #define REG_DP_CLK_CTRL (0x00000018)
20 #define REG_DP_CLK_ACTIVE (0x0000001C)
21 #define REG_DP_INTR_STATUS (0x00000020)
22 #define REG_DP_INTR_STATUS2 (0x00000024)
[all …]
|
| /kernel/linux/linux-4.19/drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/ |
| D | phytbl_lcn.c | 21 0x00000000,
22 0x00000000,
23 0x00000000,
24 0x00000000,
25 0x00000000,
26 0x00000000,
27 0x00000000,
28 0x00000000,
29 0x00000004,
30 0x00000000,
[all …]
|
| /kernel/linux/linux-5.10/drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/ |
| D | phytbl_lcn.c | 10 0x00000000,
11 0x00000000,
12 0x00000000,
13 0x00000000,
14 0x00000000,
15 0x00000000,
16 0x00000000,
17 0x00000000,
18 0x00000004,
19 0x00000000,
[all …]
|
| /kernel/linux/linux-4.19/drivers/gpu/drm/msm/dsi/ |
| D | dsi.xml.h | 50 NON_BURST_SYNCH_PULSE = 0,
56 VID_DST_FORMAT_RGB565 = 0,
63 SWAP_RGB = 0,
72 TRIGGER_NONE = 0,
81 CMD_DST_FORMAT_RGB111 = 0,
90 LANE_SWAP_0123 = 0,
100 #define DSI_IRQ_CMD_DMA_DONE 0x00000001
101 #define DSI_IRQ_MASK_CMD_DMA_DONE 0x00000002
102 #define DSI_IRQ_CMD_MDP_DONE 0x00000100
103 #define DSI_IRQ_MASK_CMD_MDP_DONE 0x00000200
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/dsi/ |
| D | dsi.xml.h | 50 NON_BURST_SYNCH_PULSE = 0,
56 VID_DST_FORMAT_RGB565 = 0,
63 SWAP_RGB = 0,
72 TRIGGER_NONE = 0,
81 CMD_DST_FORMAT_RGB111 = 0,
90 LANE_SWAP_0123 = 0,
100 #define DSI_IRQ_CMD_DMA_DONE 0x00000001
101 #define DSI_IRQ_MASK_CMD_DMA_DONE 0x00000002
102 #define DSI_IRQ_CMD_MDP_DONE 0x00000100
103 #define DSI_IRQ_MASK_CMD_MDP_DONE 0x00000200
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/pl111/ |
| D | pl111_drm.h | 29 #define CLCD_TIM0 0x00000000
30 #define CLCD_TIM1 0x00000004
31 #define CLCD_TIM2 0x00000008
32 #define CLCD_TIM3 0x0000000c
33 #define CLCD_UBAS 0x00000010
34 #define CLCD_LBAS 0x00000014
36 #define CLCD_PL110_IENB 0x00000018
37 #define CLCD_PL110_CNTL 0x0000001c
38 #define CLCD_PL110_STAT 0x00000020
39 #define CLCD_PL110_INTR 0x00000024
[all …]
|
| /kernel/linux/linux-5.10/drivers/net/wireless/ath/ath9k/ |
| D | ar956x_initvals.h | 41 {0x00009800, 0xafe68e30},
42 {0x00009804, 0xfd14e000},
43 {0x00009808, 0x9c0a9f6b},
44 {0x0000980c, 0x04900000},
45 {0x00009814, 0x0280c00a},
46 {0x00009818, 0x00000000},
47 {0x0000981c, 0x00020028},
48 {0x00009834, 0x6400a190},
49 {0x00009838, 0x0108ecff},
50 {0x0000983c, 0x14000600},
[all …]
|
| /kernel/linux/linux-4.19/drivers/net/wireless/ath/ath9k/ |
| D | ar956x_initvals.h | 41 {0x00009800, 0xafe68e30},
42 {0x00009804, 0xfd14e000},
43 {0x00009808, 0x9c0a9f6b},
44 {0x0000980c, 0x04900000},
45 {0x00009814, 0x0280c00a},
46 {0x00009818, 0x00000000},
47 {0x0000981c, 0x00020028},
48 {0x00009834, 0x6400a190},
49 {0x00009838, 0x0108ecff},
50 {0x0000983c, 0x14000600},
[all …]
|
| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/thermal/ |
| D | qoriq-thermal.txt | 6 offset 0x0BF8.
10 0x01900102 T1040
31 reg = <0xf0000 0x1000>;
32 interrupts = <18 2 0 0>;
33 fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>;
34 fsl,tmu-calibration = <0x00000000 0x00000025
35 0x00000001 0x00000028
36 0x00000002 0x0000002d
37 0x00000003 0x00000031
38 0x00000004 0x00000036
[all …]
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/include/nvhw/class/ |
| D | cl907e.h | 28 #define NV907E_SET_PRESENT_CONTROL (0x00000084)
29 #define NV907E_SET_PRESENT_CONTROL_BEGIN_MODE 1:0
30 #define NV907E_SET_PRESENT_CONTROL_BEGIN_MODE_ASAP (0x00000000)
31 #define NV907E_SET_PRESENT_CONTROL_BEGIN_MODE_TIMESTAMP (0x00000003)
33 #define NV907E_SET_CONTEXT_DMA_ISO (0x000000C0)
34 #define NV907E_SET_CONTEXT_DMA_ISO_HANDLE 31:0
35 #define NV907E_SET_COMPOSITION_CONTROL (0x00000100)
36 #define NV907E_SET_COMPOSITION_CONTROL_MODE 3:0
37 #define NV907E_SET_COMPOSITION_CONTROL_MODE_SOURCE_COLOR_VALUE_KEYING (0x00000000)
38 #define NV907E_SET_COMPOSITION_CONTROL_MODE_DESTINATION_COLOR_VALUE_KEYING (0x00000001)
[all …]
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| D | cl827e.h | 27 #define NV_DISP_NOTIFICATION_1 0x00000000
28 #define NV_DISP_NOTIFICATION_1_SIZEOF 0x00000010
29 #define NV_DISP_NOTIFICATION_1_TIME_STAMP_0 0x00000000
30 #define NV_DISP_NOTIFICATION_1_TIME_STAMP_0_NANOSECONDS0 31:0
31 #define NV_DISP_NOTIFICATION_1_TIME_STAMP_1 0x00000001
32 #define NV_DISP_NOTIFICATION_1_TIME_STAMP_1_NANOSECONDS1 31:0
33 #define NV_DISP_NOTIFICATION_1__2 0x00000002
34 #define NV_DISP_NOTIFICATION_1__2_AUDIT_TIMESTAMP 31:0
35 #define NV_DISP_NOTIFICATION_1__3 0x00000003
36 #define NV_DISP_NOTIFICATION_1__3_PRESENT_COUNT 7:0
[all …]
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| D | cl507e.h | 28 #define NV507E_SET_PRESENT_CONTROL (0x00000084)
29 #define NV507E_SET_PRESENT_CONTROL_BEGIN_MODE 1:0
30 #define NV507E_SET_PRESENT_CONTROL_BEGIN_MODE_ASAP (0x00000000)
31 #define NV507E_SET_PRESENT_CONTROL_BEGIN_MODE_TIMESTAMP (0x00000003)
33 #define NV507E_SET_CONTEXT_DMA_ISO (0x000000C0)
34 #define NV507E_SET_CONTEXT_DMA_ISO_HANDLE 31:0
35 #define NV507E_SET_POINT_IN (0x000000E0)
36 #define NV507E_SET_POINT_IN_X 14:0
38 #define NV507E_SET_SIZE_IN (0x000000E4)
39 #define NV507E_SET_SIZE_IN_WIDTH 14:0
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/edp/ |
| D | edp.xml.h | 50 EDP_6BIT = 0,
58 EDP_RGB = 0,
63 #define REG_EDP_MAINLINK_CTRL 0x00000004
64 #define EDP_MAINLINK_CTRL_ENABLE 0x00000001
65 #define EDP_MAINLINK_CTRL_RESET 0x00000002
67 #define REG_EDP_STATE_CTRL 0x00000008
68 #define EDP_STATE_CTRL_TRAIN_PATTERN_1 0x00000001
69 #define EDP_STATE_CTRL_TRAIN_PATTERN_2 0x00000002
70 #define EDP_STATE_CTRL_TRAIN_PATTERN_3 0x00000004
71 #define EDP_STATE_CTRL_SYMBOL_ERR_RATE_MEAS 0x00000008
[all …]
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| /kernel/linux/linux-4.19/drivers/gpu/drm/msm/edp/ |
| D | edp.xml.h | 50 EDP_6BIT = 0,
58 EDP_RGB = 0,
63 #define REG_EDP_MAINLINK_CTRL 0x00000004
64 #define EDP_MAINLINK_CTRL_ENABLE 0x00000001
65 #define EDP_MAINLINK_CTRL_RESET 0x00000002
67 #define REG_EDP_STATE_CTRL 0x00000008
68 #define EDP_STATE_CTRL_TRAIN_PATTERN_1 0x00000001
69 #define EDP_STATE_CTRL_TRAIN_PATTERN_2 0x00000002
70 #define EDP_STATE_CTRL_TRAIN_PATTERN_3 0x00000004
71 #define EDP_STATE_CTRL_SYMBOL_ERR_RATE_MEAS 0x00000008
[all …]
|
| /kernel/linux/linux-5.10/drivers/crypto/ |
| D | picoxcell_crypto_regs.h | 8 #define SPA_STATUS_OK 0
16 #define SPA_FIFO_STAT_STAT_CNT_MASK (0x3F << SPA_FIFO_STAT_STAT_OFFSET)
18 #define SPA_STATUS_RES_CODE_MASK (0x3 << SPA_STATUS_RES_CODE_OFFSET)
22 #define SPA_IRQ_EN_REG_OFFSET 0x00000000
23 #define SPA_IRQ_STAT_REG_OFFSET 0x00000004
24 #define SPA_IRQ_CTRL_REG_OFFSET 0x00000008
25 #define SPA_FIFO_STAT_REG_OFFSET 0x0000000C
26 #define SPA_SDMA_BRST_SZ_REG_OFFSET 0x00000010
27 #define SPA_SRC_PTR_REG_OFFSET 0x00000020
28 #define SPA_DST_PTR_REG_OFFSET 0x00000024
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/thermal/ |
| D | qoriq-thermal.yaml | 16 Register (IPBRR0) at offset 0x0BF8.
20 0x01900102 T1040
78 reg = <0xf0000 0x1000>;
79 interrupts = <18 2 0 0>;
80 fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>;
81 fsl,tmu-calibration = <0x00000000 0x00000025>,
82 <0x00000001 0x00000028>,
83 <0x00000002 0x0000002d>,
84 <0x00000003 0x00000031>,
85 <0x00000004 0x00000036>,
[all …]
|