Searched +full:0 +full:x00000054 (Results 1 – 25 of 96) sorted by relevance
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| /kernel/linux/linux-5.10/drivers/staging/media/rkisp1/ |
| D | rkisp1-regs.h | 12 #define RKISP1_CIF_ISP_CTRL_ISP_ENABLE BIT(0)
13 #define RKISP1_CIF_ISP_CTRL_ISP_MODE_RAW_PICT (0 << 1)
32 #define RKISP1_CIF_ISP_ACQ_PROP_POS_EDGE BIT(0)
35 #define RKISP1_CIF_ISP_ACQ_PROP_BAYER_PAT_RGGB (0 << 3)
40 #define RKISP1_CIF_ISP_ACQ_PROP_YCBYCR (0 << 7)
44 #define RKISP1_CIF_ISP_ACQ_PROP_FIELD_SEL_ALL (0 << 9)
47 #define RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_12B (0 << 12)
54 #define RKISP1_CIF_VI_DPCL_DMA_JPEG (0 << 0)
55 #define RKISP1_CIF_VI_DPCL_MP_MUX_MRSZ_MI BIT(0)
56 #define RKISP1_CIF_VI_DPCL_MP_MUX_MRSZ_JPEG (2 << 0)
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/hdmi/ |
| D | hdmi.xml.h | 50 HDCP_KEYS_STATE_NO_KEYS = 0,
61 DDC_WRITE = 0,
66 ACR_NONE = 0,
72 #define REG_HDMI_CTRL 0x00000000
73 #define HDMI_CTRL_ENABLE 0x00000001
74 #define HDMI_CTRL_HDMI 0x00000002
75 #define HDMI_CTRL_ENCRYPTED 0x00000004
77 #define REG_HDMI_AUDIO_PKT_CTRL1 0x00000020
78 #define HDMI_AUDIO_PKT_CTRL1_AUDIO_SAMPLE_SEND 0x00000001
80 #define REG_HDMI_ACR_PKT_CTRL 0x00000024
[all …]
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| /kernel/linux/linux-4.19/drivers/gpu/drm/msm/hdmi/ |
| D | hdmi.xml.h | 50 HDCP_KEYS_STATE_NO_KEYS = 0,
61 DDC_WRITE = 0,
66 ACR_NONE = 0,
72 #define REG_HDMI_CTRL 0x00000000
73 #define HDMI_CTRL_ENABLE 0x00000001
74 #define HDMI_CTRL_HDMI 0x00000002
75 #define HDMI_CTRL_ENCRYPTED 0x00000004
77 #define REG_HDMI_AUDIO_PKT_CTRL1 0x00000020
78 #define HDMI_AUDIO_PKT_CTRL1_AUDIO_SAMPLE_SEND 0x00000001
80 #define REG_HDMI_ACR_PKT_CTRL 0x00000024
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/thermal/ |
| D | qoriq-thermal.txt | 6 offset 0x0BF8.
10 0x01900102 T1040
31 reg = <0xf0000 0x1000>;
32 interrupts = <18 2 0 0>;
33 fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>;
34 fsl,tmu-calibration = <0x00000000 0x00000025
35 0x00000001 0x00000028
36 0x00000002 0x0000002d
37 0x00000003 0x00000031
38 0x00000004 0x00000036
[all …]
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| /kernel/linux/linux-5.10/arch/powerpc/platforms/83xx/ |
| D | mpc83xx.h | 10 #define MPC83XX_SCCR_OFFS 0xA08
11 #define MPC83XX_SCCR_USB_MASK 0x00f00000
12 #define MPC83XX_SCCR_USB_MPHCM_11 0x00c00000
13 #define MPC83XX_SCCR_USB_MPHCM_01 0x00400000
14 #define MPC83XX_SCCR_USB_MPHCM_10 0x00800000
15 #define MPC83XX_SCCR_USB_DRCM_11 0x00300000
16 #define MPC83XX_SCCR_USB_DRCM_01 0x00100000
17 #define MPC83XX_SCCR_USB_DRCM_10 0x00200000
18 #define MPC8315_SCCR_USB_MASK 0x00c00000
19 #define MPC8315_SCCR_USB_DRCM_11 0x00c00000
[all …]
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| /kernel/linux/linux-4.19/arch/powerpc/platforms/83xx/ |
| D | mpc83xx.h | 10 #define MPC83XX_SCCR_OFFS 0xA08
11 #define MPC83XX_SCCR_USB_MASK 0x00f00000
12 #define MPC83XX_SCCR_USB_MPHCM_11 0x00c00000
13 #define MPC83XX_SCCR_USB_MPHCM_01 0x00400000
14 #define MPC83XX_SCCR_USB_MPHCM_10 0x00800000
15 #define MPC83XX_SCCR_USB_DRCM_11 0x00300000
16 #define MPC83XX_SCCR_USB_DRCM_01 0x00100000
17 #define MPC83XX_SCCR_USB_DRCM_10 0x00200000
18 #define MPC8315_SCCR_USB_MASK 0x00c00000
19 #define MPC8315_SCCR_USB_DRCM_11 0x00c00000
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| /kernel/linux/linux-5.10/drivers/crypto/ |
| D | picoxcell_crypto_regs.h | 8 #define SPA_STATUS_OK 0
16 #define SPA_FIFO_STAT_STAT_CNT_MASK (0x3F << SPA_FIFO_STAT_STAT_OFFSET)
18 #define SPA_STATUS_RES_CODE_MASK (0x3 << SPA_STATUS_RES_CODE_OFFSET)
22 #define SPA_IRQ_EN_REG_OFFSET 0x00000000
23 #define SPA_IRQ_STAT_REG_OFFSET 0x00000004
24 #define SPA_IRQ_CTRL_REG_OFFSET 0x00000008
25 #define SPA_FIFO_STAT_REG_OFFSET 0x0000000C
26 #define SPA_SDMA_BRST_SZ_REG_OFFSET 0x00000010
27 #define SPA_SRC_PTR_REG_OFFSET 0x00000020
28 #define SPA_DST_PTR_REG_OFFSET 0x00000024
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/thermal/ |
| D | qoriq-thermal.yaml | 16 Register (IPBRR0) at offset 0x0BF8.
20 0x01900102 T1040
78 reg = <0xf0000 0x1000>;
79 interrupts = <18 2 0 0>;
80 fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>;
81 fsl,tmu-calibration = <0x00000000 0x00000025>,
82 <0x00000001 0x00000028>,
83 <0x00000002 0x0000002d>,
84 <0x00000003 0x00000031>,
85 <0x00000004 0x00000036>,
[all …]
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| /kernel/linux/linux-4.19/drivers/crypto/ |
| D | picoxcell_crypto_regs.h | 21 #define SPA_STATUS_OK 0
29 #define SPA_FIFO_STAT_STAT_CNT_MASK (0x3F << SPA_FIFO_STAT_STAT_OFFSET)
31 #define SPA_STATUS_RES_CODE_MASK (0x3 << SPA_STATUS_RES_CODE_OFFSET)
35 #define SPA_IRQ_EN_REG_OFFSET 0x00000000
36 #define SPA_IRQ_STAT_REG_OFFSET 0x00000004
37 #define SPA_IRQ_CTRL_REG_OFFSET 0x00000008
38 #define SPA_FIFO_STAT_REG_OFFSET 0x0000000C
39 #define SPA_SDMA_BRST_SZ_REG_OFFSET 0x00000010
40 #define SPA_SRC_PTR_REG_OFFSET 0x00000020
41 #define SPA_DST_PTR_REG_OFFSET 0x00000024
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| /kernel/linux/linux-5.10/drivers/crypto/amcc/ |
| D | crypto4xx_reg_def.h | 15 #define CRYPTO4XX_DESCRIPTOR 0x00000000
16 #define CRYPTO4XX_CTRL_STAT 0x00000000
17 #define CRYPTO4XX_SOURCE 0x00000004
18 #define CRYPTO4XX_DEST 0x00000008
19 #define CRYPTO4XX_SA 0x0000000C
20 #define CRYPTO4XX_SA_LENGTH 0x00000010
21 #define CRYPTO4XX_LENGTH 0x00000014
23 #define CRYPTO4XX_PE_DMA_CFG 0x00000040
24 #define CRYPTO4XX_PE_DMA_STAT 0x00000044
25 #define CRYPTO4XX_PDR_BASE 0x00000048
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| /kernel/linux/linux-4.19/drivers/crypto/amcc/ |
| D | crypto4xx_reg_def.h | 24 #define CRYPTO4XX_DESCRIPTOR 0x00000000
25 #define CRYPTO4XX_CTRL_STAT 0x00000000
26 #define CRYPTO4XX_SOURCE 0x00000004
27 #define CRYPTO4XX_DEST 0x00000008
28 #define CRYPTO4XX_SA 0x0000000C
29 #define CRYPTO4XX_SA_LENGTH 0x00000010
30 #define CRYPTO4XX_LENGTH 0x00000014
32 #define CRYPTO4XX_PE_DMA_CFG 0x00000040
33 #define CRYPTO4XX_PE_DMA_STAT 0x00000044
34 #define CRYPTO4XX_PDR_BASE 0x00000048
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| /kernel/linux/linux-4.19/drivers/net/wireless/realtek/rtl8xxxu/ |
| D | rtl8xxxu_8192c.c | 45 .reg_0e00 = 0x07090c0c,
46 .reg_0e04 = 0x01020405,
47 .reg_0e08 = 0x00000000,
48 .reg_086c = 0x00000000,
50 .reg_0e10 = 0x0b0c0c0e,
51 .reg_0e14 = 0x01030506,
52 .reg_0e18 = 0x0b0c0d0e,
53 .reg_0e1c = 0x01030509,
55 .reg_0830 = 0x07090c0c,
56 .reg_0834 = 0x01020405,
[all …]
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| /kernel/linux/linux-5.10/drivers/net/wireless/realtek/rtl8xxxu/ |
| D | rtl8xxxu_8192c.c | 37 .reg_0e00 = 0x07090c0c,
38 .reg_0e04 = 0x01020405,
39 .reg_0e08 = 0x00000000,
40 .reg_086c = 0x00000000,
42 .reg_0e10 = 0x0b0c0c0e,
43 .reg_0e14 = 0x01030506,
44 .reg_0e18 = 0x0b0c0d0e,
45 .reg_0e1c = 0x01030509,
47 .reg_0830 = 0x07090c0c,
48 .reg_0834 = 0x01020405,
[all …]
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| /kernel/linux/linux-4.19/drivers/video/fbdev/mbx/ |
| D | regs.h | 9 /* System Configuration Registers (0x0000_0000 0x0000_0010) */
10 #define SYSCFG __REG_2700G(0x00000000)
11 #define PFBASE __REG_2700G(0x00000004)
12 #define PFCEIL __REG_2700G(0x00000008)
13 #define POLLFLAG __REG_2700G(0x0000000c)
14 #define SYSRST __REG_2700G(0x00000010)
16 /* Interrupt Control Registers (0x0000_0014 0x0000_002F) */
17 #define NINTPW __REG_2700G(0x00000014)
18 #define MINTENABLE __REG_2700G(0x00000018)
19 #define MINTSTAT __REG_2700G(0x0000001c)
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| /kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/include/nvhw/class/ |
| D | clc37d.h | 27 #define NV_DISP_NOTIFIER 0x00000000
28 #define NV_DISP_NOTIFIER_SIZEOF 0x00000010
29 #define NV_DISP_NOTIFIER__0 0x00000000
30 #define NV_DISP_NOTIFIER__0_PRESENT_COUNT 7:0
33 #define NV_DISP_NOTIFIER__0_FLIP_TYPE_NON_TEARING 0x00000000
34 #define NV_DISP_NOTIFIER__0_FLIP_TYPE_IMMEDIATE 0x00000001
39 #define NV_DISP_NOTIFIER__0_STATUS_NOT_BEGUN 0x00000000
40 #define NV_DISP_NOTIFIER__0_STATUS_BEGUN 0x00000001
41 #define NV_DISP_NOTIFIER__0_STATUS_FINISHED 0x00000002
42 #define NV_DISP_NOTIFIER__1 0x00000001
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| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/dsi/ |
| D | dsi.xml.h | 50 NON_BURST_SYNCH_PULSE = 0,
56 VID_DST_FORMAT_RGB565 = 0,
63 SWAP_RGB = 0,
72 TRIGGER_NONE = 0,
81 CMD_DST_FORMAT_RGB111 = 0,
90 LANE_SWAP_0123 = 0,
100 #define DSI_IRQ_CMD_DMA_DONE 0x00000001
101 #define DSI_IRQ_MASK_CMD_DMA_DONE 0x00000002
102 #define DSI_IRQ_CMD_MDP_DONE 0x00000100
103 #define DSI_IRQ_MASK_CMD_MDP_DONE 0x00000200
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| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/dp/ |
| D | dp_reg.h | 10 #define REG_DP_HW_VERSION (0x00000000)
12 #define REG_DP_SW_RESET (0x00000010)
13 #define DP_SW_RESET (0x00000001)
15 #define REG_DP_PHY_CTRL (0x00000014)
16 #define DP_PHY_CTRL_SW_RESET_PLL (0x00000001)
17 #define DP_PHY_CTRL_SW_RESET (0x00000004)
19 #define REG_DP_CLK_CTRL (0x00000018)
20 #define REG_DP_CLK_ACTIVE (0x0000001C)
21 #define REG_DP_INTR_STATUS (0x00000020)
22 #define REG_DP_INTR_STATUS2 (0x00000024)
[all …]
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| /kernel/linux/linux-5.10/drivers/net/ethernet/toshiba/ |
| D | spider_net.h | 57 #define SPIDER_NET_GHIINT0STS 0x00000000
58 #define SPIDER_NET_GHIINT1STS 0x00000004
59 #define SPIDER_NET_GHIINT2STS 0x00000008
60 #define SPIDER_NET_GHIINT0MSK 0x00000010
61 #define SPIDER_NET_GHIINT1MSK 0x00000014
62 #define SPIDER_NET_GHIINT2MSK 0x00000018
64 #define SPIDER_NET_GRESUMINTNUM 0x00000020
65 #define SPIDER_NET_GREINTNUM 0x00000024
67 #define SPIDER_NET_GFFRMNUM 0x00000028
68 #define SPIDER_NET_GFAFRMNUM 0x0000002c
[all …]
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| /kernel/linux/linux-4.19/drivers/gpu/drm/msm/dsi/ |
| D | dsi.xml.h | 50 NON_BURST_SYNCH_PULSE = 0,
56 VID_DST_FORMAT_RGB565 = 0,
63 SWAP_RGB = 0,
72 TRIGGER_NONE = 0,
81 CMD_DST_FORMAT_RGB111 = 0,
90 LANE_SWAP_0123 = 0,
100 #define DSI_IRQ_CMD_DMA_DONE 0x00000001
101 #define DSI_IRQ_MASK_CMD_DMA_DONE 0x00000002
102 #define DSI_IRQ_CMD_MDP_DONE 0x00000100
103 #define DSI_IRQ_MASK_CMD_MDP_DONE 0x00000200
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| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/edp/ |
| D | edp.xml.h | 50 EDP_6BIT = 0,
58 EDP_RGB = 0,
63 #define REG_EDP_MAINLINK_CTRL 0x00000004
64 #define EDP_MAINLINK_CTRL_ENABLE 0x00000001
65 #define EDP_MAINLINK_CTRL_RESET 0x00000002
67 #define REG_EDP_STATE_CTRL 0x00000008
68 #define EDP_STATE_CTRL_TRAIN_PATTERN_1 0x00000001
69 #define EDP_STATE_CTRL_TRAIN_PATTERN_2 0x00000002
70 #define EDP_STATE_CTRL_TRAIN_PATTERN_3 0x00000004
71 #define EDP_STATE_CTRL_SYMBOL_ERR_RATE_MEAS 0x00000008
[all …]
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| /kernel/linux/linux-4.19/drivers/gpu/drm/msm/edp/ |
| D | edp.xml.h | 50 EDP_6BIT = 0,
58 EDP_RGB = 0,
63 #define REG_EDP_MAINLINK_CTRL 0x00000004
64 #define EDP_MAINLINK_CTRL_ENABLE 0x00000001
65 #define EDP_MAINLINK_CTRL_RESET 0x00000002
67 #define REG_EDP_STATE_CTRL 0x00000008
68 #define EDP_STATE_CTRL_TRAIN_PATTERN_1 0x00000001
69 #define EDP_STATE_CTRL_TRAIN_PATTERN_2 0x00000002
70 #define EDP_STATE_CTRL_TRAIN_PATTERN_3 0x00000004
71 #define EDP_STATE_CTRL_SYMBOL_ERR_RATE_MEAS 0x00000008
[all …]
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| /kernel/linux/linux-4.19/drivers/net/ethernet/toshiba/ |
| D | spider_net.h | 70 #define SPIDER_NET_GHIINT0STS 0x00000000
71 #define SPIDER_NET_GHIINT1STS 0x00000004
72 #define SPIDER_NET_GHIINT2STS 0x00000008
73 #define SPIDER_NET_GHIINT0MSK 0x00000010
74 #define SPIDER_NET_GHIINT1MSK 0x00000014
75 #define SPIDER_NET_GHIINT2MSK 0x00000018
77 #define SPIDER_NET_GRESUMINTNUM 0x00000020
78 #define SPIDER_NET_GREINTNUM 0x00000024
80 #define SPIDER_NET_GFFRMNUM 0x00000028
81 #define SPIDER_NET_GFAFRMNUM 0x0000002c
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/mcde/ |
| D | mcde_dsi_regs.h | 5 #define DSI_MCTL_INTEGRATION_MODE 0x00000000
7 #define DSI_MCTL_MAIN_DATA_CTL 0x00000004
8 #define DSI_MCTL_MAIN_DATA_CTL_LINK_EN BIT(0)
25 #define DSI_MCTL_MAIN_PHY_CTL 0x00000008
26 #define DSI_MCTL_MAIN_PHY_CTL_LANE2_EN BIT(0)
33 #define DSI_MCTL_MAIN_PHY_CTL_WAIT_BURST_TIME_MASK 0x000003C0
36 #define DSI_MCTL_PLL_CTL 0x0000000C
37 #define DSI_MCTL_LANE_STS 0x00000010
39 #define DSI_MCTL_DPHY_TIMEOUT 0x00000014
40 #define DSI_MCTL_DPHY_TIMEOUT_CLK_DIV_SHIFT 0
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| /kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/ |
| D | gt215.fuc3.h | 3 /* 0x0000: ctx_object */
4 0x00000000,
5 /* 0x0004: ctx_dma */
6 /* 0x0004: ctx_dma_query */
7 0x00000000,
8 /* 0x0008: ctx_dma_src */
9 0x00000000,
10 /* 0x000c: ctx_dma_dst */
11 0x00000000,
12 /* 0x0010: ctx_query_address_high */
[all …]
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| /kernel/linux/linux-4.19/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/ |
| D | gt215.fuc3.h | 3 /* 0x0000: ctx_object */
4 0x00000000,
5 /* 0x0004: ctx_dma */
6 /* 0x0004: ctx_dma_query */
7 0x00000000,
8 /* 0x0008: ctx_dma_src */
9 0x00000000,
10 /* 0x000c: ctx_dma_dst */
11 0x00000000,
12 /* 0x0010: ctx_query_address_high */
[all …]
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