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/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dtegra124-nyan-blaze-emc.dtsi78 nvidia,emc-auto-cal-config = <0xa1430000>;
79 nvidia,emc-auto-cal-config2 = <0x00000000>;
80 nvidia,emc-auto-cal-config3 = <0x00000000>;
81 nvidia,emc-auto-cal-interval = <0x001fffff>;
82 nvidia,emc-bgbias-ctl0 = <0x00000008>;
83 nvidia,emc-cfg = <0x73240000>;
84 nvidia,emc-cfg-2 = <0x000008c5>;
85 nvidia,emc-ctt-term-ctrl = <0x00000802>;
86 nvidia,emc-mode-1 = <0x80100003>;
87 nvidia,emc-mode-2 = <0x80200008>;
[all …]
Dtegra124-apalis-emc.dtsi94 nvidia,emc-auto-cal-config = <0xa1430000>;
95 nvidia,emc-auto-cal-config2 = <0x00000000>;
96 nvidia,emc-auto-cal-config3 = <0x00000000>;
97 nvidia,emc-auto-cal-interval = <0x001fffff>;
98 nvidia,emc-bgbias-ctl0 = <0x00000008>;
99 nvidia,emc-cfg = <0x73240000>;
100 nvidia,emc-cfg-2 = <0x000008c5>;
101 nvidia,emc-ctt-term-ctrl = <0x00000802>;
102 nvidia,emc-mode-1 = <0x80100003>;
103 nvidia,emc-mode-2 = <0x80200008>;
[all …]
Dtegra124-jetson-tk1-emc.dtsi89 nvidia,emc-auto-cal-config = <0xa1430000>;
90 nvidia,emc-auto-cal-config2 = <0x00000000>;
91 nvidia,emc-auto-cal-config3 = <0x00000000>;
92 nvidia,emc-auto-cal-interval = <0x001fffff>;
93 nvidia,emc-bgbias-ctl0 = <0x00000008>;
94 nvidia,emc-cfg = <0x73240000>;
95 nvidia,emc-cfg-2 = <0x000008c5>;
96 nvidia,emc-ctt-term-ctrl = <0x00000802>;
97 nvidia,emc-mode-1 = <0x80100003>;
98 nvidia,emc-mode-2 = <0x80200008>;
[all …]
Dtegra124-nyan-big-emc.dtsi229 nvidia,emc-auto-cal-config = <0xa1430000>;
230 nvidia,emc-auto-cal-config2 = <0x00000000>;
231 nvidia,emc-auto-cal-config3 = <0x00000000>;
232 nvidia,emc-auto-cal-interval = <0x001fffff>;
233 nvidia,emc-bgbias-ctl0 = <0x00000008>;
234 nvidia,emc-cfg = <0x73240000>;
235 nvidia,emc-cfg-2 = <0x000008c5>;
236 nvidia,emc-ctt-term-ctrl = <0x00000802>;
237 nvidia,emc-mode-1 = <0x80100003>;
238 nvidia,emc-mode-2 = <0x80200008>;
[all …]
Domap4460.dtsi15 cpu0: cpu@0 {
42 reg = <0x4a002260 0x4
43 0x4a00232C 0x4
44 0x4a002378 0x18>;
46 interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; /* talert */
49 #thermal-sensor-cells = <0>;
55 reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>,
56 <0x4A002268 0x4>;
62 1025000 0 0 0 0 0
63 1200000 0 0 0 0 0
[all …]
/kernel/linux/linux-4.19/arch/arm/boot/dts/
Dtegra124-nyan-blaze-emc.dtsi78 nvidia,emc-auto-cal-config = <0xa1430000>;
79 nvidia,emc-auto-cal-config2 = <0x00000000>;
80 nvidia,emc-auto-cal-config3 = <0x00000000>;
81 nvidia,emc-auto-cal-interval = <0x001fffff>;
82 nvidia,emc-bgbias-ctl0 = <0x00000008>;
83 nvidia,emc-cfg = <0x73240000>;
84 nvidia,emc-cfg-2 = <0x000008c5>;
85 nvidia,emc-ctt-term-ctrl = <0x00000802>;
86 nvidia,emc-mode-1 = <0x80100003>;
87 nvidia,emc-mode-2 = <0x80200008>;
[all …]
Dtegra124-nyan-big-emc.dtsi78 nvidia,emc-auto-cal-config = <0xa1430000>;
79 nvidia,emc-auto-cal-config2 = <0x00000000>;
80 nvidia,emc-auto-cal-config3 = <0x00000000>;
81 nvidia,emc-auto-cal-interval = <0x001fffff>;
82 nvidia,emc-bgbias-ctl0 = <0x00000008>;
83 nvidia,emc-cfg = <0x73240000>;
84 nvidia,emc-cfg-2 = <0x000008c5>;
85 nvidia,emc-ctt-term-ctrl = <0x00000802>;
86 nvidia,emc-mode-1 = <0x80100003>;
87 nvidia,emc-mode-2 = <0x80200008>;
[all …]
Dtegra124-jetson-tk1-emc.dtsi89 nvidia,emc-auto-cal-config = <0xa1430000>;
90 nvidia,emc-auto-cal-config2 = <0x00000000>;
91 nvidia,emc-auto-cal-config3 = <0x00000000>;
92 nvidia,emc-auto-cal-interval = <0x001fffff>;
93 nvidia,emc-bgbias-ctl0 = <0x00000008>;
94 nvidia,emc-cfg = <0x73240000>;
95 nvidia,emc-cfg-2 = <0x000008c5>;
96 nvidia,emc-ctt-term-ctrl = <0x00000802>;
97 nvidia,emc-mode-1 = <0x80100003>;
98 nvidia,emc-mode-2 = <0x80200008>;
[all …]
Dtegra124-apalis-emc.dtsi129 nvidia,emc-auto-cal-config = <0xa1430000>;
130 nvidia,emc-auto-cal-config2 = <0x00000000>;
131 nvidia,emc-auto-cal-config3 = <0x00000000>;
132 nvidia,emc-auto-cal-interval = <0x001fffff>;
133 nvidia,emc-bgbias-ctl0 = <0x00000008>;
134 nvidia,emc-cfg = <0x73240000>;
135 nvidia,emc-cfg-2 = <0x000008c5>;
136 nvidia,emc-ctt-term-ctrl = <0x00000802>;
137 nvidia,emc-mode-1 = <0x80100003>;
138 nvidia,emc-mode-2 = <0x80200008>;
[all …]
Domap4460.dtsi15 cpu0: cpu@0 {
42 reg = <0x4a002260 0x4
43 0x4a00232C 0x4
44 0x4a002378 0x18>;
46 interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; /* talert */
49 #thermal-sensor-cells = <0>;
55 reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>,
56 <0x4A002268 0x4>;
62 1025000 0 0 0 0 0
63 1200000 0 0 0 0 0
[all …]
/kernel/linux/linux-4.19/drivers/net/wireless/broadcom/b43/
Ddma.h19 #define B43_DMA32_TXCTL 0x00
20 #define B43_DMA32_TXENABLE 0x00000001
21 #define B43_DMA32_TXSUSPEND 0x00000002
22 #define B43_DMA32_TXLOOPBACK 0x00000004
23 #define B43_DMA32_TXFLUSH 0x00000010
24 #define B43_DMA32_TXPARITYDISABLE 0x00000800
25 #define B43_DMA32_TXADDREXT_MASK 0x00030000
27 #define B43_DMA32_TXRING 0x04
28 #define B43_DMA32_TXINDEX 0x08
29 #define B43_DMA32_TXSTATUS 0x0C
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/broadcom/b43/
Ddma.h19 #define B43_DMA32_TXCTL 0x00
20 #define B43_DMA32_TXENABLE 0x00000001
21 #define B43_DMA32_TXSUSPEND 0x00000002
22 #define B43_DMA32_TXLOOPBACK 0x00000004
23 #define B43_DMA32_TXFLUSH 0x00000010
24 #define B43_DMA32_TXPARITYDISABLE 0x00000800
25 #define B43_DMA32_TXADDREXT_MASK 0x00030000
27 #define B43_DMA32_TXRING 0x04
28 #define B43_DMA32_TXINDEX 0x08
29 #define B43_DMA32_TXSTATUS 0x0C
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/
Dnv40.c37 u32 dma0 = nvkm_instmem_rd32(imem, inst + 0); in nv40_mpeg_mthd_dma()
40 u32 base = (dma2 & 0xfffff000) | (dma0 >> 20); in nv40_mpeg_mthd_dma()
44 if (!(dma0 & 0x00002000)) { in nv40_mpeg_mthd_dma()
50 if (mthd == 0x0190) { in nv40_mpeg_mthd_dma()
52 nvkm_mask(device, 0x00b300, 0x00030000, (dma0 & 0x00030000)); in nv40_mpeg_mthd_dma()
53 nvkm_wr32(device, 0x00b334, base); in nv40_mpeg_mthd_dma()
54 nvkm_wr32(device, 0x00b324, size); in nv40_mpeg_mthd_dma()
56 if (mthd == 0x01a0) { in nv40_mpeg_mthd_dma()
58 nvkm_mask(device, 0x00b300, 0x000c0000, (dma0 & 0x00030000) << 2); in nv40_mpeg_mthd_dma()
59 nvkm_wr32(device, 0x00b360, base); in nv40_mpeg_mthd_dma()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/
Dnv40.c37 u32 dma0 = nvkm_instmem_rd32(imem, inst + 0); in nv40_mpeg_mthd_dma()
40 u32 base = (dma2 & 0xfffff000) | (dma0 >> 20); in nv40_mpeg_mthd_dma()
44 if (!(dma0 & 0x00002000)) { in nv40_mpeg_mthd_dma()
50 if (mthd == 0x0190) { in nv40_mpeg_mthd_dma()
52 nvkm_mask(device, 0x00b300, 0x00030000, (dma0 & 0x00030000)); in nv40_mpeg_mthd_dma()
53 nvkm_wr32(device, 0x00b334, base); in nv40_mpeg_mthd_dma()
54 nvkm_wr32(device, 0x00b324, size); in nv40_mpeg_mthd_dma()
56 if (mthd == 0x01a0) { in nv40_mpeg_mthd_dma()
58 nvkm_mask(device, 0x00b300, 0x000c0000, (dma0 & 0x00030000) << 2); in nv40_mpeg_mthd_dma()
59 nvkm_wr32(device, 0x00b360, base); in nv40_mpeg_mthd_dma()
[all …]
/kernel/linux/linux-4.19/drivers/net/wireless/broadcom/b43legacy/
Ddma.h24 #define B43legacy_DMA32_TXCTL 0x00
25 #define B43legacy_DMA32_TXENABLE 0x00000001
26 #define B43legacy_DMA32_TXSUSPEND 0x00000002
27 #define B43legacy_DMA32_TXLOOPBACK 0x00000004
28 #define B43legacy_DMA32_TXFLUSH 0x00000010
29 #define B43legacy_DMA32_TXADDREXT_MASK 0x00030000
31 #define B43legacy_DMA32_TXRING 0x04
32 #define B43legacy_DMA32_TXINDEX 0x08
33 #define B43legacy_DMA32_TXSTATUS 0x0C
34 #define B43legacy_DMA32_TXDPTR 0x00000FFF
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/broadcom/b43legacy/
Ddma.h24 #define B43legacy_DMA32_TXCTL 0x00
25 #define B43legacy_DMA32_TXENABLE 0x00000001
26 #define B43legacy_DMA32_TXSUSPEND 0x00000002
27 #define B43legacy_DMA32_TXLOOPBACK 0x00000004
28 #define B43legacy_DMA32_TXFLUSH 0x00000010
29 #define B43legacy_DMA32_TXADDREXT_MASK 0x00030000
31 #define B43legacy_DMA32_TXRING 0x04
32 #define B43legacy_DMA32_TXINDEX 0x08
33 #define B43legacy_DMA32_TXSTATUS 0x0C
34 #define B43legacy_DMA32_TXDPTR 0x00000FFF
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/nouveau/nvkm/engine/disp/
Dpiocnv50.c38 nvkm_mask(device, 0x610200 + (ctrl * 0x10), 0x00000001, 0x00000000); in nv50_disp_pioc_fini()
40 if (!(nvkm_rd32(device, 0x610200 + (ctrl * 0x10)) & 0x00030000)) in nv50_disp_pioc_fini()
42 ) < 0) { in nv50_disp_pioc_fini()
44 nvkm_rd32(device, 0x610200 + (ctrl * 0x10))); in nv50_disp_pioc_fini()
57 nvkm_wr32(device, 0x610200 + (ctrl * 0x10), 0x00002000); in nv50_disp_pioc_init()
59 if (!(nvkm_rd32(device, 0x610200 + (ctrl * 0x10)) & 0x00030000)) in nv50_disp_pioc_init()
61 ) < 0) { in nv50_disp_pioc_init()
63 nvkm_rd32(device, 0x610200 + (ctrl * 0x10))); in nv50_disp_pioc_init()
67 nvkm_wr32(device, 0x610200 + (ctrl * 0x10), 0x00000001); in nv50_disp_pioc_init()
69 u32 tmp = nvkm_rd32(device, 0x610200 + (ctrl * 0x10)); in nv50_disp_pioc_init()
[all …]
Dpiocgf119.c38 nvkm_mask(device, 0x610490 + (ctrl * 0x10), 0x00000001, 0x00000000); in gf119_disp_pioc_fini()
40 if (!(nvkm_rd32(device, 0x610490 + (ctrl * 0x10)) & 0x00030000)) in gf119_disp_pioc_fini()
42 ) < 0) { in gf119_disp_pioc_fini()
44 nvkm_rd32(device, 0x610490 + (ctrl * 0x10))); in gf119_disp_pioc_fini()
58 nvkm_wr32(device, 0x610490 + (ctrl * 0x10), 0x00000001); in gf119_disp_pioc_init()
60 u32 tmp = nvkm_rd32(device, 0x610490 + (ctrl * 0x10)); in gf119_disp_pioc_init()
61 if ((tmp & 0x00030000) == 0x00010000) in gf119_disp_pioc_init()
63 ) < 0) { in gf119_disp_pioc_init()
65 nvkm_rd32(device, 0x610490 + (ctrl * 0x10))); in gf119_disp_pioc_init()
69 return 0; in gf119_disp_pioc_init()
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/disp/
Dpiocnv50.c38 nvkm_mask(device, 0x610200 + (ctrl * 0x10), 0x00000001, 0x00000000); in nv50_disp_pioc_fini()
40 if (!(nvkm_rd32(device, 0x610200 + (ctrl * 0x10)) & 0x00030000)) in nv50_disp_pioc_fini()
42 ) < 0) { in nv50_disp_pioc_fini()
44 nvkm_rd32(device, 0x610200 + (ctrl * 0x10))); in nv50_disp_pioc_fini()
57 nvkm_wr32(device, 0x610200 + (ctrl * 0x10), 0x00002000); in nv50_disp_pioc_init()
59 if (!(nvkm_rd32(device, 0x610200 + (ctrl * 0x10)) & 0x00030000)) in nv50_disp_pioc_init()
61 ) < 0) { in nv50_disp_pioc_init()
63 nvkm_rd32(device, 0x610200 + (ctrl * 0x10))); in nv50_disp_pioc_init()
67 nvkm_wr32(device, 0x610200 + (ctrl * 0x10), 0x00000001); in nv50_disp_pioc_init()
69 u32 tmp = nvkm_rd32(device, 0x610200 + (ctrl * 0x10)); in nv50_disp_pioc_init()
[all …]
Dpiocgf119.c38 nvkm_mask(device, 0x610490 + (ctrl * 0x10), 0x00000001, 0x00000000); in gf119_disp_pioc_fini()
40 if (!(nvkm_rd32(device, 0x610490 + (ctrl * 0x10)) & 0x00030000)) in gf119_disp_pioc_fini()
42 ) < 0) { in gf119_disp_pioc_fini()
44 nvkm_rd32(device, 0x610490 + (ctrl * 0x10))); in gf119_disp_pioc_fini()
58 nvkm_wr32(device, 0x610490 + (ctrl * 0x10), 0x00000001); in gf119_disp_pioc_init()
60 u32 tmp = nvkm_rd32(device, 0x610490 + (ctrl * 0x10)); in gf119_disp_pioc_init()
61 if ((tmp & 0x00030000) == 0x00010000) in gf119_disp_pioc_init()
63 ) < 0) { in gf119_disp_pioc_init()
65 nvkm_rd32(device, 0x610490 + (ctrl * 0x10))); in gf119_disp_pioc_init()
69 return 0; in gf119_disp_pioc_init()
/kernel/linux/linux-5.10/drivers/gpu/drm/via/
Dvia_3d_reg.h27 #define HC_REG_BASE 0x0400
29 #define HC_REG_TRANS_SPACE 0x0040
31 #define HC_ParaN_MASK 0xffffffff
32 #define HC_Para_MASK 0x00ffffff
33 #define HC_SubA_MASK 0xff000000
37 #define HC_REG_TRANS_SET 0x003c
38 #define HC_ParaSubType_MASK 0xff000000
39 #define HC_ParaType_MASK 0x00ff0000
40 #define HC_ParaOS_MASK 0x0000ff00
41 #define HC_ParaAdr_MASK 0x000000ff
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/via/
Dvia_3d_reg.h27 #define HC_REG_BASE 0x0400
29 #define HC_REG_TRANS_SPACE 0x0040
31 #define HC_ParaN_MASK 0xffffffff
32 #define HC_Para_MASK 0x00ffffff
33 #define HC_SubA_MASK 0xff000000
37 #define HC_REG_TRANS_SET 0x003c
38 #define HC_ParaSubType_MASK 0xff000000
39 #define HC_ParaType_MASK 0x00ff0000
40 #define HC_ParaOS_MASK 0x0000ff00
41 #define HC_ParaAdr_MASK 0x000000ff
[all …]
/kernel/linux/linux-4.19/arch/parisc/kernel/
Dperf_images.h40 0x4c00c000, 0x00000000, 0x00060000, 0x00000000,
41 0xe0e0e0e0, 0x004e0004, 0x07ffffff, 0xffc01380,
42 0x0101ffff, 0xfffff104, 0xe000c07f, 0xfffffffc,
43 0x01380010, 0x1fffffff, 0xff000000, 0x00000000,
44 0x00000fff, 0xff00000f, 0xffff0000, 0x0fffff00,
45 0x000fffff, 0x00000000, 0x00000000, 0x00ffffff,
46 0xfffff000, 0x0000000f, 0xffffffff, 0xff000000,
47 0x0000ffff, 0xfffffff0, 0x00000000, 0x0fffffff,
48 0xffff0000, 0x00000000, 0x6fffffff, 0xffffffff,
49 0xfff55fff, 0xffffffff, 0xffffffff, 0xf0000000,
[all …]
/kernel/linux/linux-5.10/arch/parisc/kernel/
Dperf_images.h27 0x4c00c000, 0x00000000, 0x00060000, 0x00000000,
28 0xe0e0e0e0, 0x004e0004, 0x07ffffff, 0xffc01380,
29 0x0101ffff, 0xfffff104, 0xe000c07f, 0xfffffffc,
30 0x01380010, 0x1fffffff, 0xff000000, 0x00000000,
31 0x00000fff, 0xff00000f, 0xffff0000, 0x0fffff00,
32 0x000fffff, 0x00000000, 0x00000000, 0x00ffffff,
33 0xfffff000, 0x0000000f, 0xffffffff, 0xff000000,
34 0x0000ffff, 0xfffffff0, 0x00000000, 0x0fffffff,
35 0xffff0000, 0x00000000, 0x6fffffff, 0xffffffff,
36 0xfff55fff, 0xffffffff, 0xffffffff, 0xf0000000,
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-ep93xx/
Dsoc.h19 * the synchronous boot mode is selected. When ASDO is "0" (i.e
23 * 0x00000000 and nCS0 is decoded starting at 0xf0000000. For asynchronous
24 * boot mode they are swapped with nCS0 decoded at 0x00000000 ann nSDCE3
25 * decoded at 0xf0000000.
34 #define EP93XX_CS0_PHYS_BASE_ASYNC 0x00000000 /* ASDO Pin = 0 */
35 #define EP93XX_SDCE3_PHYS_BASE_SYNC 0x00000000 /* ASDO Pin = 1 */
36 #define EP93XX_CS1_PHYS_BASE 0x10000000
37 #define EP93XX_CS2_PHYS_BASE 0x20000000
38 #define EP93XX_CS3_PHYS_BASE 0x30000000
39 #define EP93XX_PCMCIA_PHYS_BASE 0x40000000
[all …]

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