Searched +full:0 +full:x0064 (Results 1 – 25 of 569) sorted by relevance
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| /kernel/linux/linux-4.19/arch/unicore32/include/mach/ |
| D | regs-ps2.h | 8 #define PS2_DATA (PKUNITY_PS2_BASE + 0x0060)
12 #define PS2_COMMAND (PKUNITY_PS2_BASE + 0x0064)
16 #define PS2_STATUS (PKUNITY_PS2_BASE + 0x0064)
20 #define PS2_CNT (PKUNITY_PS2_BASE + 0x0068)
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| /kernel/linux/linux-4.19/drivers/gpu/drm/ast/ |
| D | ast_dram_tables.h | 12 { 0x0108, 0x00000000 },
13 { 0x0120, 0x00004a21 },
14 { 0xFF00, 0x00000043 },
15 { 0x0000, 0xFFFFFFFF },
16 { 0x0004, 0x00000089 },
17 { 0x0008, 0x22331353 },
18 { 0x000C, 0x0d07000b },
19 { 0x0010, 0x11113333 },
20 { 0x0020, 0x00110350 },
21 { 0x0028, 0x1e0828f0 },
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/ast/ |
| D | ast_dram_tables.h | 12 { 0x0108, 0x00000000 },
13 { 0x0120, 0x00004a21 },
14 { 0xFF00, 0x00000043 },
15 { 0x0000, 0xFFFFFFFF },
16 { 0x0004, 0x00000089 },
17 { 0x0008, 0x22331353 },
18 { 0x000C, 0x0d07000b },
19 { 0x0010, 0x11113333 },
20 { 0x0020, 0x00110350 },
21 { 0x0028, 0x1e0828f0 },
[all …]
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| /kernel/linux/linux-4.19/arch/arm/mach-omap2/ |
| D | prm44xx.h | 31 #define OMAP4430_PRM_BASE 0x4a306000
38 #define OMAP4430_PRM_OCP_SOCKET_INST 0x0000
39 #define OMAP4430_PRM_CKGEN_INST 0x0100
40 #define OMAP4430_PRM_MPU_INST 0x0300
41 #define OMAP4430_PRM_TESLA_INST 0x0400
42 #define OMAP4430_PRM_ABE_INST 0x0500
43 #define OMAP4430_PRM_ALWAYS_ON_INST 0x0600
44 #define OMAP4430_PRM_CORE_INST 0x0700
45 #define OMAP4430_PRM_IVAHD_INST 0x0f00
46 #define OMAP4430_PRM_CAM_INST 0x1000
[all …]
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| D | prm7xx.h | 29 #define DRA7XX_PRM_BASE 0x4ae06000
36 #define DRA7XX_PRM_OCP_SOCKET_INST 0x0000
37 #define DRA7XX_PRM_CKGEN_INST 0x0100
38 #define DRA7XX_PRM_MPU_INST 0x0300
39 #define DRA7XX_PRM_DSP1_INST 0x0400
40 #define DRA7XX_PRM_IPU_INST 0x0500
41 #define DRA7XX_PRM_COREAON_INST 0x0628
42 #define DRA7XX_PRM_CORE_INST 0x0700
43 #define DRA7XX_PRM_IVA_INST 0x0f00
44 #define DRA7XX_PRM_CAM_INST 0x1000
[all …]
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| D | cm33xx.h | 25 #define AM33XX_CM_BASE 0x44e00000
31 #define AM33XX_CM_PER_MOD 0x0000
32 #define AM33XX_CM_WKUP_MOD 0x0400
33 #define AM33XX_CM_DPLL_MOD 0x0500
34 #define AM33XX_CM_MPU_MOD 0x0600
35 #define AM33XX_CM_DEVICE_MOD 0x0700
36 #define AM33XX_CM_RTC_MOD 0x0800
37 #define AM33XX_CM_GFX_MOD 0x0900
38 #define AM33XX_CM_CEFUSE_MOD 0x0A00
43 #define AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET 0x0000
[all …]
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| D | prm3xxx.h | 36 #define OMAP3_PRM_REVISION_OFFSET 0x0004
37 #define OMAP3430_PRM_REVISION OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004)
38 #define OMAP3_PRM_SYSCONFIG_OFFSET 0x0014
39 #define OMAP3430_PRM_SYSCONFIG OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014)
41 #define OMAP3_PRM_IRQSTATUS_MPU_OFFSET 0x0018
42 #define OMAP3430_PRM_IRQSTATUS_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018)
43 #define OMAP3_PRM_IRQENABLE_MPU_OFFSET 0x001c
44 #define OMAP3430_PRM_IRQENABLE_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c)
47 #define OMAP3_PRM_VC_SMPS_SA_OFFSET 0x0020
48 #define OMAP3430_PRM_VC_SMPS_SA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
[all …]
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| D | prm54xx.h | 27 #define OMAP54XX_PRM_BASE 0x4ae06000
34 #define OMAP54XX_PRM_OCP_SOCKET_INST 0x0000
35 #define OMAP54XX_PRM_CKGEN_INST 0x0100
36 #define OMAP54XX_PRM_MPU_INST 0x0300
37 #define OMAP54XX_PRM_DSP_INST 0x0400
38 #define OMAP54XX_PRM_ABE_INST 0x0500
39 #define OMAP54XX_PRM_COREAON_INST 0x0600
40 #define OMAP54XX_PRM_CORE_INST 0x0700
41 #define OMAP54XX_PRM_IVA_INST 0x1200
42 #define OMAP54XX_PRM_CAM_INST 0x1300
[all …]
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| D | cm1_54xx.h | 26 #define OMAP54XX_CM_CORE_AON_BASE 0x4a004000
32 #define OMAP54XX_CM_CORE_AON_OCP_SOCKET_INST 0x0000
33 #define OMAP54XX_CM_CORE_AON_CKGEN_INST 0x0100
34 #define OMAP54XX_CM_CORE_AON_MPU_INST 0x0300
35 #define OMAP54XX_CM_CORE_AON_DSP_INST 0x0400
36 #define OMAP54XX_CM_CORE_AON_ABE_INST 0x0500
37 #define OMAP54XX_CM_CORE_AON_RESTORE_INST 0x0e00
38 #define OMAP54XX_CM_CORE_AON_INSTR_INST 0x0f00
41 #define OMAP54XX_CM_CORE_AON_MPU_MPU_CDOFFS 0x0000
42 #define OMAP54XX_CM_CORE_AON_DSP_DSP_CDOFFS 0x0000
[all …]
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| /kernel/linux/linux-5.10/arch/arm/mach-omap2/ |
| D | prm44xx.h | 28 #define OMAP4430_PRM_BASE 0x4a306000
35 #define OMAP4430_PRM_OCP_SOCKET_INST 0x0000
36 #define OMAP4430_PRM_CKGEN_INST 0x0100
37 #define OMAP4430_PRM_MPU_INST 0x0300
38 #define OMAP4430_PRM_TESLA_INST 0x0400
39 #define OMAP4430_PRM_ABE_INST 0x0500
40 #define OMAP4430_PRM_ALWAYS_ON_INST 0x0600
41 #define OMAP4430_PRM_CORE_INST 0x0700
42 #define OMAP4430_PRM_IVAHD_INST 0x0f00
43 #define OMAP4430_PRM_CAM_INST 0x1000
[all …]
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| D | prm7xx.h | 26 #define DRA7XX_PRM_BASE 0x4ae06000
33 #define DRA7XX_PRM_OCP_SOCKET_INST 0x0000
34 #define DRA7XX_PRM_CKGEN_INST 0x0100
35 #define DRA7XX_PRM_MPU_INST 0x0300
36 #define DRA7XX_PRM_DSP1_INST 0x0400
37 #define DRA7XX_PRM_IPU_INST 0x0500
38 #define DRA7XX_PRM_COREAON_INST 0x0628
39 #define DRA7XX_PRM_CORE_INST 0x0700
40 #define DRA7XX_PRM_IVA_INST 0x0f00
41 #define DRA7XX_PRM_CAM_INST 0x1000
[all …]
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| D | cm33xx.h | 25 #define AM33XX_CM_BASE 0x44e00000
31 #define AM33XX_CM_PER_MOD 0x0000
32 #define AM33XX_CM_WKUP_MOD 0x0400
33 #define AM33XX_CM_DPLL_MOD 0x0500
34 #define AM33XX_CM_MPU_MOD 0x0600
35 #define AM33XX_CM_DEVICE_MOD 0x0700
36 #define AM33XX_CM_RTC_MOD 0x0800
37 #define AM33XX_CM_GFX_MOD 0x0900
38 #define AM33XX_CM_CEFUSE_MOD 0x0A00
43 #define AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET 0x0000
[all …]
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| D | prm3xxx.h | 33 #define OMAP3_PRM_REVISION_OFFSET 0x0004
34 #define OMAP3430_PRM_REVISION OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004)
35 #define OMAP3_PRM_SYSCONFIG_OFFSET 0x0014
36 #define OMAP3430_PRM_SYSCONFIG OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014)
38 #define OMAP3_PRM_IRQSTATUS_MPU_OFFSET 0x0018
39 #define OMAP3430_PRM_IRQSTATUS_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018)
40 #define OMAP3_PRM_IRQENABLE_MPU_OFFSET 0x001c
41 #define OMAP3430_PRM_IRQENABLE_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c)
44 #define OMAP3_PRM_VC_SMPS_SA_OFFSET 0x0020
45 #define OMAP3430_PRM_VC_SMPS_SA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
[all …]
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| D | prm54xx.h | 24 #define OMAP54XX_PRM_BASE 0x4ae06000
31 #define OMAP54XX_PRM_OCP_SOCKET_INST 0x0000
32 #define OMAP54XX_PRM_CKGEN_INST 0x0100
33 #define OMAP54XX_PRM_MPU_INST 0x0300
34 #define OMAP54XX_PRM_DSP_INST 0x0400
35 #define OMAP54XX_PRM_ABE_INST 0x0500
36 #define OMAP54XX_PRM_COREAON_INST 0x0600
37 #define OMAP54XX_PRM_CORE_INST 0x0700
38 #define OMAP54XX_PRM_IVA_INST 0x1200
39 #define OMAP54XX_PRM_CAM_INST 0x1300
[all …]
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| D | cm1_54xx.h | 22 #define OMAP54XX_CM_CORE_AON_BASE 0x4a004000
28 #define OMAP54XX_CM_CORE_AON_OCP_SOCKET_INST 0x0000
29 #define OMAP54XX_CM_CORE_AON_CKGEN_INST 0x0100
30 #define OMAP54XX_CM_CORE_AON_MPU_INST 0x0300
31 #define OMAP54XX_CM_CORE_AON_DSP_INST 0x0400
32 #define OMAP54XX_CM_CORE_AON_ABE_INST 0x0500
33 #define OMAP54XX_CM_CORE_AON_RESTORE_INST 0x0e00
34 #define OMAP54XX_CM_CORE_AON_INSTR_INST 0x0f00
37 #define OMAP54XX_CM_CORE_AON_MPU_MPU_CDOFFS 0x0000
38 #define OMAP54XX_CM_CORE_AON_DSP_DSP_CDOFFS 0x0000
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/nbio/ |
| D | nbio_6_1_offset.h | 27 // base address: 0x0
28 …PSWUSCFG0_VENDOR_ID 0x0000
29 …PSWUSCFG0_DEVICE_ID 0x0002
30 …PSWUSCFG0_COMMAND 0x0004
31 …PSWUSCFG0_STATUS 0x0006
32 …PSWUSCFG0_REVISION_ID 0x0008
33 …PSWUSCFG0_PROG_INTERFACE 0x0009
34 …PSWUSCFG0_SUB_CLASS 0x000a
35 …PSWUSCFG0_BASE_CLASS 0x000b
36 …PSWUSCFG0_CACHE_LINE 0x000c
[all …]
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| D | nbio_7_0_offset.h | 27 // base address: 0x0
28 …NB_NBCFG0_NB_VENDOR_ID 0x0000
29 …NB_NBCFG0_NB_DEVICE_ID 0x0002
30 …NB_NBCFG0_NB_COMMAND 0x0004
31 …NB_NBCFG0_NB_STATUS 0x0006
32 …NB_NBCFG0_NB_REVISION_ID 0x0008
33 …NB_NBCFG0_NB_REGPROG_INF 0x0009
34 …NB_NBCFG0_NB_SUB_CLASS 0x000a
35 …NB_NBCFG0_NB_BASE_CODE 0x000b
36 …NB_NBCFG0_NB_CACHE_LINE 0x000c
[all …]
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| D | nbio_7_4_offset.h | 27 // base address: 0x0
28 …PSWUSCFG0_VENDOR_ID 0x0000
29 …PSWUSCFG0_DEVICE_ID 0x0002
30 …PSWUSCFG0_COMMAND 0x0004
31 …PSWUSCFG0_STATUS 0x0006
32 …PSWUSCFG0_REVISION_ID 0x0008
33 …PSWUSCFG0_PROG_INTERFACE 0x0009
34 …PSWUSCFG0_SUB_CLASS 0x000a
35 …PSWUSCFG0_BASE_CLASS 0x000b
36 …PSWUSCFG0_CACHE_LINE 0x000c
[all …]
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| /kernel/linux/linux-4.19/drivers/gpu/drm/amd/include/asic_reg/nbio/ |
| D | nbio_6_1_offset.h | 27 // base address: 0x0
28 …PSWUSCFG0_VENDOR_ID 0x0000
29 …PSWUSCFG0_DEVICE_ID 0x0002
30 …PSWUSCFG0_COMMAND 0x0004
31 …PSWUSCFG0_STATUS 0x0006
32 …PSWUSCFG0_REVISION_ID 0x0008
33 …PSWUSCFG0_PROG_INTERFACE 0x0009
34 …PSWUSCFG0_SUB_CLASS 0x000a
35 …PSWUSCFG0_BASE_CLASS 0x000b
36 …PSWUSCFG0_CACHE_LINE 0x000c
[all …]
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| D | nbio_7_0_offset.h | 27 // base address: 0x0
28 …NB_NBCFG0_NB_VENDOR_ID 0x0000
29 …NB_NBCFG0_NB_DEVICE_ID 0x0002
30 …NB_NBCFG0_NB_COMMAND 0x0004
31 …NB_NBCFG0_NB_STATUS 0x0006
32 …NB_NBCFG0_NB_REVISION_ID 0x0008
33 …NB_NBCFG0_NB_REGPROG_INF 0x0009
34 …NB_NBCFG0_NB_SUB_CLASS 0x000a
35 …NB_NBCFG0_NB_BASE_CODE 0x000b
36 …NB_NBCFG0_NB_CACHE_LINE 0x000c
[all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | imx6ull-pinfunc-snvs.h | 13 #define MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x0000 0x0044 0x0000 0x5 0x0
14 #define MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x0004 0x0048 0x0000 0x5 0x0
15 #define MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0008 0x004C 0x0000 0x5 0x0
16 #define MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x000C 0x0050 0x0000 0x5 0x0
17 #define MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0010 0x0054 0x0000 0x5 0x0
18 #define MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0014 0x0058 0x0000 0x5 0x0
19 #define MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0018 0x005C 0x0000 0x5 0x0
20 #define MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x001C 0x0060 0x0000 0x5 0x0
21 #define MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0020 0x0064 0x0000 0x5 0x0
22 #define MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0024 0x0068 0x0000 0x5 0x0
[all …]
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| D | imx6ul-pinfunc.h | 13 #define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0014 0x02a0 0x0000 5 0
14 #define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x0018 0x02a4 0x0000 5 0
16 #define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x001c 0x02a8 0x0000 5 0
17 #define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0020 0x02ac 0x0000 5 0
18 #define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0024 0x02b0 0x0000 5 0
19 #define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0028 0x02b4 0x0000 5 0
20 #define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x002c 0x02b8 0x0000 5 0
21 #define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0030 0x02bc 0x0000 5 0
22 #define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0034 0x02c0 0x0000 5 0
23 #define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0038 0x02c4 0x0000 5 0
[all …]
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| /kernel/linux/linux-4.19/arch/arm/boot/dts/ |
| D | imx6ull-pinfunc-snvs.h | 13 #define MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x0000 0x0044 0x0000 0x5 0x0
14 #define MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x0004 0x0048 0x0000 0x5 0x0
15 #define MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0008 0x004C 0x0000 0x5 0x0
16 #define MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x000C 0x0050 0x0000 0x5 0x0
17 #define MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0010 0x0054 0x0000 0x5 0x0
18 #define MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0014 0x0058 0x0000 0x5 0x0
19 #define MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0018 0x005C 0x0000 0x5 0x0
20 #define MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x001C 0x0060 0x0000 0x5 0x0
21 #define MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0020 0x0064 0x0000 0x5 0x0
22 #define MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0024 0x0068 0x0000 0x5 0x0
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | dove-divider-clock.txt | 11 0 AXI bus clock
19 Control 0 register. This will cover that register, as well as the
26 reg = <0x0064 0x8>;
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/clock/ |
| D | dove-divider-clock.txt | 11 0 AXI bus clock
19 Control 0 register. This will cover that register, as well as the
26 reg = <0x0064 0x8>;
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