Searched +full:0 +full:x021bc000 (Results 1 – 14 of 14) sorted by relevance
33 reg = <0x021bc000 0x4000>;37 reg = <0x38 4>;41 reg = <0x20 4>;
34 reg = <0x021bc000 0x4000>;38 reg = <0x38 4>;42 reg = <0x20 4>;
65 "^.*@[0-9a-f]+$":89 reg = <0x021bc000 0x4000>;93 reg = <0x10 4>;97 reg = <0x38 4>;101 reg = <0x20 4>;
75 reg = <0x021bc000 0x4000>;79 reg = <0x38 4>;83 reg = <0x20 4>;89 reg = <0x020c8000 0x1000>;90 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,91 <0 54 IRQ_TYPE_LEVEL_HIGH>,92 <0 127 IRQ_TYPE_LEVEL_HIGH>;
45 #size-cells = <0>;47 cpu0: cpu@0 {50 reg = <0>;81 reg = <0x00a01000 0x1000>,82 <0x00a00100 0x100>;88 #clock-cells = <0>;95 #clock-cells = <0>;102 #clock-cells = <0>;103 clock-frequency = <0>;109 #clock-cells = <0>;[all …]
41 #size-cells = <0>;43 cpu@0 {46 reg = <0x0>;77 reg = <0x00a01000 0x1000>,78 <0x00a00100 0x100>;85 #clock-cells = <0>;91 #clock-cells = <0>;98 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;108 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;120 reg = <0x00900000 0x20000>;[all …]
56 #size-cells = <0>;58 cpu0: cpu@0 {61 reg = <0>;101 reg = <0x00a01000 0x1000>,102 <0x00a02000 0x2000>,103 <0x00a04000 0x2000>,104 <0x00a06000 0x2000>;119 #clock-cells = <0>;126 #clock-cells = <0>;133 #clock-cells = <0>;[all …]
56 #clock-cells = <0>;62 #clock-cells = <0>;63 clock-frequency = <0>;68 #clock-cells = <0>;76 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;84 #size-cells = <0>;89 lvds-channel@0 {91 #size-cells = <0>;92 reg = <0>;95 port@0 {[all …]
58 #size-cells = <0>;60 cpu0: cpu@0 {63 reg = <0>;97 reg = <0x00a01000 0x1000>,98 <0x00a00100 0x100>;104 #clock-cells = <0>;111 #clock-cells = <0>;118 #clock-cells = <0>;119 clock-frequency = <0>;125 #clock-cells = <0>;[all …]
45 #size-cells = <0>;47 cpu0: cpu@0 {50 reg = <0>;82 #clock-cells = <0>;89 #clock-cells = <0>;96 #clock-cells = <0>;97 clock-frequency = <0>;103 #clock-cells = <0>;104 clock-frequency = <0>;117 reg = <0x00900000 0x20000>;[all …]
48 #size-cells = <0>;50 cpu@0 {53 reg = <0x0>;85 #clock-cells = <0>;91 #clock-cells = <0>;99 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;104 #phy-cells = <0>;116 reg = <0x00900000 0x20000>;124 reg = <0x00a01000 0x1000>,125 <0x00a00100 0x100>;[all …]
56 #size-cells = <0>;58 cpu0: cpu@0 {61 reg = <0>;108 #clock-cells = <0>;115 #clock-cells = <0>;122 #clock-cells = <0>;123 clock-frequency = <0>;129 #clock-cells = <0>;130 clock-frequency = <0>;149 reg = <0x00900000 0x20000>;[all …]
55 #clock-cells = <0>;61 #clock-cells = <0>;62 clock-frequency = <0>;67 #clock-cells = <0>;74 #size-cells = <0>;79 lvds-channel@0 {81 #size-cells = <0>;82 reg = <0>;85 port@0 {86 reg = <0>;[all …]
58 #size-cells = <0>;60 cpu0: cpu@0 {63 reg = <0>;97 #clock-cells = <0>;104 #clock-cells = <0>;111 #clock-cells = <0>;112 clock-frequency = <0>;118 #clock-cells = <0>;119 clock-frequency = <0>;125 #clock-cells = <0>;[all …]