| /kernel/linux/linux-5.10/arch/arm64/crypto/ |
| D | poly1305-core.S_shipped | 29 mov x9,#0xfffffffc0fffffff
30 movk x9,#0x0fff,lsl#48
35 and x7,x7,x9 // &=0ffffffc0fffffff
37 and x8,x8,x9 // &=0ffffffc0ffffffc
96 cmp x17,#0 // is_base2_26?
184 cmp x7,#0 // is_base2_26?
252 and x12,x4,#0x03ffffff // base 2^64 -> base 2^26
255 and x14,x14,#0x03ffffff
259 str w12,[x0,#16*0] // r0
287 .inst 0xd503233f // paciasp
[all …]
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| D | poly1305-armv8.pl | 34 $0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
44 my ($ctx,$inp,$len,$padbit) = map("x$_",(0..3));
78 mov $s1,#0xfffffffc0fffffff
79 movk $s1,#0x0fff,lsl#48
84 and $r0,$r0,$s1 // &=0ffffffc0fffffff
86 and $r1,$r1,$s1 // &=0ffffffc0ffffffc
145 cmp x17,#0 // is_base2_26?
233 cmp $r0,#0 // is_base2_26?
262 my ($R0,$R1,$S1,$R2,$S2,$R3,$S3,$R4,$S4) = map("v$_.4s",(0..8));
313 and x12,$h0,#0x03ffffff // base 2^64 -> base 2^26
[all …]
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| /kernel/linux/linux-4.19/arch/mips/kernel/ |
| D | relocate.c | 43 return 0; in plat_post_relocation()
50 __asm__("rdhwr %0, $1" : "=r" (res)); in get_synci_step()
62 "synci 0(%0)" in sync_icache()
77 return 0; in apply_r_mips_64_rel()
84 return 0; in apply_r_mips_32_rel()
89 unsigned long target_addr = (*loc_orig) & 0x03ffffff; in apply_r_mips_26_rel()
98 target_addr += (unsigned long)loc_orig & ~0x03ffffff; in apply_r_mips_26_rel()
103 if ((target_addr & 0xf0000000) != ((unsigned long)loc_new & 0xf0000000)) { in apply_r_mips_26_rel()
108 target_addr -= (unsigned long)loc_new & ~0x03ffffff; in apply_r_mips_26_rel()
111 *loc_new = (*loc_new & ~0x03ffffff) | (target_addr & 0x03ffffff); in apply_r_mips_26_rel()
[all …]
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| D | module.c | 51 GFP_KERNEL, PAGE_KERNEL, 0, NUMA_NO_NODE, in module_alloc()
52 __builtin_return_address(0)); in module_alloc()
59 return 0; in apply_r_mips_none()
67 return 0; in apply_r_mips_32()
79 if ((v & 0xf0000000) != (((unsigned long)location + 4) & 0xf0000000)) { in apply_r_mips_26()
85 *location = (*location & ~0x03ffffff) | in apply_r_mips_26()
86 ((base + (v >> 2)) & 0x03ffffff); in apply_r_mips_26()
88 return 0; in apply_r_mips_26()
97 *location = (*location & 0xffff0000) | in apply_r_mips_hi16()
98 ((((long long) v + 0x8000LL) >> 16) & 0xffff); in apply_r_mips_hi16()
[all …]
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| /kernel/linux/linux-5.10/arch/mips/kernel/ |
| D | relocate.c | 43 return 0; in plat_post_relocation()
50 __asm__("rdhwr %0, $1" : "=r" (res)); in get_synci_step()
62 "synci 0(%0)" in sync_icache()
77 return 0; in apply_r_mips_64_rel()
84 return 0; in apply_r_mips_32_rel()
89 unsigned long target_addr = (*loc_orig) & 0x03ffffff; in apply_r_mips_26_rel()
98 target_addr += (unsigned long)loc_orig & ~0x03ffffff; in apply_r_mips_26_rel()
103 if ((target_addr & 0xf0000000) != ((unsigned long)loc_new & 0xf0000000)) { in apply_r_mips_26_rel()
108 target_addr -= (unsigned long)loc_new & ~0x03ffffff; in apply_r_mips_26_rel()
111 *loc_new = (*loc_new & ~0x03ffffff) | (target_addr & 0x03ffffff); in apply_r_mips_26_rel()
[all …]
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| D | module.c | 38 GFP_KERNEL, PAGE_KERNEL, 0, NUMA_NO_NODE, in module_alloc()
39 __builtin_return_address(0)); in module_alloc()
46 return 0; in apply_r_mips_none()
54 return 0; in apply_r_mips_32()
66 if ((v & 0xf0000000) != (((unsigned long)location + 4) & 0xf0000000)) { in apply_r_mips_26()
72 *location = (*location & ~0x03ffffff) | in apply_r_mips_26()
73 ((base + (v >> 2)) & 0x03ffffff); in apply_r_mips_26()
75 return 0; in apply_r_mips_26()
84 *location = (*location & 0xffff0000) | in apply_r_mips_hi16()
85 ((((long long) v + 0x8000LL) >> 16) & 0xffff); in apply_r_mips_hi16()
[all …]
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| /kernel/linux/linux-5.10/arch/mips/include/asm/mach-ralink/ |
| D | mt7621.h | 10 #define MT7621_PALMBUS_BASE 0x1C000000
11 #define MT7621_PALMBUS_SIZE 0x03FFFFFF
13 #define MT7621_SYSC_BASE 0x1E000000
15 #define SYSC_REG_CHIP_NAME0 0x00
16 #define SYSC_REG_CHIP_NAME1 0x04
17 #define SYSC_REG_CHIP_REV 0x0c
18 #define SYSC_REG_SYSTEM_CONFIG0 0x10
19 #define SYSC_REG_SYSTEM_CONFIG1 0x14
21 #define CHIP_REV_PKG_MASK 0x1
23 #define CHIP_REV_VER_MASK 0xf
[all …]
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| /kernel/linux/linux-4.19/arch/mips/include/asm/mach-ralink/ |
| D | mt7621.h | 12 #define MT7621_PALMBUS_BASE 0x1C000000
13 #define MT7621_PALMBUS_SIZE 0x03FFFFFF
15 #define MT7621_SYSC_BASE 0x1E000000
17 #define SYSC_REG_CHIP_NAME0 0x00
18 #define SYSC_REG_CHIP_NAME1 0x04
19 #define SYSC_REG_CHIP_REV 0x0c
20 #define SYSC_REG_SYSTEM_CONFIG0 0x10
21 #define SYSC_REG_SYSTEM_CONFIG1 0x14
23 #define CHIP_REV_PKG_MASK 0x1
25 #define CHIP_REV_VER_MASK 0xf
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/ |
| D | faraday,ftpci100.txt | 9 The host controller appear on the PCI bus with vendor ID 0x159b (Faraday
10 Technology) and product ID 0x4321.
23 - bus-range: set to <0x00 0xff>
45 - #address-cells: set to <0>
64 interrupt-map-mask = <0xf800 0 0 7>;
66 <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
67 <0x4800 0 0 2 &pci_intc 1>,
68 <0x4800 0 0 3 &pci_intc 2>,
69 <0x4800 0 0 4 &pci_intc 3>,
70 <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/pci/ |
| D | faraday,ftpci100.txt | 9 The host controller appear on the PCI bus with vendor ID 0x159b (Faraday
10 Technology) and product ID 0x4321.
23 - bus-range: set to <0x00 0xff>
45 - #address-cells: set to <0>
64 interrupt-map-mask = <0xf800 0 0 7>;
66 <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
67 <0x4800 0 0 2 &pci_intc 1>,
68 <0x4800 0 0 3 &pci_intc 2>,
69 <0x4800 0 0 4 &pci_intc 3>,
70 <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
[all …]
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| /kernel/linux/linux-5.10/arch/arm/crypto/ |
| D | poly1305-core.S_shipped | 31 cmp r1,#0
32 str r3,[r0,#0] @ zero hash value
43 moveq r0,#0
54 ldrb r4,[r1,#0]
55 mov r10,#0x0fffffff
57 and r3,r10,#-4 @ 0x0ffffffc
113 str r4,[r0,#0]
124 mov r0,#0
133 .word 0xe12fff1e @ interoperable with Thumb ISA:-)
166 mov r2,#0
[all …]
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| D | poly1305-armv4.pl | 28 $0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
38 ($ctx,$inp,$len,$padbit)=map("r$_",(0..3));
71 cmp $inp,#0
72 str r3,[$ctx,#0] @ zero hash value
83 moveq r0,#0
94 ldrb r4,[$inp,#0]
95 mov r10,#0x0fffffff
97 and r3,r10,#-4 @ 0x0ffffffc
153 str r4,[$ctx,#0]
164 mov r0,#0
[all …]
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| /kernel/linux/linux-4.19/drivers/isdn/hisax/ |
| D | isdnl3.h | 9 #define ALL_STATES 0x03ffffff
11 #define PROTO_DIS_EURO 0x08
13 #define L3_DEB_WARN 0x01
14 #define L3_DEB_PROTERR 0x02
15 #define L3_DEB_STATE 0x04
16 #define L3_DEB_CHARGE 0x08
17 #define L3_DEB_CHECK 0x10
18 #define L3_DEB_SI 0x20
|
| /kernel/linux/linux-4.19/arch/sh/include/mach-common/mach/ |
| D | sh7785lcr.h | 11 * 0x00000000 - 0x03ffffff(CS0) | NOR Flash | NOR Flash
12 * 0x04000000 - 0x05ffffff(CS1) | PLD | PLD
13 * 0x06000000 - 0x07ffffff(CS1) | I2C | I2C
14 * 0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM
15 * 0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM
16 * 0x10000000 - 0x13ffffff(CS4) | SM107 | SM107
17 * 0x14000000 - 0x17ffffff(CS5) | reserved | USB
18 * 0x18000000 - 0x1bffffff(CS6) | reserved | SD
19 * 0x40000000 - 0x5fffffff | DDR SDRAM | (cannot use)
23 #define NOR_FLASH_ADDR 0x00000000
[all …]
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| /kernel/linux/linux-5.10/arch/sh/include/mach-common/mach/ |
| D | sh7785lcr.h | 11 * 0x00000000 - 0x03ffffff(CS0) | NOR Flash | NOR Flash
12 * 0x04000000 - 0x05ffffff(CS1) | PLD | PLD
13 * 0x06000000 - 0x07ffffff(CS1) | I2C | I2C
14 * 0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM
15 * 0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM
16 * 0x10000000 - 0x13ffffff(CS4) | SM107 | SM107
17 * 0x14000000 - 0x17ffffff(CS5) | reserved | USB
18 * 0x18000000 - 0x1bffffff(CS6) | reserved | SD
19 * 0x40000000 - 0x5fffffff | DDR SDRAM | (cannot use)
23 #define NOR_FLASH_ADDR 0x00000000
[all …]
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| /kernel/linux/linux-5.10/arch/openrisc/kernel/ |
| D | module.c | 30 for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { in apply_relocate_add()
54 value &= 0x03ffffff; in apply_relocate_add()
55 value |= *location & 0xfc000000; in apply_relocate_add()
65 return 0; in apply_relocate_add()
|
| /kernel/linux/linux-4.19/arch/openrisc/kernel/ |
| D | module.c | 34 for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { in apply_relocate_add()
58 value &= 0x03ffffff; in apply_relocate_add()
59 value |= *location & 0xfc000000; in apply_relocate_add()
69 return 0; in apply_relocate_add()
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/watchdog/ |
| D | snps,dw-wdt.yaml | 52 default: [0x0001000 0x0002000 0x0004000 0x0008000
53 0x0010000 0x0020000 0x0040000 0x0080000
54 0x0100000 0x0200000 0x0400000 0x0800000
55 0x1000000 0x2000000 0x4000000 0x8000000]
70 reg = <0xffd02000 0x1000>;
71 interrupts = <0 171 4>;
79 reg = <0xffd02000 0x1000>;
80 interrupts = <0 171 4>;
83 snps,watchdog-tops = <0x000000FF 0x000001FF 0x000003FF
84 0x000007FF 0x0000FFFF 0x0001FFFF
[all …]
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| /kernel/linux/linux-5.10/arch/mips/include/asm/ |
| D | inst.h | 25 #define I_JTARGET_SFT 0
26 #define MIPSInst_JTARGET(x) (MIPSInst(x) & 0x03ffffff)
29 #define MIPSInst_RS(x) ((MIPSInst(x) & 0x03e00000) >> I_RS_SFT)
32 #define MIPSInst_RT(x) ((MIPSInst(x) & 0x001f0000) >> I_RT_SFT)
34 #define I_IMM_SFT 0
35 #define MIPSInst_SIMM(x) ((int)((short)(MIPSInst(x) & 0xffff)))
36 #define MIPSInst_UIMM(x) (MIPSInst(x) & 0xffff)
39 #define MIPSInst_CACHEOP(x) ((MIPSInst(x) & 0x001c0000) >> I_CACHEOP_SFT)
42 #define MIPSInst_CACHESEL(x) ((MIPSInst(x) & 0x00030000) >> I_CACHESEL_SFT)
45 #define MIPSInst_RD(x) ((MIPSInst(x) & 0x0000f800) >> I_RD_SFT)
[all …]
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| /kernel/linux/linux-4.19/arch/mips/include/asm/ |
| D | inst.h | 25 #define I_JTARGET_SFT 0
26 #define MIPSInst_JTARGET(x) (MIPSInst(x) & 0x03ffffff)
29 #define MIPSInst_RS(x) ((MIPSInst(x) & 0x03e00000) >> I_RS_SFT)
32 #define MIPSInst_RT(x) ((MIPSInst(x) & 0x001f0000) >> I_RT_SFT)
34 #define I_IMM_SFT 0
35 #define MIPSInst_SIMM(x) ((int)((short)(MIPSInst(x) & 0xffff)))
36 #define MIPSInst_UIMM(x) (MIPSInst(x) & 0xffff)
39 #define MIPSInst_CACHEOP(x) ((MIPSInst(x) & 0x001c0000) >> I_CACHEOP_SFT)
42 #define MIPSInst_CACHESEL(x) ((MIPSInst(x) & 0x00030000) >> I_CACHESEL_SFT)
45 #define MIPSInst_RD(x) ((MIPSInst(x) & 0x0000f800) >> I_RD_SFT)
[all …]
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| /kernel/linux/linux-4.19/arch/arm/boot/dts/ |
| D | gemini.dtsi | 23 pinctrl-0 = <&pflash_default_pins>;
33 reg = <0x40000000 0x1000>;
41 offset = <0x0c>;
43 mask = <0xC0000000>;
51 pinctrl-0 = <&dram_default_pins>, <&system_default_pins>,
161 reg = <0x41000000 0x1000>;
170 reg = <0x42000000 0x100>;
175 pinctrl-0 = <&uart_default_pins>;
181 reg = <0x43000000 0x1000>;
195 reg = <0x45000000 0x100>;
[all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | gemini.dtsi | 23 pinctrl-0 = <&pflash_default_pins>;
33 reg = <0x40000000 0x1000>;
41 offset = <0x0c>;
43 mask = <0xC0000000>;
51 pinctrl-0 = <&dram_default_pins>, <&system_default_pins>,
161 reg = <0x41000000 0x1000>;
170 reg = <0x42000000 0x100>;
175 pinctrl-0 = <&uart_default_pins>;
181 reg = <0x43000000 0x1000>;
195 reg = <0x45000000 0x100>;
[all …]
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| /kernel/linux/linux-4.19/drivers/video/console/ |
| D | sticore.c | 43 * 0 - Black
56 0, 6, 4, 5,
62 #define c_index(sti, c) ((c) & 0xff)
84 memset(inptr, 0, sizeof(*inptr)); in sti_init_graph()
86 memset(inptr_ext, 0, sizeof(*inptr_ext)); in sti_init_graph()
88 outptr->errno = 0; in sti_init_graph()
93 if (ret >= 0) in sti_init_graph()
99 if (ret < 0) { in sti_init_graph()
104 return 0; in sti_init_graph()
122 memset(inptr, 0, sizeof(*inptr)); in sti_inq_conf()
[all …]
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| /kernel/linux/linux-5.10/drivers/video/console/ |
| D | sticore.c | 46 * 0 - Black
59 0, 6, 4, 5,
65 #define c_index(sti, c) ((c) & 0xff)
87 memset(inptr, 0, sizeof(*inptr)); in sti_init_graph()
89 memset(inptr_ext, 0, sizeof(*inptr_ext)); in sti_init_graph()
91 outptr->errno = 0; in sti_init_graph()
96 if (ret >= 0) in sti_init_graph()
102 if (ret < 0) { in sti_init_graph()
107 return 0; in sti_init_graph()
125 memset(inptr, 0, sizeof(*inptr)); in sti_inq_conf()
[all …]
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| /kernel/linux/linux-5.10/drivers/pcmcia/ |
| D | tcic.h | 33 #define TCIC_BASE 0x240
36 #define TCIC_DATA 0x00
37 #define TCIC_ADDR 0x02
38 #define TCIC_SCTRL 0x06
39 #define TCIC_SSTAT 0x07
40 #define TCIC_MODE 0x08
41 #define TCIC_PWR 0x09
42 #define TCIC_EDC 0x0A
43 #define TCIC_ICSR 0x0C
44 #define TCIC_IENA 0x0D
[all …]
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