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/kernel/linux/linux-4.19/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/
Dgf100.c30 u32 addr = nvkm_rd32(device, 0x122120 + (i * 0x0400)); in gf100_ibus_intr_hub()
31 u32 data = nvkm_rd32(device, 0x122124 + (i * 0x0400)); in gf100_ibus_intr_hub()
32 u32 stat = nvkm_rd32(device, 0x122128 + (i * 0x0400)); in gf100_ibus_intr_hub()
34 nvkm_mask(device, 0x122128 + (i * 0x0400), 0x00000200, 0x00000000); in gf100_ibus_intr_hub()
41 u32 addr = nvkm_rd32(device, 0x124120 + (i * 0x0400)); in gf100_ibus_intr_rop()
42 u32 data = nvkm_rd32(device, 0x124124 + (i * 0x0400)); in gf100_ibus_intr_rop()
43 u32 stat = nvkm_rd32(device, 0x124128 + (i * 0x0400)); in gf100_ibus_intr_rop()
45 nvkm_mask(device, 0x124128 + (i * 0x0400), 0x00000200, 0x00000000); in gf100_ibus_intr_rop()
52 u32 addr = nvkm_rd32(device, 0x128120 + (i * 0x0400)); in gf100_ibus_intr_gpc()
53 u32 data = nvkm_rd32(device, 0x128124 + (i * 0x0400)); in gf100_ibus_intr_gpc()
[all …]
/kernel/linux/linux-4.19/include/linux/mfd/wm8350/
Dcore.h32 #define WM8350_RESET_ID 0x00
33 #define WM8350_ID 0x01
34 #define WM8350_REVISION 0x02
35 #define WM8350_SYSTEM_CONTROL_1 0x03
36 #define WM8350_SYSTEM_CONTROL_2 0x04
37 #define WM8350_SYSTEM_HIBERNATE 0x05
38 #define WM8350_INTERFACE_CONTROL 0x06
39 #define WM8350_POWER_MGMT_1 0x08
40 #define WM8350_POWER_MGMT_2 0x09
41 #define WM8350_POWER_MGMT_3 0x0A
[all …]
Dgpio.h21 #define WM8350_GPIO_DEBOUNCE 0x80
22 #define WM8350_GPIO_PIN_PULL_UP_CONTROL 0x81
23 #define WM8350_GPIO_PULL_DOWN_CONTROL 0x82
24 #define WM8350_GPIO_INT_MODE 0x83
25 #define WM8350_GPIO_CONTROL 0x85
26 #define WM8350_GPIO_CONFIGURATION_I_O 0x86
27 #define WM8350_GPIO_PIN_POLARITY_TYPE 0x87
28 #define WM8350_GPIO_FUNCTION_SELECT_1 0x8C
29 #define WM8350_GPIO_FUNCTION_SELECT_2 0x8D
30 #define WM8350_GPIO_FUNCTION_SELECT_3 0x8E
[all …]
/kernel/linux/linux-5.10/include/linux/mfd/wm8350/
Dcore.h27 #define WM8350_RESET_ID 0x00
28 #define WM8350_ID 0x01
29 #define WM8350_REVISION 0x02
30 #define WM8350_SYSTEM_CONTROL_1 0x03
31 #define WM8350_SYSTEM_CONTROL_2 0x04
32 #define WM8350_SYSTEM_HIBERNATE 0x05
33 #define WM8350_INTERFACE_CONTROL 0x06
34 #define WM8350_POWER_MGMT_1 0x08
35 #define WM8350_POWER_MGMT_2 0x09
36 #define WM8350_POWER_MGMT_3 0x0A
[all …]
Dgpio.h16 #define WM8350_GPIO_DEBOUNCE 0x80
17 #define WM8350_GPIO_PIN_PULL_UP_CONTROL 0x81
18 #define WM8350_GPIO_PULL_DOWN_CONTROL 0x82
19 #define WM8350_GPIO_INT_MODE 0x83
20 #define WM8350_GPIO_CONTROL 0x85
21 #define WM8350_GPIO_CONFIGURATION_I_O 0x86
22 #define WM8350_GPIO_PIN_POLARITY_TYPE 0x87
23 #define WM8350_GPIO_FUNCTION_SELECT_1 0x8C
24 #define WM8350_GPIO_FUNCTION_SELECT_2 0x8D
25 #define WM8350_GPIO_FUNCTION_SELECT_3 0x8E
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/
Dgf100.c31 u32 addr = nvkm_rd32(device, 0x122120 + (i * 0x0400)); in gf100_ibus_intr_hub()
32 u32 data = nvkm_rd32(device, 0x122124 + (i * 0x0400)); in gf100_ibus_intr_hub()
33 u32 stat = nvkm_rd32(device, 0x122128 + (i * 0x0400)); in gf100_ibus_intr_hub()
41 u32 addr = nvkm_rd32(device, 0x124120 + (i * 0x0400)); in gf100_ibus_intr_rop()
42 u32 data = nvkm_rd32(device, 0x124124 + (i * 0x0400)); in gf100_ibus_intr_rop()
43 u32 stat = nvkm_rd32(device, 0x124128 + (i * 0x0400)); in gf100_ibus_intr_rop()
51 u32 addr = nvkm_rd32(device, 0x128120 + (i * 0x0400)); in gf100_ibus_intr_gpc()
52 u32 data = nvkm_rd32(device, 0x128124 + (i * 0x0400)); in gf100_ibus_intr_gpc()
53 u32 stat = nvkm_rd32(device, 0x128128 + (i * 0x0400)); in gf100_ibus_intr_gpc()
61 u32 intr0 = nvkm_rd32(device, 0x121c58); in gf100_ibus_intr()
[all …]
/kernel/linux/linux-5.10/drivers/clk/samsung/
Dclk-exynos5260.h15 #define MUX_SEL_AUD 0x0200
16 #define MUX_ENABLE_AUD 0x0300
17 #define MUX_STAT_AUD 0x0400
18 #define MUX_IGNORE_AUD 0x0500
19 #define DIV_AUD0 0x0600
20 #define DIV_AUD1 0x0604
21 #define DIV_STAT_AUD0 0x0700
22 #define DIV_STAT_AUD1 0x0704
23 #define EN_ACLK_AUD 0x0800
24 #define EN_PCLK_AUD 0x0900
[all …]
/kernel/linux/linux-4.19/drivers/clk/samsung/
Dclk-exynos5260.h18 #define MUX_SEL_AUD 0x0200
19 #define MUX_ENABLE_AUD 0x0300
20 #define MUX_STAT_AUD 0x0400
21 #define MUX_IGNORE_AUD 0x0500
22 #define DIV_AUD0 0x0600
23 #define DIV_AUD1 0x0604
24 #define DIV_STAT_AUD0 0x0700
25 #define DIV_STAT_AUD1 0x0704
26 #define EN_ACLK_AUD 0x0800
27 #define EN_PCLK_AUD 0x0900
[all …]
/kernel/linux/patches/linux-5.10/prebuilts/usr/include/linux/
Dmii.h23 #define MII_BMCR 0x00
24 #define MII_BMSR 0x01
25 #define MII_PHYSID1 0x02
26 #define MII_PHYSID2 0x03
27 #define MII_ADVERTISE 0x04
28 #define MII_LPA 0x05
29 #define MII_EXPANSION 0x06
30 #define MII_CTRL1000 0x09
31 #define MII_STAT1000 0x0a
32 #define MII_MMD_CTRL 0x0d
[all …]
/kernel/linux/linux-4.19/drivers/net/ethernet/cirrus/
Dcs89x0.h18 #define PP_ChipID 0x0000 /* offset 0h -> Corp -ID */
22 #define PP_ISAIOB 0x0020 /* IO base address */
23 #define PP_CS8900_ISAINT 0x0022 /* ISA interrupt select */
24 #define PP_CS8920_ISAINT 0x0370 /* ISA interrupt select */
25 #define PP_CS8900_ISADMA 0x0024 /* ISA Rec DMA channel */
26 #define PP_CS8920_ISADMA 0x0374 /* ISA Rec DMA channel */
27 #define PP_ISASOF 0x0026 /* ISA DMA offset */
28 #define PP_DmaFrameCnt 0x0028 /* ISA DMA Frame count */
29 #define PP_DmaByteCnt 0x002A /* ISA DMA Byte count */
30 #define PP_CS8900_ISAMemB 0x002C /* Memory base */
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/cirrus/
Dcs89x0.h18 #define PP_ChipID 0x0000 /* offset 0h -> Corp -ID */
22 #define PP_ISAIOB 0x0020 /* IO base address */
23 #define PP_CS8900_ISAINT 0x0022 /* ISA interrupt select */
24 #define PP_CS8920_ISAINT 0x0370 /* ISA interrupt select */
25 #define PP_CS8900_ISADMA 0x0024 /* ISA Rec DMA channel */
26 #define PP_CS8920_ISADMA 0x0374 /* ISA Rec DMA channel */
27 #define PP_ISASOF 0x0026 /* ISA DMA offset */
28 #define PP_DmaFrameCnt 0x0028 /* ISA DMA Frame count */
29 #define PP_DmaByteCnt 0x002A /* ISA DMA Byte count */
30 #define PP_CS8900_ISAMemB 0x002C /* Memory base */
[all …]
/kernel/linux/linux-5.10/arch/sh/include/asm/
Dsmc37c93x.h14 #define FDC_PRIMARY_BASE 0x3f0
15 #define IDE1_PRIMARY_BASE 0x1f0
16 #define IDE1_SECONDARY_BASE 0x170
17 #define PARPORT_PRIMARY_BASE 0x378
18 #define COM1_PRIMARY_BASE 0x2f8
19 #define COM2_PRIMARY_BASE 0x3f8
20 #define RTC_PRIMARY_BASE 0x070
21 #define KBC_PRIMARY_BASE 0x060
22 #define AUXIO_PRIMARY_BASE 0x000 /* XXX */
25 #define LDN_FDC 0
[all …]
/kernel/linux/linux-4.19/arch/sh/include/asm/
Dsmc37c93x.h14 #define FDC_PRIMARY_BASE 0x3f0
15 #define IDE1_PRIMARY_BASE 0x1f0
16 #define IDE1_SECONDARY_BASE 0x170
17 #define PARPORT_PRIMARY_BASE 0x378
18 #define COM1_PRIMARY_BASE 0x2f8
19 #define COM2_PRIMARY_BASE 0x3f8
20 #define RTC_PRIMARY_BASE 0x070
21 #define KBC_PRIMARY_BASE 0x060
22 #define AUXIO_PRIMARY_BASE 0x000 /* XXX */
25 #define LDN_FDC 0
[all …]
/kernel/linux/patches/linux-4.19/prebuilts/usr/include/linux/
Dmii.h10 #define MII_BMCR 0x00
11 #define MII_BMSR 0x01
12 #define MII_PHYSID1 0x02
13 #define MII_PHYSID2 0x03
14 #define MII_ADVERTISE 0x04
15 #define MII_LPA 0x05
16 #define MII_EXPANSION 0x06
17 #define MII_CTRL1000 0x09
18 #define MII_STAT1000 0x0a
19 #define MII_MMD_CTRL 0x0d
[all …]
/kernel/linux/linux-4.19/drivers/media/platform/ti-vpe/
Dcsc.c36 #define CSC_COEFFS_VIDEO_RANGE_Y2R 0
46 0x0400, 0x0000, 0x057D, 0x0400, 0x1EA7, 0x1D35,
47 0x0400, 0x06EF, 0x1FFE, 0x0D40, 0x0210, 0x0C88,
51 0x0400, 0x0000, 0x0629, 0x0400, 0x1F45, 0x1E2B,
52 0x0400, 0x0742, 0x0000, 0x0CEC, 0x0148, 0x0C60,
58 0x04A8, 0x1FFE, 0x0662, 0x04A8, 0x1E6F, 0x1CBF,
59 0x04A8, 0x0812, 0x1FFF, 0x0C84, 0x0220, 0x0BAC,
63 0x04A8, 0x0000, 0x072C, 0x04A8, 0x1F26, 0x1DDE,
64 0x04A8, 0x0873, 0x0000, 0x0C20, 0x0134, 0x0B7C,
70 0x0132, 0x0259, 0x0075, 0x1F50, 0x1EA5, 0x020B,
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/mediatek/mt76/mt7915/
Ddma.c18 err = mt76_queue_alloc(dev, hwq, MT7915_TXQ_BAND0, n_desc, 0, in mt7915_init_tx_queues()
20 if (err < 0) in mt7915_init_tx_queues()
23 for (i = 0; i < MT_TXQ_MCU; i++) in mt7915_init_tx_queues()
26 return 0; in mt7915_init_tx_queues()
39 err = mt76_queue_alloc(dev, hwq, idx, n_desc, 0, MT_TX_RING_BASE); in mt7915_init_mcu_queue()
40 if (err < 0) in mt7915_init_mcu_queue()
45 return 0; in mt7915_init_mcu_queue()
55 type = FIELD_GET(MT_RXD0_PKT_TYPE, le32_to_cpu(rxd[0])); in mt7915_queue_rx_skb()
91 if (napi_complete_done(napi, 0)) in mt7915_poll_tx()
94 return 0; in mt7915_poll_tx()
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/amd/
Dam79c961a.h9 /* use 0 for production, 1 for verification, >2 for debug. debug flags: */
15 #define NET_DEBUG 0
18 #define NET_UID 0
19 #define NET_RDP 0x10
20 #define NET_RAP 0x12
21 #define NET_RESET 0x14
22 #define NET_IDP 0x16
27 #define CSR0 0
28 #define CSR0_INIT 0x0001
29 #define CSR0_STRT 0x0002
[all …]
/kernel/linux/linux-5.10/include/uapi/linux/
Dmii.h16 #define MII_BMCR 0x00 /* Basic mode control register */
17 #define MII_BMSR 0x01 /* Basic mode status register */
18 #define MII_PHYSID1 0x02 /* PHYS ID 1 */
19 #define MII_PHYSID2 0x03 /* PHYS ID 2 */
20 #define MII_ADVERTISE 0x04 /* Advertisement control reg */
21 #define MII_LPA 0x05 /* Link partner ability reg */
22 #define MII_EXPANSION 0x06 /* Expansion register */
23 #define MII_CTRL1000 0x09 /* 1000BASE-T control */
24 #define MII_STAT1000 0x0a /* 1000BASE-T status */
25 #define MII_MMD_CTRL 0x0d /* MMD Access Control Register */
[all …]
/kernel/linux/linux-5.10/include/linux/mfd/
Dwm8400-private.h16 #define WM8400_REGISTER_COUNT 0x55
28 #define WM8400_RESET_ID 0x00
29 #define WM8400_ID 0x01
30 #define WM8400_POWER_MANAGEMENT_1 0x02
31 #define WM8400_POWER_MANAGEMENT_2 0x03
32 #define WM8400_POWER_MANAGEMENT_3 0x04
33 #define WM8400_AUDIO_INTERFACE_1 0x05
34 #define WM8400_AUDIO_INTERFACE_2 0x06
35 #define WM8400_CLOCKING_1 0x07
36 #define WM8400_CLOCKING_2 0x08
[all …]
/kernel/linux/linux-4.19/drivers/net/ethernet/amd/
Dam79c961a.h12 /* use 0 for production, 1 for verification, >2 for debug. debug flags: */
18 #define NET_DEBUG 0
21 #define NET_UID 0
22 #define NET_RDP 0x10
23 #define NET_RAP 0x12
24 #define NET_RESET 0x14
25 #define NET_IDP 0x16
30 #define CSR0 0
31 #define CSR0_INIT 0x0001
32 #define CSR0_STRT 0x0002
[all …]
/kernel/linux/linux-4.19/include/linux/mfd/
Dwm8400-private.h29 #define WM8400_REGISTER_COUNT 0x55
41 #define WM8400_RESET_ID 0x00
42 #define WM8400_ID 0x01
43 #define WM8400_POWER_MANAGEMENT_1 0x02
44 #define WM8400_POWER_MANAGEMENT_2 0x03
45 #define WM8400_POWER_MANAGEMENT_3 0x04
46 #define WM8400_AUDIO_INTERFACE_1 0x05
47 #define WM8400_AUDIO_INTERFACE_2 0x06
48 #define WM8400_CLOCKING_1 0x07
49 #define WM8400_CLOCKING_2 0x08
[all …]
/kernel/linux/linux-5.10/arch/mips/include/asm/mach-db1x00/
Dbcsr.h23 #define DB1000_BCSR_PHYS_ADDR 0x0E000000
24 #define DB1000_BCSR_HEXLED_OFS 0x01000000
26 #define DB1550_BCSR_PHYS_ADDR 0x0F000000
27 #define DB1550_BCSR_HEXLED_OFS 0x00400000
29 #define PB1550_BCSR_PHYS_ADDR 0x0F000000
30 #define PB1550_BCSR_HEXLED_OFS 0x00800000
32 #define DB1200_BCSR_PHYS_ADDR 0x19800000
33 #define DB1200_BCSR_HEXLED_OFS 0x00400000
35 #define PB1200_BCSR_PHYS_ADDR 0x0D800000
36 #define PB1200_BCSR_HEXLED_OFS 0x00400000
[all …]
/kernel/linux/linux-4.19/arch/mips/include/asm/mach-db1x00/
Dbcsr.h23 #define DB1000_BCSR_PHYS_ADDR 0x0E000000
24 #define DB1000_BCSR_HEXLED_OFS 0x01000000
26 #define DB1550_BCSR_PHYS_ADDR 0x0F000000
27 #define DB1550_BCSR_HEXLED_OFS 0x00400000
29 #define PB1550_BCSR_PHYS_ADDR 0x0F000000
30 #define PB1550_BCSR_HEXLED_OFS 0x00800000
32 #define DB1200_BCSR_PHYS_ADDR 0x19800000
33 #define DB1200_BCSR_HEXLED_OFS 0x00400000
35 #define PB1200_BCSR_PHYS_ADDR 0x0D800000
36 #define PB1200_BCSR_HEXLED_OFS 0x00400000
[all …]
/kernel/linux/linux-4.19/include/linux/mfd/wm831x/
Dregulator.h19 * R16462 (0x404E) - Current Sink 1
21 #define WM831X_CS1_ENA 0x8000 /* CS1_ENA */
22 #define WM831X_CS1_ENA_MASK 0x8000 /* CS1_ENA */
25 #define WM831X_CS1_DRIVE 0x4000 /* CS1_DRIVE */
26 #define WM831X_CS1_DRIVE_MASK 0x4000 /* CS1_DRIVE */
29 #define WM831X_CS1_SLPENA 0x1000 /* CS1_SLPENA */
30 #define WM831X_CS1_SLPENA_MASK 0x1000 /* CS1_SLPENA */
33 #define WM831X_CS1_OFF_RAMP_MASK 0x0C00 /* CS1_OFF_RAMP - [11:10] */
36 #define WM831X_CS1_ON_RAMP_MASK 0x0300 /* CS1_ON_RAMP - [9:8] */
39 #define WM831X_CS1_ISEL_MASK 0x003F /* CS1_ISEL - [5:0] */
[all …]
/kernel/linux/linux-5.10/include/linux/mfd/wm831x/
Dregulator.h14 * R16462 (0x404E) - Current Sink 1
16 #define WM831X_CS1_ENA 0x8000 /* CS1_ENA */
17 #define WM831X_CS1_ENA_MASK 0x8000 /* CS1_ENA */
20 #define WM831X_CS1_DRIVE 0x4000 /* CS1_DRIVE */
21 #define WM831X_CS1_DRIVE_MASK 0x4000 /* CS1_DRIVE */
24 #define WM831X_CS1_SLPENA 0x1000 /* CS1_SLPENA */
25 #define WM831X_CS1_SLPENA_MASK 0x1000 /* CS1_SLPENA */
28 #define WM831X_CS1_OFF_RAMP_MASK 0x0C00 /* CS1_OFF_RAMP - [11:10] */
31 #define WM831X_CS1_ON_RAMP_MASK 0x0300 /* CS1_ON_RAMP - [9:8] */
34 #define WM831X_CS1_ISEL_MASK 0x003F /* CS1_ISEL - [5:0] */
[all …]

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