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/kernel/linux/linux-5.10/drivers/pinctrl/mediatek/
Dpinctrl-mt8183.c13 * iocfg[0]:0x10005000, iocfg[1]:0x11F20000, iocfg[2]:0x11E80000,
14 * iocfg[3]:0x11E70000, iocfg[4]:0x11E90000, iocfg[5]:0x11D30000,
15 * iocfg[6]:0x11D20000, iocfg[7]:0x11C50000, iocfg[8]:0x11F30000.
21 _x_bits, 32, 0)
28 PIN_FIELD(0, 192, 0x300, 0x10, 0, 4),
32 PIN_FIELD(0, 192, 0x0, 0x10, 0, 1),
36 PIN_FIELD(0, 192, 0x200, 0x10, 0, 1),
40 PIN_FIELD(0, 192, 0x100, 0x10, 0, 1),
44 PINS_FIELD_BASE(0, 3, 6, 0x000, 0x10, 3, 1),
45 PINS_FIELD_BASE(4, 7, 6, 0x000, 0x10, 5, 1),
[all …]
Dpinctrl-mt6397.c18 #define MT6397_PIN_REG_BASE 0xc000
23 .dir_offset = (MT6397_PIN_REG_BASE + 0x000),
26 .pullen_offset = (MT6397_PIN_REG_BASE + 0x020),
27 .pullsel_offset = (MT6397_PIN_REG_BASE + 0x040),
28 .dout_offset = (MT6397_PIN_REG_BASE + 0x080),
29 .din_offset = (MT6397_PIN_REG_BASE + 0x0a0),
30 .pinmux_offset = (MT6397_PIN_REG_BASE + 0x0c0),
34 .port_mask = 0x3,
/kernel/linux/linux-5.10/drivers/pinctrl/samsung/
Dpinctrl-exynos-arm.c27 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
32 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
36 #define S5P_OTHERS 0xE000
73 clk_base = of_iomap(np, 0); in s5pv210_retention_init()
93 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
94 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04),
95 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
96 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
97 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
98 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
[all …]
Dpinctrl-exynos-arm64.c24 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
29 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
35 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
40 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
49 EXYNOS5433_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
50 EXYNOS5433_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
51 EXYNOS5433_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
52 EXYNOS5433_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
53 EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x020, "gpf1", 0x1004, 1),
54 EXYNOS5433_PIN_BANK_EINTW_EXT(4, 0x040, "gpf2", 0x1008, 1),
[all …]
/kernel/linux/linux-4.19/drivers/pinctrl/samsung/
Dpinctrl-exynos-arm.c27 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
32 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
36 #define S5P_OTHERS 0xE000
73 clk_base = of_iomap(np, 0); in s5pv210_retention_init()
93 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
94 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04),
95 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
96 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
97 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
98 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
[all …]
Dpinctrl-exynos-arm64.c24 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
29 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
35 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
40 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
49 EXYNOS5433_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
50 EXYNOS5433_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
51 EXYNOS5433_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
52 EXYNOS5433_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
53 EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x020, "gpf1", 0x1004, 1),
54 EXYNOS5433_PIN_BANK_EINTW_EXT(4, 0x040, "gpf2", 0x1008, 1),
[all …]
/kernel/linux/linux-4.19/arch/mips/include/asm/
Dr4kcache.h47 " cache %0, %1 \n" \
57 for (redundance = 0; redundance < mt_n_iflushes; redundance++) {
65 for (redundance = 0; redundance < mt_n_dflushes; redundance++) {
152 int __err = 0; \
161 "3: li %0, %3 \n" \
175 int __err = 0; \
185 "3: li %0, %3 \n" \
252 " cache %1, 0x000(%0); cache %1, 0x010(%0) \n" \
253 " cache %1, 0x020(%0); cache %1, 0x030(%0) \n" \
254 " cache %1, 0x040(%0); cache %1, 0x050(%0) \n" \
[all …]
/kernel/linux/linux-5.10/include/linux/spi/
Dmxs-spi.h19 #define HW_SSP_CTRL0 0x000
27 #define BM_SSP_CTRL0_BUS_WIDTH (0x3 << 22)
33 #define BP_SSP_CTRL0_XFER_COUNT 0
34 #define BM_SSP_CTRL0_XFER_COUNT 0xffff
35 #define HW_SSP_CMD0 0x010
41 #define BM_SSP_CMD0_BLOCK_SIZE (0xf << 16)
43 #define BM_SSP_CMD0_BLOCK_COUNT (0xff << 8)
44 #define BP_SSP_CMD0_CMD 0
45 #define BM_SSP_CMD0_CMD 0xff
46 #define HW_SSP_CMD1 0x020
[all …]
/kernel/linux/linux-4.19/include/linux/spi/
Dmxs-spi.h28 #define HW_SSP_CTRL0 0x000
36 #define BM_SSP_CTRL0_BUS_WIDTH (0x3 << 22)
42 #define BP_SSP_CTRL0_XFER_COUNT 0
43 #define BM_SSP_CTRL0_XFER_COUNT 0xffff
44 #define HW_SSP_CMD0 0x010
50 #define BM_SSP_CMD0_BLOCK_SIZE (0xf << 16)
52 #define BM_SSP_CMD0_BLOCK_COUNT (0xff << 8)
53 #define BP_SSP_CMD0_CMD 0
54 #define BM_SSP_CMD0_CMD 0xff
55 #define HW_SSP_CMD1 0x020
[all …]
/kernel/linux/linux-4.19/arch/arm/mach-spear/include/mach/
Dmisc_regs.h20 #define DMA_CHN_CFG (MISC_BASE + 0x0A0)
/kernel/linux/linux-5.10/arch/arm/mach-spear/include/mach/
Dmisc_regs.h20 #define DMA_CHN_CFG (MISC_BASE + 0x0A0)
/kernel/linux/patches/linux-4.19/prebuilts/usr/include/linux/
Dvirtio_mmio.h8 #define VIRTIO_MMIO_MAGIC_VALUE 0x000
9 #define VIRTIO_MMIO_VERSION 0x004
10 #define VIRTIO_MMIO_DEVICE_ID 0x008
11 #define VIRTIO_MMIO_VENDOR_ID 0x00c
12 #define VIRTIO_MMIO_DEVICE_FEATURES 0x010
13 #define VIRTIO_MMIO_DEVICE_FEATURES_SEL 0x014
14 #define VIRTIO_MMIO_DRIVER_FEATURES 0x020
15 #define VIRTIO_MMIO_DRIVER_FEATURES_SEL 0x024
17 #define VIRTIO_MMIO_GUEST_PAGE_SIZE 0x028
19 #define VIRTIO_MMIO_QUEUE_SEL 0x030
[all …]
/kernel/linux/linux-4.19/drivers/phy/qualcomm/
Dphy-qcom-qmp.h10 #define QSERDES_COM_BG_TIMER 0x00c
11 #define QSERDES_COM_SSC_EN_CENTER 0x010
12 #define QSERDES_COM_SSC_ADJ_PER1 0x014
13 #define QSERDES_COM_SSC_ADJ_PER2 0x018
14 #define QSERDES_COM_SSC_PER1 0x01c
15 #define QSERDES_COM_SSC_PER2 0x020
16 #define QSERDES_COM_SSC_STEP_SIZE1 0x024
17 #define QSERDES_COM_SSC_STEP_SIZE2 0x028
18 #define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034
19 #define QSERDES_COM_CLK_ENABLE1 0x038
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/mediatek/mt76/mt7603/
Deeprom.h9 MT_EE_CHIP_ID = 0x000,
10 MT_EE_VERSION = 0x002,
11 MT_EE_MAC_ADDR = 0x004,
12 MT_EE_NIC_CONF_0 = 0x034,
13 MT_EE_NIC_CONF_1 = 0x036,
14 MT_EE_NIC_CONF_2 = 0x042,
16 MT_EE_XTAL_TRIM_1 = 0x03a,
18 MT_EE_RSSI_OFFSET_2G = 0x046,
19 MT_EE_WIFI_RF_SETTING = 0x048,
20 MT_EE_RSSI_OFFSET_5G = 0x04a,
[all …]
/kernel/linux/linux-5.10/sound/soc/meson/
Daiu.h18 PCLK = 0,
63 #define AIU_IEC958_BPF 0x000
64 #define AIU_958_MISC 0x010
65 #define AIU_IEC958_DCU_FF_CTRL 0x01c
66 #define AIU_958_CHSTAT_L0 0x020
67 #define AIU_958_CHSTAT_L1 0x024
68 #define AIU_958_CTRL 0x028
69 #define AIU_I2S_SOURCE_DESC 0x034
70 #define AIU_I2S_DAC_CFG 0x040
71 #define AIU_I2S_SYNC 0x044
[all …]
/kernel/linux/linux-5.10/drivers/clk/mediatek/
Dclk-mt7622.c295 .set_ofs = 0x8,
296 .clr_ofs = 0x8,
297 .sta_ofs = 0x8,
301 .set_ofs = 0x40,
302 .clr_ofs = 0x44,
303 .sta_ofs = 0x48,
307 .set_ofs = 0x120,
308 .clr_ofs = 0x120,
309 .sta_ofs = 0x120,
313 .set_ofs = 0x128,
[all …]
Dclk-mt7629.c314 .set_ofs = 0x8,
315 .clr_ofs = 0x8,
316 .sta_ofs = 0x8,
320 .set_ofs = 0x40,
321 .clr_ofs = 0x44,
322 .sta_ofs = 0x48,
326 .set_ofs = 0x8,
327 .clr_ofs = 0x10,
328 .sta_ofs = 0x18,
332 .set_ofs = 0xC,
[all …]
/kernel/linux/linux-4.19/drivers/clk/mediatek/
Dclk-mt7622.c303 .set_ofs = 0x8,
304 .clr_ofs = 0x8,
305 .sta_ofs = 0x8,
309 .set_ofs = 0x40,
310 .clr_ofs = 0x44,
311 .sta_ofs = 0x48,
315 .set_ofs = 0x120,
316 .clr_ofs = 0x120,
317 .sta_ofs = 0x120,
321 .set_ofs = 0x128,
[all …]
/kernel/linux/linux-4.19/drivers/pinctrl/mediatek/
Dpinctrl-mt6397.c26 #define MT6397_PIN_REG_BASE 0xc000
31 .dir_offset = (MT6397_PIN_REG_BASE + 0x000),
34 .pullen_offset = (MT6397_PIN_REG_BASE + 0x020),
35 .pullsel_offset = (MT6397_PIN_REG_BASE + 0x040),
36 .dout_offset = (MT6397_PIN_REG_BASE + 0x080),
37 .din_offset = (MT6397_PIN_REG_BASE + 0x0a0),
38 .pinmux_offset = (MT6397_PIN_REG_BASE + 0x0c0),
42 .port_mask = 0x3,
/kernel/linux/linux-5.10/drivers/platform/x86/
Ddcdbas.h17 #define HC_ACTION_NONE (0)
21 #define HC_SMITYPE_NONE (0)
26 #define ESM_APM_CMD (0x0A0)
27 #define ESM_APM_POWER_CYCLE (0x10)
30 #define CMOS_BASE_PORT (0x070)
31 #define CMOS_PAGE1_INDEX_PORT (0)
35 #define PE1400_APM_CONTROL_PORT (0x0B0)
36 #define PCAT_APM_CONTROL_PORT (0x0B2)
37 #define PCAT_APM_STATUS_PORT (0x0B3)
38 #define PE1300_CMOS_CMD_STRUCT_PTR (0x38)
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/
Ddc_dsc.h29 #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_0 0x0a0 /* DP 1.4a SCR */
30 #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 0x0a1
31 #define DP_DSC_BRANCH_MAX_LINE_WIDTH 0x0a2
50 int max_slices_h; // Maximum available if 0
/kernel/linux/linux-4.19/drivers/clk/meson/
Daxg-audio.h16 #define AUDIO_CLK_GATE_EN 0x000
17 #define AUDIO_MCLK_A_CTRL 0x004
18 #define AUDIO_MCLK_B_CTRL 0x008
19 #define AUDIO_MCLK_C_CTRL 0x00C
20 #define AUDIO_MCLK_D_CTRL 0x010
21 #define AUDIO_MCLK_E_CTRL 0x014
22 #define AUDIO_MCLK_F_CTRL 0x018
23 #define AUDIO_MST_A_SCLK_CTRL0 0x040
24 #define AUDIO_MST_A_SCLK_CTRL1 0x044
25 #define AUDIO_MST_B_SCLK_CTRL0 0x048
[all …]
/kernel/linux/linux-4.19/drivers/firmware/
Ddcdbas.h7 * it under the terms of the GNU General Public License v2.0 as published by
25 #define HC_ACTION_NONE (0)
29 #define HC_SMITYPE_NONE (0)
34 #define ESM_APM_CMD (0x0A0)
35 #define ESM_APM_POWER_CYCLE (0x10)
38 #define CMOS_BASE_PORT (0x070)
39 #define CMOS_PAGE1_INDEX_PORT (0)
43 #define PE1400_APM_CONTROL_PORT (0x0B0)
44 #define PCAT_APM_CONTROL_PORT (0x0B2)
45 #define PCAT_APM_STATUS_PORT (0x0B3)
[all …]
/kernel/linux/linux-5.10/drivers/clk/meson/
Daxg-audio.h16 #define AUDIO_CLK_GATE_EN 0x000
17 #define AUDIO_MCLK_A_CTRL 0x004
18 #define AUDIO_MCLK_B_CTRL 0x008
19 #define AUDIO_MCLK_C_CTRL 0x00C
20 #define AUDIO_MCLK_D_CTRL 0x010
21 #define AUDIO_MCLK_E_CTRL 0x014
22 #define AUDIO_MCLK_F_CTRL 0x018
23 #define AUDIO_MST_PAD_CTRL0 0x01c
24 #define AUDIO_MST_PAD_CTRL1 0x020
25 #define AUDIO_SW_RESET 0x024
[all …]
/kernel/linux/patches/linux-5.10/prebuilts/usr/include/linux/
Dvirtio_mmio.h21 #define VIRTIO_MMIO_MAGIC_VALUE 0x000
22 #define VIRTIO_MMIO_VERSION 0x004
23 #define VIRTIO_MMIO_DEVICE_ID 0x008
24 #define VIRTIO_MMIO_VENDOR_ID 0x00c
25 #define VIRTIO_MMIO_DEVICE_FEATURES 0x010
26 #define VIRTIO_MMIO_DEVICE_FEATURES_SEL 0x014
27 #define VIRTIO_MMIO_DRIVER_FEATURES 0x020
28 #define VIRTIO_MMIO_DRIVER_FEATURES_SEL 0x024
30 #define VIRTIO_MMIO_GUEST_PAGE_SIZE 0x028
32 #define VIRTIO_MMIO_QUEUE_SEL 0x030
[all …]

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