Home
last modified time | relevance | path

Searched +full:0 +full:x0d000000 (Results 1 – 25 of 53) sorted by relevance

123

/kernel/linux/linux-5.10/arch/arm/mach-pxa/
Dmp900.c33 __asm__ volatile ("0:\n" in isp116x_pfm_delay()
34 "subs %0, %1, #1\n" in isp116x_pfm_delay()
35 "bge 0b\n" in isp116x_pfm_delay()
37 :"0"(cyc) in isp116x_pfm_delay()
47 [0] = {
48 .start = 0x0d000000,
49 .end = 0x0d000000 + 1,
53 .start = 0x0d000000 + 4,
54 .end = 0x0d000000 + 5,
92 .atag_offset = 0x220100,
/kernel/linux/linux-4.19/arch/arm/mach-pxa/
Dmp900.c36 __asm__ volatile ("0:\n" in isp116x_pfm_delay()
37 "subs %0, %1, #1\n" in isp116x_pfm_delay()
38 "bge 0b\n" in isp116x_pfm_delay()
40 :"0"(cyc) in isp116x_pfm_delay()
50 [0] = {
51 .start = 0x0d000000,
52 .end = 0x0d000000 + 1,
56 .start = 0x0d000000 + 4,
57 .end = 0x0d000000 + 5,
95 .atag_offset = 0x220100,
/kernel/linux/linux-4.19/arch/powerpc/boot/dts/
Dwii.dts24 /*/memreserve/ 0x10000000 0x0004000;*/ /* DSP RAM */
38 reg = <0x00000000 0x01800000 /* MEM1 24MB 1T-SRAM */
39 0x10000000 0x04000000>; /* MEM2 64MB GDDR3 */
44 #size-cells = <0>;
46 PowerPC,broadway@0 {
48 reg = <0>;
64 ranges = <0x0c000000 0x0c000000 0x01000000
65 0x0d000000 0x0d000000 0x00800000
66 0x0d800000 0x0d800000 0x00800000>;
72 reg = <0x0c002000 0x100>;
[all …]
/kernel/linux/linux-5.10/arch/powerpc/boot/dts/
Dwii.dts20 /*/memreserve/ 0x10000000 0x0004000;*/ /* DSP RAM */
34 reg = <0x00000000 0x01800000 /* MEM1 24MB 1T-SRAM */
35 0x10000000 0x04000000>; /* MEM2 64MB GDDR3 */
40 #size-cells = <0>;
42 PowerPC,broadway@0 {
44 reg = <0>;
60 ranges = <0x0c000000 0x0c000000 0x01000000
61 0x0d000000 0x0d000000 0x00800000
62 0x0d800000 0x0d800000 0x00800000>;
68 reg = <0x0c002000 0x100>;
[all …]
/kernel/linux/linux-5.10/arch/sh/configs/
Dhp6xx_defconfig9 CONFIG_MEMORY_START=0x0d000000
10 CONFIG_MEMORY_SIZE=0x00400000
/kernel/linux/linux-4.19/arch/sh/configs/
Dhp6xx_defconfig10 CONFIG_MEMORY_START=0x0d000000
11 CONFIG_MEMORY_SIZE=0x00400000
/kernel/linux/linux-4.19/arch/xtensa/boot/dts/
Dcsp.dts11 …bootargs = "earlycon=cdns,0xfd000000,115200 console=tty0 console=ttyPS0,115200 root=/dev/ram0 rw e…
14 memory@0 {
16 reg = <0x00000000 0x40000000>;
21 #size-cells = <0>;
22 cpu@0 {
24 reg = <0>;
36 #clock-cells = <0>;
45 ranges = <0x00000000 0xf0000000 0x10000000>;
47 uart0: serial@0d000000 {
51 reg = <0x0d000000 0x1000>;
[all …]
/kernel/linux/linux-5.10/arch/xtensa/boot/dts/
Dcsp.dts11 …bootargs = "earlycon=cdns,0xfd000000,115200 console=tty0 console=ttyPS0,115200 root=/dev/ram0 rw e…
14 memory@0 {
16 reg = <0x00000000 0x40000000>;
21 #size-cells = <0>;
22 cpu@0 {
24 reg = <0>;
36 #clock-cells = <0>;
45 ranges = <0x00000000 0xf0000000 0x10000000>;
47 uart0: serial@0d000000 {
51 reg = <0x0d000000 0x1000>;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/ti/
Dk3-j721e.dtsi40 #size-cells = <0>;
54 cpu0: cpu@0 {
56 reg = <0x000>;
59 i-cache-size = <0xC000>;
62 d-cache-size = <0x8000>;
70 reg = <0x001>;
73 i-cache-size = <0xC000>;
76 d-cache-size = <0x8000>;
86 cache-size = <0x100000>;
127 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
Dk3-j7200.dtsi39 #size-cells = <0>;
53 cpu0: cpu@0 {
55 reg = <0x000>;
58 i-cache-size = <0xc000>;
61 d-cache-size = <0x8000>;
69 reg = <0x001>;
72 i-cache-size = <0xc000>;
75 d-cache-size = <0x8000>;
85 cache-size = <0x100000>;
125 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/pci/
Ddesignware-pcie.txt39 0x00-0xff is assumed if not present)
48 reg = <0xdfc00000 0x0001000>, /* IP registers */
49 <0xd0000000 0x0002000>; /* Configuration space */
54 ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000
55 0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>;
63 reg = <0xdfc00000 0x0001000>, /* IP registers 1 */
64 <0xdfc01000 0x0001000>, /* IP registers 2 */
65 <0xd0000000 0x2000000>; /* Configuration space */
Dnvidia,tegra20-pcie.txt27 - cell 0 specifies the bus and device numbers of the root port:
30 - cell 1 denotes the upper 32 address bits and should be 0
45 - 0x81000000: I/O memory region
46 - 0x82000000: non-prefetchable memory region
47 - 0xc2000000: prefetchable memory region
96 - If lanes 0 to 3 are used:
154 - Root port 0 uses 4 lanes, root port 1 is unused.
162 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
175 reg = <0x80003000 0x00000800 /* PADS registers */
176 0x80003800 0x00000200 /* AFI registers */
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/
Dti,j721e-pci-ep.yaml78 reg = <0x00 0x02900000 0x00 0x1000>,
79 <0x00 0x02907000 0x00 0x400>,
80 <0x00 0x0d000000 0x00 0x00800000>,
81 <0x00 0x10000000 0x00 0x08000000>;
Dti,j721e-pci-host.yaml48 const: 0x104c
51 const: 0xb00d
88 reg = <0x00 0x02900000 0x00 0x1000>,
89 <0x00 0x02907000 0x00 0x400>,
90 <0x00 0x0d000000 0x00 0x00800000>,
91 <0x00 0x10000000 0x00 0x00001000>;
102 bus-range = <0x0 0xf>;
103 vendor-id = <0x104c>;
104 device-id = <0xb00d>;
105 msi-map = <0x0 &gic_its 0x0 0x10000>;
[all …]
Ddesignware-pcie.txt46 0x00-0xff is assumed if not present)
55 reg = <0xdfc00000 0x0001000>, /* IP registers */
56 <0xd0000000 0x0002000>; /* Configuration space */
61 ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000
62 0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>;
70 reg = <0xdfc00000 0x0001000>, /* IP registers 1 */
71 <0xdfc01000 0x0001000>, /* IP registers 2 */
72 <0xd0000000 0x2000000>; /* Configuration space */
Dnvidia,tegra20-pcie.txt27 - cell 0 specifies the bus and device numbers of the root port:
30 - cell 1 denotes the upper 32 address bits and should be 0
45 - 0x81000000: I/O memory region
46 - 0x82000000: non-prefetchable memory region
47 - 0xc2000000: prefetchable memory region
73 - pinctrl-0: phandle for the default/active state of pin configurations.
104 - If lanes 0 to 3 are used:
150 - Root port 0 uses 4 lanes, root port 1 is unused.
158 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
171 reg = <0x80003000 0x00000800 /* PADS registers */
[all …]
/kernel/linux/linux-5.10/arch/arm/nwfpe/
Dentry.S50 EmulateAll returns 1 if the emulation was successful, or 0 if not.
83 cmp r0, #0 @ was emulation successful
91 and r2, r6, #0x0F000000 @ test for FP insns
92 teq r2, #0x0C000000
93 teqne r2, #0x0D000000
94 teqne r2, #0x0E000000
/kernel/linux/linux-4.19/arch/arm/nwfpe/
Dentry.S61 EmulateAll returns 1 if the emulation was successful, or 0 if not.
94 cmp r0, #0 @ was emulation successful
102 and r2, r6, #0x0F000000 @ test for FP insns
103 teq r2, #0x0C000000
104 teqne r2, #0x0D000000
105 teqne r2, #0x0E000000
/kernel/linux/linux-5.10/arch/powerpc/platforms/embedded6xx/
Dusbgecko_udbg.c22 #define EXI_CSR 0x00
23 #define EXI_CSR_CLKMASK (0x7<<4)
25 #define EXI_CSR_CSMASK (0x7<<7)
26 #define EXI_CSR_CS_0 (0x1<<7) /* Chip Select 001 */
28 #define EXI_CR 0x0c
29 #define EXI_CR_TSTART (1<<0)
34 #define EXI_DATA 0x10
66 out_be32(csr_reg, 0); in ug_io_transaction()
80 return 0; in ug_is_adapter_present()
82 return ug_io_transaction(0x90000000) == 0x04700000; in ug_is_adapter_present()
[all …]
/kernel/linux/linux-4.19/drivers/crypto/chelsio/
Dchcr_crypto.h62 #define CHCR_ENCRYPT_OP 0
71 #define CHCR_SCMD_AUTH_CTRL_AUTH_CIPHER 0
74 #define CHCR_SCMD_CIPHER_MODE_NOP 0
82 #define CHCR_SCMD_AUTH_MODE_NOP 0
94 #define CHCR_SCMD_HMAC_CTRL_NOP 0
102 #define VERIFY_HW 0
105 #define CHCR_SCMD_IVGEN_CTRL_HW 0
110 #define CHCR_KEYCTX_MAC_KEY_SIZE_128 0
115 #define CHCR_KEYCTX_CIPHER_KEY_SIZE_128 0
127 #define IV_NOP 0
[all …]
/kernel/linux/linux-4.19/arch/powerpc/platforms/embedded6xx/
Dusbgecko_udbg.c27 #define EXI_CSR 0x00
28 #define EXI_CSR_CLKMASK (0x7<<4)
30 #define EXI_CSR_CSMASK (0x7<<7)
31 #define EXI_CSR_CS_0 (0x1<<7) /* Chip Select 001 */
33 #define EXI_CR 0x0c
34 #define EXI_CR_TSTART (1<<0)
39 #define EXI_DATA 0x10
71 out_be32(csr_reg, 0); in ug_io_transaction()
85 return 0; in ug_is_adapter_present()
87 return ug_io_transaction(0x90000000) == 0x04700000; in ug_is_adapter_present()
[all …]
/kernel/linux/linux-5.10/drivers/crypto/chelsio/
Dchcr_crypto.h63 #define CHCR_ENCRYPT_OP 0
72 #define CHCR_SCMD_AUTH_CTRL_AUTH_CIPHER 0
75 #define CHCR_SCMD_CIPHER_MODE_NOP 0
83 #define CHCR_SCMD_AUTH_MODE_NOP 0
95 #define CHCR_SCMD_HMAC_CTRL_NOP 0
103 #define VERIFY_HW 0
106 #define CHCR_SCMD_IVGEN_CTRL_HW 0
111 #define CHCR_KEYCTX_MAC_KEY_SIZE_128 0
116 #define CHCR_KEYCTX_CIPHER_KEY_SIZE_128 0
128 #define IV_NOP 0
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/etnaviv/
Dstate_hi.xml.h7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
48 #define MMU_EXCEPTION_SLAVE_NOT_PRESENT 0x00000001
49 #define MMU_EXCEPTION_PAGE_NOT_PRESENT 0x00000002
50 #define MMU_EXCEPTION_WRITE_VIOLATION 0x00000003
51 #define VIVS_HI 0x00000000
53 #define VIVS_HI_CLOCK_CONTROL 0x00000000
54 #define VIVS_HI_CLOCK_CONTROL_CLK3D_DIS 0x00000001
55 #define VIVS_HI_CLOCK_CONTROL_CLK2D_DIS 0x00000002
56 #define VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK 0x000001fc
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/etnaviv/
Dstate_hi.xml.h7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
48 #define MMU_EXCEPTION_SLAVE_NOT_PRESENT 0x00000001
49 #define MMU_EXCEPTION_PAGE_NOT_PRESENT 0x00000002
50 #define MMU_EXCEPTION_WRITE_VIOLATION 0x00000003
51 #define MMU_EXCEPTION_OUT_OF_BOUND 0x00000004
52 #define MMU_EXCEPTION_READ_SECURITY_VIOLATION 0x00000005
53 #define MMU_EXCEPTION_WRITE_SECURITY_VIOLATION 0x00000006
54 #define VIVS_HI 0x00000000
56 #define VIVS_HI_CLOCK_CONTROL 0x00000000
[all …]
/kernel/linux/linux-5.10/arch/mips/alchemy/devboards/
Ddb1000.c50 return 0; in db1000_board_setup()
57 if ((slot < 12) || (slot > 13) || pin == 0) in db1500_map_pci_irq()
60 return (pin == 1) ? AU1500_PCI_INTA : 0xff; in db1500_map_pci_irq()
75 [0] = {
77 .end = AU1500_PCI_PHYS_ADDR + 0xfff,
89 .id = 0,
100 [0] = {
102 .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1,
114 .id = 0,
124 [0] = {
[all …]

123