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/kernel/linux/linux-4.19/sound/soc/sh/rcar/
Dgen.c52 RSND_REG_SET(RSND_REG_##id, offset, 0, #id)
68 return 0; in rsnd_is_accessible_reg()
82 return 0; in rsnd_read()
155 memset(&regc, 0, sizeof(regc)); in _rsnd_gen_regmap_init()
180 for (i = 0; i < conf_size; i++) { in _rsnd_gen_regmap_init()
184 regf.lsb = 0; in _rsnd_gen_regmap_init()
197 return 0; in _rsnd_gen_regmap_init()
206 RSND_GEN_S_REG(SSI_MODE0, 0x800), in rsnd_gen2_probe()
207 RSND_GEN_S_REG(SSI_MODE1, 0x804), in rsnd_gen2_probe()
208 RSND_GEN_S_REG(SSI_MODE2, 0x808), in rsnd_gen2_probe()
[all …]
/kernel/linux/linux-5.10/sound/soc/sh/rcar/
Dgen.c52 RSND_REG_SET(id, offset, 0, #id)
68 return 0; in rsnd_is_accessible_reg()
90 return 0; in rsnd_mod_read()
164 memset(&regc, 0, sizeof(regc)); in _rsnd_gen_regmap_init()
189 for (i = 0; i < conf_size; i++) { in _rsnd_gen_regmap_init()
193 regf.lsb = 0; in _rsnd_gen_regmap_init()
206 return 0; in _rsnd_gen_regmap_init()
215 RSND_GEN_S_REG(SSI_MODE0, 0x800), in rsnd_gen2_probe()
216 RSND_GEN_S_REG(SSI_MODE1, 0x804), in rsnd_gen2_probe()
217 RSND_GEN_S_REG(SSI_MODE2, 0x808), in rsnd_gen2_probe()
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/radeon/
Drv770.c49 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in rv770_set_uvd_clocks()
64 return 0; in rv770_set_uvd_clocks()
68 43663, 0x03FFFFFE, 1, 30, ~0, in rv770_set_uvd_clocks()
77 /* set UPLL_FB_DIV to 0x50000 */ in rv770_set_uvd_clocks()
78 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(0x50000), ~UPLL_FB_DIV_MASK); in rv770_set_uvd_clocks()
81 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~(UPLL_RESET_MASK | UPLL_SLEEP_MASK)); in rv770_set_uvd_clocks()
83 /* assert BYPASS EN and FB_DIV[0] <- ??? why? */ in rv770_set_uvd_clocks()
110 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in rv770_set_uvd_clocks()
114 /* deassert BYPASS EN and FB_DIV[0] <- ??? why? */ in rv770_set_uvd_clocks()
115 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); in rv770_set_uvd_clocks()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
Drv770.c53 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in rv770_set_uvd_clocks()
68 return 0; in rv770_set_uvd_clocks()
72 43663, 0x03FFFFFE, 1, 30, ~0, in rv770_set_uvd_clocks()
81 /* set UPLL_FB_DIV to 0x50000 */ in rv770_set_uvd_clocks()
82 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(0x50000), ~UPLL_FB_DIV_MASK); in rv770_set_uvd_clocks()
85 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~(UPLL_RESET_MASK | UPLL_SLEEP_MASK)); in rv770_set_uvd_clocks()
87 /* assert BYPASS EN and FB_DIV[0] <- ??? why? */ in rv770_set_uvd_clocks()
114 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in rv770_set_uvd_clocks()
118 /* deassert BYPASS EN and FB_DIV[0] <- ??? why? */ in rv770_set_uvd_clocks()
119 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); in rv770_set_uvd_clocks()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/adreno/
Da6xx_gpu_state.h13 0x8000, 0x8006, 0x8010, 0x8092, 0x8094, 0x809d, 0x80a0, 0x80a6,
14 0x80af, 0x80f1, 0x8100, 0x8107, 0x8109, 0x8109, 0x8110, 0x8110,
15 0x8400, 0x840b,
19 0x8800, 0x8806, 0x8809, 0x8811, 0x8818, 0x881e, 0x8820, 0x8865,
20 0x8870, 0x8879, 0x8880, 0x8889, 0x8890, 0x8891, 0x8898, 0x8898,
21 0x88c0, 0x88c1, 0x88d0, 0x88e3, 0x8900, 0x890c, 0x890f, 0x891a,
22 0x8c00, 0x8c01, 0x8c08, 0x8c10, 0x8c17, 0x8c1f, 0x8c26, 0x8c33,
26 0x88f0, 0x88f3, 0x890d, 0x890e, 0x8927, 0x8928, 0x8bf0, 0x8bf1,
27 0x8c02, 0x8c07, 0x8c11, 0x8c16, 0x8c20, 0x8c25,
31 0x9200, 0x9216, 0x9218, 0x9236, 0x9300, 0x9306,
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/net/
Dmscc-ocelot.txt18 - "portX" with X from 0 to the number of last port index available on that
30 - #size-cells: Must be 0
45 reg = <0x1010000 0x10000>,
46 <0x1030000 0x10000>,
47 <0x1080000 0x100>,
48 <0x10d0000 0x10000>,
49 <0x11e0000 0x100>,
50 <0x11f0000 0x100>,
51 <0x1200000 0x100>,
52 <0x1210000 0x100>,
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dmscc-ocelot.txt18 - "portX" with X from 0 to the number of last port index available on that
31 - #size-cells: Must be 0
46 reg = <0x1010000 0x10000>,
47 <0x1030000 0x10000>,
48 <0x1080000 0x100>,
49 <0x10e0000 0x10000>,
50 <0x11e0000 0x100>,
51 <0x11f0000 0x100>,
52 <0x1200000 0x100>,
53 <0x1210000 0x100>,
[all …]
/kernel/linux/linux-4.19/drivers/net/ethernet/intel/igbvf/
Dregs.h7 #define E1000_CTRL 0x00000 /* Device Control - RW */
8 #define E1000_STATUS 0x00008 /* Device Status - RO */
9 #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
10 #define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */
11 #define E1000_EITR(_n) (0x01680 + (0x4 * (_n)))
12 #define E1000_EICS 0x01520 /* Ext. Interrupt Cause Set - W0 */
13 #define E1000_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */
14 #define E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */
15 #define E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */
16 #define E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/intel/igbvf/
Dregs.h7 #define E1000_CTRL 0x00000 /* Device Control - RW */
8 #define E1000_STATUS 0x00008 /* Device Status - RO */
9 #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
10 #define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */
11 #define E1000_EITR(_n) (0x01680 + (0x4 * (_n)))
12 #define E1000_EICS 0x01520 /* Ext. Interrupt Cause Set - W0 */
13 #define E1000_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */
14 #define E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */
15 #define E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */
16 #define E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */
[all …]
/kernel/linux/linux-4.19/arch/mips/boot/dts/mscc/
Docelot.dtsi11 #size-cells = <0>;
13 cpu@0 {
17 reg = <0>;
26 #address-cells = <0>;
34 #clock-cells = <0>;
40 #clock-cells = <0>;
50 ranges = <0 0x70000000 0x2000000>;
54 cpu_ctrl: syscon@0 {
56 reg = <0x0 0x2c>;
61 reg = <0x70 0x70>;
[all …]
/kernel/linux/linux-5.10/drivers/memory/tegra/
Dtegra20.c12 .id = 0x00,
15 .id = 0x01,
18 .id = 0x02,
21 .id = 0x03,
24 .id = 0x04,
27 .id = 0x05,
30 .id = 0x06,
33 .id = 0x07,
36 .id = 0x08,
39 .id = 0x09,
[all …]
/kernel/linux/linux-4.19/drivers/memory/tegra/
Dtegra20.c15 .id = 0x00,
18 .id = 0x01,
21 .id = 0x02,
24 .id = 0x03,
27 .id = 0x04,
30 .id = 0x05,
33 .id = 0x06,
36 .id = 0x07,
39 .id = 0x08,
42 .id = 0x09,
[all …]
/kernel/linux/linux-5.10/arch/powerpc/boot/dts/
Dmpc5121.dtsi26 #size-cells = <0>;
28 PowerPC,5121@0 {
30 reg = <0>;
31 d-cache-line-size = <0x20>; /* 32 bytes */
32 i-cache-line-size = <0x20>; /* 32 bytes */
33 d-cache-size = <0x8000>; /* L1, 32K */
34 i-cache-size = <0x8000>; /* L1, 32K */
43 reg = <0x00000000 0x10000000>; /* 256MB at 0 */
48 reg = <0x20000000 0x4000>;
49 interrupts = <66 0x8>;
[all …]
/kernel/linux/linux-4.19/arch/powerpc/boot/dts/
Dmpc5121.dtsi30 #size-cells = <0>;
32 PowerPC,5121@0 {
34 reg = <0>;
35 d-cache-line-size = <0x20>; /* 32 bytes */
36 i-cache-line-size = <0x20>; /* 32 bytes */
37 d-cache-size = <0x8000>; /* L1, 32K */
38 i-cache-size = <0x8000>; /* L1, 32K */
47 reg = <0x00000000 0x10000000>; /* 256MB at 0 */
52 reg = <0x20000000 0x4000>;
53 interrupts = <66 0x8>;
[all …]
/kernel/linux/linux-5.10/arch/mips/boot/dts/mscc/
Docelot.dtsi11 #size-cells = <0>;
13 cpu@0 {
17 reg = <0>;
26 #address-cells = <0>;
34 #clock-cells = <0>;
40 #clock-cells = <0>;
50 ranges = <0 0x70000000 0x2000000>;
54 cpu_ctrl: syscon@0 {
56 reg = <0x0 0x2c>;
61 reg = <0x70 0x70>;
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dexynos5.dtsi40 reg = <0x10000000 0x100>;
45 reg = <0x12250000 0x14>;
53 reg = <0x10440000 0x1000>;
54 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
92 reg = <0x10481000 0x1000>,
93 <0x10482000 0x2000>,
94 <0x10484000 0x2000>,
95 <0x10486000 0x2000>;
102 reg = <0x10050000 0x5000>;
107 reg = <0x12C00000 0x100>;
[all …]
Dtango4-common.dtsi9 #define CPU_CLK 0
24 #clock-cells = <0>;
29 ranges = <0x00000000 0x20000000 0x2000>;
33 scu@0 {
35 reg = <0x0 0x100>;
40 reg = <0x600 0x10>;
50 reg = <0x1000 0x1000>, <0x100 0x100>;
56 reg = <0x20100000 0x1000>;
71 #clock-cells = <0>;
76 reg = <0x10000 0x100>;
[all …]
/kernel/linux/linux-4.19/arch/arm/boot/dts/
Dexynos5.dtsi40 reg = <0x10000000 0x100>;
45 reg = <0x12250000 0x14>;
53 reg = <0x10440000 0x1000>;
54 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
92 reg = <0x10481000 0x1000>,
93 <0x10482000 0x2000>,
94 <0x10484000 0x2000>,
95 <0x10486000 0x2000>;
102 reg = <0x10050000 0x5000>;
107 reg = <0x12C00000 0x100>;
[all …]
Dtango4-common.dtsi9 #define CPU_CLK 0
24 #clock-cells = <0>;
29 ranges = <0x00000000 0x20000000 0x2000>;
33 scu@0 {
35 reg = <0x0 0x100>;
40 reg = <0x600 0x10>;
50 reg = <0x1000 0x1000>, <0x100 0x100>;
56 reg = <0x20100000 0x1000>;
71 #clock-cells = <0>;
76 reg = <0x10000 0x100>;
[all …]
/kernel/linux/linux-4.19/arch/powerpc/kernel/
Dexceptions-64s.S26 * - Virtual mode exceptions must be mapped at their 0xc000... location.
30 * - LOAD_HANDLER targets must be within first 64K of physical 0 /
31 * virtual 0xc00...
41 * are offset by 0xc000000000000000 and also tend to get an added 0x4000
47 * It's impossible to receive interrupts below 0x300 via AIL.
50 * escalated to HV=1 from HV=0 is delivered via real mode handlers.
54 * 0x0000 - 0x00ff : Secondary processor spin code
55 * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors
56 * 0x1900 - 0x3fff : Real mode trampolines
57 * 0x4000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors
[all …]
/kernel/linux/linux-4.19/arch/mips/include/asm/mach-ralink/
Drt3883.h16 #define RT3883_SDRAM_BASE 0x00000000
17 #define RT3883_SYSC_BASE 0x10000000
18 #define RT3883_TIMER_BASE 0x10000100
19 #define RT3883_INTC_BASE 0x10000200
20 #define RT3883_MEMC_BASE 0x10000300
21 #define RT3883_UART0_BASE 0x10000500
22 #define RT3883_PIO_BASE 0x10000600
23 #define RT3883_FSCC_BASE 0x10000700
24 #define RT3883_NANDC_BASE 0x10000810
25 #define RT3883_I2C_BASE 0x10000900
[all …]
/kernel/linux/linux-5.10/arch/mips/include/asm/mach-ralink/
Drt3883.h13 #define RT3883_SDRAM_BASE 0x00000000
14 #define RT3883_SYSC_BASE 0x10000000
15 #define RT3883_TIMER_BASE 0x10000100
16 #define RT3883_INTC_BASE 0x10000200
17 #define RT3883_MEMC_BASE 0x10000300
18 #define RT3883_UART0_BASE 0x10000500
19 #define RT3883_PIO_BASE 0x10000600
20 #define RT3883_FSCC_BASE 0x10000700
21 #define RT3883_NANDC_BASE 0x10000810
22 #define RT3883_I2C_BASE 0x10000900
[all …]
/kernel/linux/linux-5.10/sound/soc/codecs/
Dwm8770.c37 { 0, 0x7f },
38 { 1, 0x7f },
39 { 2, 0x7f },
40 { 3, 0x7f },
41 { 4, 0x7f },
42 { 5, 0x7f },
43 { 6, 0x7f },
44 { 7, 0x7f },
45 { 8, 0x7f },
46 { 9, 0xff },
[all …]
/kernel/linux/linux-5.10/sound/pci/oxygen/
Dwm8776.h14 #define WM8776_HPLVOL 0x00
15 #define WM8776_HPRVOL 0x01
16 #define WM8776_HPMASTER 0x02
17 #define WM8776_DACLVOL 0x03
18 #define WM8776_DACRVOL 0x04
19 #define WM8776_DACMASTER 0x05
20 #define WM8776_PHASESWAP 0x06
21 #define WM8776_DACCTRL1 0x07
22 #define WM8776_DACMUTE 0x08
23 #define WM8776_DACCTRL2 0x09
[all …]
/kernel/linux/linux-4.19/sound/pci/oxygen/
Dwm8776.h17 #define WM8776_HPLVOL 0x00
18 #define WM8776_HPRVOL 0x01
19 #define WM8776_HPMASTER 0x02
20 #define WM8776_DACLVOL 0x03
21 #define WM8776_DACRVOL 0x04
22 #define WM8776_DACMASTER 0x05
23 #define WM8776_PHASESWAP 0x06
24 #define WM8776_DACCTRL1 0x07
25 #define WM8776_DACMUTE 0x08
26 #define WM8776_DACCTRL2 0x09
[all …]

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