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/kernel/linux/linux-4.19/Documentation/devicetree/bindings/crypto/
Dhisilicon,hip07-sec.txt9 Region 0 has registers to control the backend processing engines.
16 Interrupt 0 is for the SEC unit error queue.
29 reg = <0x400 0xd0000000 0x0 0x10000
30 0x400 0xd2000000 0x0 0x10000
31 0x400 0xd2010000 0x0 0x10000
32 0x400 0xd2020000 0x0 0x10000
33 0x400 0xd2030000 0x0 0x10000
34 0x400 0xd2040000 0x0 0x10000
35 0x400 0xd2050000 0x0 0x10000
36 0x400 0xd2060000 0x0 0x10000
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/crypto/
Dhisilicon,hip07-sec.txt9 Region 0 has registers to control the backend processing engines.
16 Interrupt 0 is for the SEC unit error queue.
29 reg = <0x400 0xd0000000 0x0 0x10000
30 0x400 0xd2000000 0x0 0x10000
31 0x400 0xd2010000 0x0 0x10000
32 0x400 0xd2020000 0x0 0x10000
33 0x400 0xd2030000 0x0 0x10000
34 0x400 0xd2040000 0x0 0x10000
35 0x400 0xd2050000 0x0 0x10000
36 0x400 0xd2060000 0x0 0x10000
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/ti/
Dti,j721e-dss.yaml27 - description: common_s0 DSS Shared common 0
83 - description: common_s0 DSS Shared common 0
107 const: 0
109 port@0:
159 reg = <0x04a00000 0x10000>, /* common_m */
160 <0x04a10000 0x10000>, /* common_s0*/
161 <0x04b00000 0x10000>, /* common_s1*/
162 <0x04b10000 0x10000>, /* common_s2*/
163 <0x04a20000 0x10000>, /* vidl1 */
164 <0x04a30000 0x10000>, /* vidl2 */
[all …]
/kernel/linux/linux-4.19/arch/arm/boot/dts/
Dimx7s.dtsi53 #size-cells = <0>;
55 cpu0: cpu@0 {
58 reg = <0>;
67 #clock-cells = <0>;
74 #clock-cells = <0>;
83 #phy-cells = <0>;
90 #phy-cells = <0>;
109 #size-cells = <0>;
111 port@0 {
112 reg = <0>;
[all …]
Dls1021a.dtsi72 #size-cells = <0>;
77 reg = <0xf00>;
78 clocks = <&clockgen 1 0>;
85 reg = <0xf01>;
86 clocks = <&clockgen 1 0>;
93 #clock-cells = <0>;
116 offset = <0xb0>;
117 mask = <0x02>;
132 reg = <0x0 0x1401000 0x0 0x1000>,
133 <0x0 0x1402000 0x0 0x2000>,
[all …]
Dprima2.dtsi18 #size-cells = <0>;
20 cpu@0 {
23 reg = <0x0>;
29 timebase-frequency = <0>;
30 bus-frequency = <0>;
31 clock-frequency = <0>;
53 ranges = <0x40000000 0x40000000 0x80000000>;
57 reg = <0x80040000 0x1000>;
61 arm,filter-ranges = <0 0x40000000>;
68 reg = <0x80020000 0x1000>;
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dimx7s.dtsi54 #size-cells = <0>;
61 arm,psci-suspend-param = <0x0010000>;
69 cpu0: cpu@0 {
72 reg = <0>;
82 #clock-cells = <0>;
89 #clock-cells = <0>;
98 #phy-cells = <0>;
105 #phy-cells = <0>;
124 #size-cells = <0>;
126 port@0 {
[all …]
Dls1021a.dtsi74 #size-cells = <0>;
79 reg = <0xf00>;
80 clocks = <&clockgen 1 0>;
87 reg = <0xf01>;
88 clocks = <&clockgen 1 0>;
95 reg = <0x0 0x0 0x0 0x0>;
100 #clock-cells = <0>;
123 offset = <0xb0>;
124 mask = <0x02>;
137 reg = <0x0 0x1080000 0x0 0x1000>;
[all …]
Dprima2.dtsi16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0x0>;
27 timebase-frequency = <0>;
28 bus-frequency = <0>;
29 clock-frequency = <0>;
51 ranges = <0x40000000 0x40000000 0x80000000>;
55 reg = <0x80040000 0x1000>;
59 arm,filter-ranges = <0 0x40000000>;
66 reg = <0x80020000 0x1000>;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/
Dimx8mp.dtsi43 #size-cells = <0>;
45 A53_0: cpu@0 {
48 reg = <0x0>;
59 reg = <0x1>;
70 reg = <0x2>;
81 reg = <0x3>;
96 #clock-cells = <0>;
103 #clock-cells = <0>;
110 #clock-cells = <0>;
117 #clock-cells = <0>;
[all …]
Dimx8mn.dtsi44 #size-cells = <0>;
51 arm,psci-suspend-param = <0x0010033>;
59 A53_0: cpu@0 {
62 reg = <0x0>;
77 reg = <0x1>;
90 reg = <0x2>;
103 reg = <0x3>;
125 opp-supported-hw = <0xb00>, <0x7>;
133 opp-supported-hw = <0x300>, <0x7>;
141 opp-supported-hw = <0x100>, <0x3>;
[all …]
Dimx8mm.dtsi44 #size-cells = <0>;
51 arm,psci-suspend-param = <0x0010033>;
59 A53_0: cpu@0 {
62 reg = <0x0>;
77 reg = <0x1>;
90 reg = <0x2>;
103 reg = <0x3>;
125 opp-supported-hw = <0xe>, <0x7>;
133 opp-supported-hw = <0xc>, <0x7>;
141 opp-supported-hw = <0x8>, <0x3>;
[all …]
Dfsl-ls1012a.dtsi31 #size-cells = <0>;
33 cpu0: cpu@0 {
36 reg = <0x0>;
37 clocks = <&clockgen 1 0>;
53 arm,psci-suspend-param = <0x0>;
62 #clock-cells = <0>;
69 #clock-cells = <0>;
84 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
91 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
92 <0x0 0x1402000 0 0x2000>, /* GICC */
[all …]
Dimx8mq.dtsi46 #clock-cells = <0>;
53 #clock-cells = <0>;
60 #clock-cells = <0>;
67 #clock-cells = <0>;
74 #clock-cells = <0>;
81 #clock-cells = <0>;
88 #clock-cells = <0>;
95 #size-cells = <0>;
97 A53_0: cpu@0 {
100 reg = <0x0>;
[all …]
Dfsl-ls1028a.dtsi26 #size-cells = <0>;
28 cpu0: cpu@0 {
31 reg = <0x0>;
33 clocks = <&clockgen 1 0>;
42 reg = <0x1>;
44 clocks = <&clockgen 1 0>;
65 arm,psci-suspend-param = <0x0>;
74 #clock-cells = <0>;
81 #clock-cells = <0>;
88 reg = <0x0 0xf1f0000 0x0 0xffff>;
[all …]
Dfsl-ls1046a.dtsi36 #size-cells = <0>;
38 cpu0: cpu@0 {
41 reg = <0x0>;
42 clocks = <&clockgen 1 0>;
51 reg = <0x1>;
52 clocks = <&clockgen 1 0>;
61 reg = <0x2>;
62 clocks = <&clockgen 1 0>;
71 reg = <0x3>;
72 clocks = <&clockgen 1 0>;
[all …]
/kernel/linux/linux-4.19/drivers/mtd/chips/
Djedec_probe.c26 #define AM29DL800BB 0x22CB
27 #define AM29DL800BT 0x224A
29 #define AM29F800BB 0x2258
30 #define AM29F800BT 0x22D6
31 #define AM29LV400BB 0x22BA
32 #define AM29LV400BT 0x22B9
33 #define AM29LV800BB 0x225B
34 #define AM29LV800BT 0x22DA
35 #define AM29LV160DT 0x22C4
36 #define AM29LV160DB 0x2249
[all …]
/kernel/linux/linux-5.10/drivers/mtd/chips/
Djedec_probe.c26 #define AM29DL800BB 0x22CB
27 #define AM29DL800BT 0x224A
29 #define AM29F800BB 0x2258
30 #define AM29F800BT 0x22D6
31 #define AM29LV400BB 0x22BA
32 #define AM29LV400BT 0x22B9
33 #define AM29LV800BB 0x225B
34 #define AM29LV800BT 0x22DA
35 #define AM29LV160DT 0x22C4
36 #define AM29LV160DB 0x2249
[all …]
/kernel/linux/linux-4.19/arch/arm64/boot/dts/freescale/
Dfsl-ls1046a.dtsi34 #size-cells = <0>;
36 cpu0: cpu@0 {
39 reg = <0x0>;
40 clocks = <&clockgen 1 0>;
49 reg = <0x1>;
50 clocks = <&clockgen 1 0>;
59 reg = <0x2>;
60 clocks = <&clockgen 1 0>;
69 reg = <0x3>;
70 clocks = <&clockgen 1 0>;
[all …]
Dfsl-ls1012a.dtsi29 #size-cells = <0>;
31 cpu0: cpu@0 {
34 reg = <0x0>;
35 clocks = <&clockgen 1 0>;
51 arm,psci-suspend-param = <0x0>;
60 #clock-cells = <0>;
67 #clock-cells = <0>;
82 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
89 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
90 <0x0 0x1402000 0 0x2000>, /* GICC */
[all …]
Dfsl-ls1043a.dtsi32 #size-cells = <0>;
40 cpu0: cpu@0 {
43 reg = <0x0>;
44 clocks = <&clockgen 1 0>;
53 reg = <0x1>;
54 clocks = <&clockgen 1 0>;
63 reg = <0x2>;
64 clocks = <&clockgen 1 0>;
73 reg = <0x3>;
74 clocks = <&clockgen 1 0>;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/hisilicon/
Dhip07.dtsi23 #size-cells = <0>;
270 reg = <0x10000>;
273 numa-node-id = <0>;
279 reg = <0x10001>;
282 numa-node-id = <0>;
288 reg = <0x10002>;
291 numa-node-id = <0>;
297 reg = <0x10003>;
300 numa-node-id = <0>;
306 reg = <0x10100>;
[all …]
/kernel/linux/linux-4.19/arch/arm64/boot/dts/hisilicon/
Dhip07.dtsi27 #size-cells = <0>;
274 reg = <0x10000>;
277 numa-node-id = <0>;
283 reg = <0x10001>;
286 numa-node-id = <0>;
292 reg = <0x10002>;
295 numa-node-id = <0>;
301 reg = <0x10003>;
304 numa-node-id = <0>;
310 reg = <0x10100>;
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/sun4i/
Dsun8i_ui_scaler.h24 (0x20000 + 0x20000 * (vi_cnt) + 0x10000 * (ui_idx) + 0x0)
26 (0x20000 + 0x20000 * (vi_cnt) + 0x10000 * (ui_idx) + 0x40)
28 (0x20000 + 0x20000 * (vi_cnt) + 0x10000 * (ui_idx) + 0x80)
30 (0x20000 + 0x20000 * (vi_cnt) + 0x10000 * (ui_idx) + 0x88)
32 (0x20000 + 0x20000 * (vi_cnt) + 0x10000 * (ui_idx) + 0x8c)
34 (0x20000 + 0x20000 * (vi_cnt) + 0x10000 * (ui_idx) + 0x90)
36 (0x20000 + 0x20000 * (vi_cnt) + 0x10000 * (ui_idx) + 0x98)
38 (0x20000 + 0x20000 * (vi_cnt) + 0x10000 * (ui_idx) + 0x200 + \
39 0x4 * (index))
41 #define SUN8I_SCALER_GSU_CTRL_EN BIT(0)
/kernel/linux/linux-4.19/arch/arm64/boot/dts/nvidia/
Dtegra194.dtsi19 ranges = <0x0 0x0 0x0 0x40000000>;
24 reg = <0x2200000 0x10000>,
25 <0x2210000 0x10000>;
41 reg = <0x02490000 0x10000>;
55 snps,burst-map = <0x7>;
62 reg = <0x03100000 0x40>;
74 reg = <0x03110000 0x40>;
86 reg = <0x03130000 0x40>;
98 reg = <0x03140000 0x40>;
110 reg = <0x03150000 0x40>;
[all …]

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