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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/powerpc/fsl/
Dmpc512x_lpbfifo.txt16 reg = <0x10100 0x50>;
17 interrupts = <7 0x8>;
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/powerpc/fsl/
Dmpc512x_lpbfifo.txt16 reg = <0x10100 0x50>;
17 interrupts = <7 0x8>;
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/mips/cavium/
Dciu3.txt24 #address-cells = <0>;
26 reg = <0x10100 0x00000000 0x0 0xb0000000>;
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mips/cavium/
Dciu3.txt24 #address-cells = <0>;
26 reg = <0x10100 0x00000000 0x0 0xb0000000>;
/kernel/linux/linux-5.10/arch/m68k/include/asm/
Dapollohw.h52 #define IO_BASE 0x80000000
62 #define SAU7_SIO01_PHYSADDR 0x10400
63 #define SAU7_SIO23_PHYSADDR 0x10500
64 #define SAU7_RTC_PHYSADDR 0x10900
65 #define SAU7_PICA 0x11000
66 #define SAU7_PICB 0x11100
67 #define SAU7_CPUCTRL 0x10100
68 #define SAU7_TIMER 0x010800
70 #define SAU8_SIO01_PHYSADDR 0x8400
71 #define SAU8_RTC_PHYSADDR 0x8900
[all …]
/kernel/linux/linux-4.19/arch/m68k/include/asm/
Dapollohw.h52 #define IO_BASE 0x80000000
62 #define SAU7_SIO01_PHYSADDR 0x10400
63 #define SAU7_SIO23_PHYSADDR 0x10500
64 #define SAU7_RTC_PHYSADDR 0x10900
65 #define SAU7_PICA 0x11000
66 #define SAU7_PICB 0x11100
67 #define SAU7_CPUCTRL 0x10100
68 #define SAU7_TIMER 0x010800
70 #define SAU8_SIO01_PHYSADDR 0x8400
71 #define SAU8_RTC_PHYSADDR 0x8900
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/
Dcpus.txt22 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
23 the reg property contained in bits 7 down to 0
57 If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
64 Definition: must be set to 0
81 this property is required and must be set to 0.
84 required and matches the CPUID[11:0] register bits.
86 Bits [11:0] in the reg cell must be set to
87 bits [11:0] in CPU ID register.
89 All other bits in the reg cell must be set to 0.
92 required and matches the CPU MPIDR[23:0] register
[all …]
Dtopology.txt89 cluster/core/thread) (where N = {0, 1, ...} is the node number; nodes which
91 sequential N value, starting from 0).
170 #size-cells = <0>;
257 CPU0: cpu@0 {
260 reg = <0x0 0x0>;
262 cpu-release-addr = <0 0x20000000>;
268 reg = <0x0 0x1>;
270 cpu-release-addr = <0 0x20000000>;
276 reg = <0x0 0x100>;
278 cpu-release-addr = <0 0x20000000>;
[all …]
Didle-states.txt74 between 0 and infinite time, until a wake-up event occurs.
99 wakeup-delay = exit-latency + max(entry-latency - (now - entry-timestamp), 0)
139 0| 1 time(ms)
144 The graph curve with X-axis values = { x | 0 < x < 1ms } has a steep slope
352 #size-cells = <0>;
355 CPU0: cpu@0 {
358 reg = <0x0 0x0>;
367 reg = <0x0 0x1>;
376 reg = <0x0 0x100>;
385 reg = <0x0 0x101>;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/
Dcpus.yaml30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31 the reg property contained in bits 7 down to 0
49 this property is required and must be set to 0.
52 required and matches the CPUID[11:0] register bits.
54 Bits [11:0] in the reg cell must be set to
55 bits [11:0] in CPU ID register.
57 All other bits in the reg cell must be set to 0.
60 required and matches the CPU MPIDR[23:0] register
63 Bits [23:0] in the reg cell must be set to
64 bits [23:0] in MPIDR.
[all …]
Didle-states.yaml82 between 0 and infinite time, until a wake-up event occurs.
107 wakeup-delay = exit-latency + max(entry-latency - (now - entry-timestamp), 0)
147 0| 1 time(ms)
152 The graph curve with X-axis values = { x | 0 < x < 1ms } has a steep slope
332 #size-cells = <0>;
335 cpu@0 {
338 reg = <0x0 0x0>;
347 reg = <0x0 0x1>;
356 reg = <0x0 0x100>;
365 reg = <0x0 0x101>;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/cpu/
Dcpu-topology.txt87 (ie socket/cluster/core/thread) (where N = {0, 1, ...} is the node number; nodes
89 sequential N value, starting from 0).
187 #size-cells = <0>;
276 CPU0: cpu@0 {
279 reg = <0x0 0x0>;
281 cpu-release-addr = <0 0x20000000>;
287 reg = <0x0 0x1>;
289 cpu-release-addr = <0 0x20000000>;
295 reg = <0x0 0x100>;
297 cpu-release-addr = <0 0x20000000>;
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dorion5x.dtsi29 reg = <MBUS_ID(0xf0, 0x01) 0x1046C 0x4>;
30 ranges = <0 MBUS_ID(0x01, 0x0f) 0 0xffffffff>;
33 clocks = <&core_clk 0>;
39 reg = <MBUS_ID(0xf0, 0x01) 0x1045C 0x4>;
40 ranges = <0 MBUS_ID(0x01, 0x1e) 0 0xffffffff>;
43 clocks = <&core_clk 0>;
49 reg = <MBUS_ID(0xf0, 0x01) 0x10460 0x4>;
50 ranges = <0 MBUS_ID(0x01, 0x1d) 0 0xffffffff>;
53 clocks = <&core_clk 0>;
59 reg = <MBUS_ID(0xf0, 0x01) 0x10464 0x4>;
[all …]
Dkirkwood.dtsi15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0>;
37 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 /* internal-regs */
38 MBUS_ID(0x01, 0x2f) 0 0xf4000000 0x10000 /* nand flash */
39 MBUS_ID(0x03, 0x01) 0 0xf5000000 0x10000 /* crypto sram */
42 pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */
43 pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */
48 cle = <0>;
52 reg = <MBUS_ID(0x01, 0x2f) 0 0x400>;
[all …]
/kernel/linux/linux-4.19/arch/arm/boot/dts/
Dorion5x.dtsi29 reg = <MBUS_ID(0xf0, 0x01) 0x1046C 0x4>;
30 ranges = <0 MBUS_ID(0x01, 0x0f) 0 0xffffffff>;
33 clocks = <&core_clk 0>;
39 reg = <MBUS_ID(0xf0, 0x01) 0x1045C 0x4>;
40 ranges = <0 MBUS_ID(0x01, 0x1e) 0 0xffffffff>;
43 clocks = <&core_clk 0>;
49 reg = <MBUS_ID(0xf0, 0x01) 0x10460 0x4>;
50 ranges = <0 MBUS_ID(0x01, 0x1d) 0 0xffffffff>;
53 clocks = <&core_clk 0>;
59 reg = <MBUS_ID(0xf0, 0x01) 0x10464 0x4>;
[all …]
Dkirkwood.dtsi14 #size-cells = <0>;
16 cpu@0 {
19 reg = <0>;
36 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 /* internal-regs */
37 MBUS_ID(0x01, 0x2f) 0 0xf4000000 0x10000 /* nand flash */
38 MBUS_ID(0x03, 0x01) 0 0xf5000000 0x10000 /* crypto sram */
41 pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */
42 pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */
47 cle = <0>;
51 reg = <MBUS_ID(0x01, 0x2f) 0 0x400>;
[all …]
/kernel/linux/linux-4.19/drivers/crypto/mediatek/
Dmtk-regs.h17 #define CDR_BASE_ADDR_LO(x) (0x0 + ((x) << 12))
18 #define CDR_BASE_ADDR_HI(x) (0x4 + ((x) << 12))
19 #define CDR_DATA_BASE_ADDR_LO(x) (0x8 + ((x) << 12))
20 #define CDR_DATA_BASE_ADDR_HI(x) (0xC + ((x) << 12))
21 #define CDR_ACD_BASE_ADDR_LO(x) (0x10 + ((x) << 12))
22 #define CDR_ACD_BASE_ADDR_HI(x) (0x14 + ((x) << 12))
23 #define CDR_RING_SIZE(x) (0x18 + ((x) << 12))
24 #define CDR_DESC_SIZE(x) (0x1C + ((x) << 12))
25 #define CDR_CFG(x) (0x20 + ((x) << 12))
26 #define CDR_DMA_CFG(x) (0x24 + ((x) << 12))
[all …]
/kernel/linux/linux-5.10/drivers/crypto/mediatek/
Dmtk-regs.h13 #define CDR_BASE_ADDR_LO(x) (0x0 + ((x) << 12))
14 #define CDR_BASE_ADDR_HI(x) (0x4 + ((x) << 12))
15 #define CDR_DATA_BASE_ADDR_LO(x) (0x8 + ((x) << 12))
16 #define CDR_DATA_BASE_ADDR_HI(x) (0xC + ((x) << 12))
17 #define CDR_ACD_BASE_ADDR_LO(x) (0x10 + ((x) << 12))
18 #define CDR_ACD_BASE_ADDR_HI(x) (0x14 + ((x) << 12))
19 #define CDR_RING_SIZE(x) (0x18 + ((x) << 12))
20 #define CDR_DESC_SIZE(x) (0x1C + ((x) << 12))
21 #define CDR_CFG(x) (0x20 + ((x) << 12))
22 #define CDR_DMA_CFG(x) (0x24 + ((x) << 12))
[all …]
/kernel/linux/linux-5.10/arch/powerpc/boot/dts/
Dmpc5125twr.dts30 #size-cells = <0>;
32 PowerPC,5125@0 {
34 reg = <0>;
35 d-cache-line-size = <0x20>; // 32 bytes
36 i-cache-line-size = <0x20>; // 32 bytes
37 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <0x8000>; // L1, 32K
47 reg = <0x00000000 0x10000000>; // 256MB at 0
52 reg = <0x30000000 0x08000>; // 32K at 0x30000000
57 #size-cells = <0>;
[all …]
Dmpc5121.dtsi26 #size-cells = <0>;
28 PowerPC,5121@0 {
30 reg = <0>;
31 d-cache-line-size = <0x20>; /* 32 bytes */
32 i-cache-line-size = <0x20>; /* 32 bytes */
33 d-cache-size = <0x8000>; /* L1, 32K */
34 i-cache-size = <0x8000>; /* L1, 32K */
43 reg = <0x00000000 0x10000000>; /* 256MB at 0 */
48 reg = <0x20000000 0x4000>;
49 interrupts = <66 0x8>;
[all …]
/kernel/linux/linux-4.19/arch/powerpc/boot/dts/
Dmpc5125twr.dts34 #size-cells = <0>;
36 PowerPC,5125@0 {
38 reg = <0>;
39 d-cache-line-size = <0x20>; // 32 bytes
40 i-cache-line-size = <0x20>; // 32 bytes
41 d-cache-size = <0x8000>; // L1, 32K
42 i-cache-size = <0x8000>; // L1, 32K
51 reg = <0x00000000 0x10000000>; // 256MB at 0
56 reg = <0x30000000 0x08000>; // 32K at 0x30000000
61 #size-cells = <0>;
[all …]
Dmpc5121.dtsi30 #size-cells = <0>;
32 PowerPC,5121@0 {
34 reg = <0>;
35 d-cache-line-size = <0x20>; /* 32 bytes */
36 i-cache-line-size = <0x20>; /* 32 bytes */
37 d-cache-size = <0x8000>; /* L1, 32K */
38 i-cache-size = <0x8000>; /* L1, 32K */
47 reg = <0x00000000 0x10000000>; /* 256MB at 0 */
52 reg = <0x20000000 0x4000>;
53 interrupts = <66 0x8>;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/arm/
Dfvp-base-revc.dts15 /memreserve/ 0x80000000 0x00010000;
43 #size-cells = <0>;
45 cpu0: cpu@0 {
48 reg = <0x0 0x000>;
54 reg = <0x0 0x100>;
60 reg = <0x0 0x200>;
66 reg = <0x0 0x300>;
72 reg = <0x0 0x10000>;
78 reg = <0x0 0x10100>;
84 reg = <0x0 0x10200>;
[all …]
/kernel/linux/linux-5.10/drivers/rapidio/switches/
Didt_gen3.c18 #define RIO_EM_PW_STAT 0x40020
19 #define RIO_PW_CTL 0x40204
20 #define RIO_PW_CTL_PW_TMR 0xffffff00
21 #define RIO_PW_ROUTE 0x40208
23 #define RIO_EM_DEV_INT_EN 0x40030
25 #define RIO_PLM_SPx_IMP_SPEC_CTL(x) (0x10100 + (x)*0x100)
26 #define RIO_PLM_SPx_IMP_SPEC_CTL_SOFT_RST 0x02000000
28 #define RIO_PLM_SPx_PW_EN(x) (0x10118 + (x)*0x100)
29 #define RIO_PLM_SPx_PW_EN_OK2U 0x40000000
30 #define RIO_PLM_SPx_PW_EN_LINIT 0x10000000
[all …]
/kernel/linux/linux-4.19/drivers/rapidio/switches/
Didt_gen3.c22 #define RIO_EM_PW_STAT 0x40020
23 #define RIO_PW_CTL 0x40204
24 #define RIO_PW_CTL_PW_TMR 0xffffff00
25 #define RIO_PW_ROUTE 0x40208
27 #define RIO_EM_DEV_INT_EN 0x40030
29 #define RIO_PLM_SPx_IMP_SPEC_CTL(x) (0x10100 + (x)*0x100)
30 #define RIO_PLM_SPx_IMP_SPEC_CTL_SOFT_RST 0x02000000
32 #define RIO_PLM_SPx_PW_EN(x) (0x10118 + (x)*0x100)
33 #define RIO_PLM_SPx_PW_EN_OK2U 0x40000000
34 #define RIO_PLM_SPx_PW_EN_LINIT 0x10000000
[all …]

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