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/kernel/linux/linux-4.19/drivers/mfd/
Dwm8994-core.c39 .id = 0,
131 if (ret < 0) { in wm8994_suspend()
135 return 0; in wm8994_suspend()
162 if (ret != 0) in wm8994_suspend()
169 if (ret != 0) in wm8994_suspend()
177 if (ret != 0) { in wm8994_suspend()
182 return 0; in wm8994_suspend()
192 return 0; in wm8994_resume()
196 if (ret != 0) { in wm8994_resume()
203 if (ret != 0) { in wm8994_resume()
[all …]
/kernel/linux/linux-5.10/drivers/mfd/
Dwm8994-core.c33 .id = 0,
125 if (ret < 0) { in wm8994_suspend()
129 return 0; in wm8994_suspend()
156 if (ret != 0) in wm8994_suspend()
163 if (ret != 0) in wm8994_suspend()
171 if (ret != 0) { in wm8994_suspend()
176 return 0; in wm8994_suspend()
186 return 0; in wm8994_resume()
190 if (ret != 0) { in wm8994_resume()
197 if (ret != 0) { in wm8994_resume()
[all …]
/kernel/linux/linux-4.19/arch/arm/mach-tango/
Dsmc.h4 #define tango_set_l2_control(val) tango_smc(val, 0x102)
5 #define tango_start_aux_core(val) tango_smc(val, 0x104)
6 #define tango_set_aux_boot_addr(val) tango_smc(val, 0x105)
7 #define tango_suspend(val) tango_smc(val, 0x120)
8 #define tango_aux_core_die(val) tango_smc(val, 0x121)
9 #define tango_aux_core_kill(val) tango_smc(val, 0x122)
/kernel/linux/linux-5.10/arch/arm/mach-tango/
Dsmc.h4 #define tango_set_l2_control(val) tango_smc(val, 0x102)
5 #define tango_start_aux_core(val) tango_smc(val, 0x104)
6 #define tango_set_aux_boot_addr(val) tango_smc(val, 0x105)
7 #define tango_suspend(val) tango_smc(val, 0x120)
8 #define tango_aux_core_die(val) tango_smc(val, 0x121)
9 #define tango_aux_core_kill(val) tango_smc(val, 0x122)
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/selftests/
Di915_perf.c35 oa_config->id = idr_alloc(&perf->metrics_idr, oa_config, 2, 0, GFP_KERNEL); in alloc_empty_config()
36 if (oa_config->id < 0) { in alloc_empty_config()
44 return 0; in alloc_empty_config()
99 0), in test_stream()
152 return 0; in live_sanitycheck()
173 *cs++ = 0; in write_timestamp()
174 *cs++ = 0; in write_timestamp()
175 *cs++ = 0; in write_timestamp()
179 return 0; in write_timestamp()
215 for (i = 0; i < 4; i++) in live_noa_delay()
[all …]
/kernel/linux/linux-5.10/drivers/of/unittest-data/
Doverlay_bad_add_dup_node.dts19 power_bus = < 0x1 0x2 >;
26 power_bus_emergency = < 0x101 0x102 >;
/kernel/linux/linux-5.10/include/soc/arc/
Dtimers.h12 #define ARC_REG_TIMER0_LIMIT 0x23 /* timer 0 limit */
13 #define ARC_REG_TIMER0_CTRL 0x22 /* timer 0 control */
14 #define ARC_REG_TIMER0_CNT 0x21 /* timer 0 count */
15 #define ARC_REG_TIMER1_LIMIT 0x102 /* timer 1 limit */
16 #define ARC_REG_TIMER1_CTRL 0x101 /* timer 1 control */
17 #define ARC_REG_TIMER1_CNT 0x100 /* timer 1 count */
20 #define TIMER_CTRL_IE (1 << 0) /* Interrupt when Count reaches limit */
23 #define ARC_TIMERN_MAX 0xFFFFFFFF
25 #define ARC_REG_TIMERS_BCR 0x75
/kernel/linux/linux-5.10/arch/powerpc/include/asm/
Dps3gpu.h16 #define L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_SYNC 0x101
17 #define L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_FLIP 0x102
19 #define L1GPU_CONTEXT_ATTRIBUTE_FB_SETUP 0x600
20 #define L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT 0x601
21 #define L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT_SYNC 0x602
22 #define L1GPU_CONTEXT_ATTRIBUTE_FB_CLOSE 0x603
39 head, ddr_offset, 0, 0); in lv1_gpu_display_sync()
47 head, ddr_offset, 0, 0); in lv1_gpu_display_flip()
55 xdr_lpar, xdr_size, ioif_offset, 0); in lv1_gpu_fb_setup()
70 L1GPU_CONTEXT_ATTRIBUTE_FB_CLOSE, 0, in lv1_gpu_fb_close()
[all …]
/kernel/linux/linux-4.19/include/soc/arc/
Dtimers.h15 #define ARC_REG_TIMER0_LIMIT 0x23 /* timer 0 limit */
16 #define ARC_REG_TIMER0_CTRL 0x22 /* timer 0 control */
17 #define ARC_REG_TIMER0_CNT 0x21 /* timer 0 count */
18 #define ARC_REG_TIMER1_LIMIT 0x102 /* timer 1 limit */
19 #define ARC_REG_TIMER1_CTRL 0x101 /* timer 1 control */
20 #define ARC_REG_TIMER1_CNT 0x100 /* timer 1 count */
23 #define TIMER_CTRL_IE (1 << 0) /* Interrupt when Count reaches limit */
26 #define ARC_TIMERN_MAX 0xFFFFFFFF
28 #define ARC_REG_TIMERS_BCR 0x75
/kernel/linux/linux-4.19/arch/powerpc/include/asm/
Dps3gpu.h28 #define L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_SYNC 0x101
29 #define L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_FLIP 0x102
31 #define L1GPU_CONTEXT_ATTRIBUTE_FB_SETUP 0x600
32 #define L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT 0x601
33 #define L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT_SYNC 0x602
34 #define L1GPU_CONTEXT_ATTRIBUTE_FB_CLOSE 0x603
51 head, ddr_offset, 0, 0); in lv1_gpu_display_sync()
59 head, ddr_offset, 0, 0); in lv1_gpu_display_flip()
67 xdr_lpar, xdr_size, ioif_offset, 0); in lv1_gpu_fb_setup()
82 L1GPU_CONTEXT_ATTRIBUTE_FB_CLOSE, 0, in lv1_gpu_fb_close()
[all …]
/kernel/linux/linux-4.19/arch/arm/boot/dts/
Dusb_a9g20-dab-mmx.dtsi22 i2c-gpio@0 {
70 #size-cells = <0>;
75 linux,code = <0x100>;
81 linux,code = <0x101>;
87 linux,code = <0x102>;
93 linux,code = <0x103>;
Dat91-kizboxmini.dts22 reg = <0x20000000 0x8000000>;
38 timer@0 {
40 reg = <0>;
60 pinctrl-0 = <&pinctrl_pwm0_pwm0_1
84 pinctrl-0 = <&pinctrl_ebi_addr_nand
91 pinctrl-0 = <&pinctrl_nand_oe_we
97 reg = <0x3 0x0 0x800000>;
112 bootstrap@0 {
114 reg = <0x0 0x20000>;
119 reg = <0x20000 0x7fe0000>;
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dusb_a9g20-dab-mmx.dtsi21 i2c-gpio@0 {
69 #size-cells = <0>;
74 linux,code = <0x100>;
80 linux,code = <0x101>;
86 linux,code = <0x102>;
92 linux,code = <0x103>;
/kernel/linux/patches/linux-4.19/prebuilts/usr/include/sound/
Dtlv.h8 #define SNDRV_CTL_TLVT_CONTAINER 0
14 #define SNDRV_CTL_TLVT_CHMAP_FIXED 0x101
15 #define SNDRV_CTL_TLVT_CHMAP_VAR 0x102
16 #define SNDRV_CTL_TLVT_CHMAP_PAIRED 0x103
21 #define SNDRV_CTL_TLVO_TYPE 0
29 #define SNDRV_CTL_TLVD_DB_SCALE_MASK 0xffff
30 #define SNDRV_CTL_TLVD_DB_SCALE_MUTE 0x10000
35 ((mute) ? SNDRV_CTL_TLVD_DB_SCALE_MUTE : 0))
Dskl-tplg-interface.h9 #define SKL_CONTROL_TYPE_BYTE_TLV 0x100
10 #define SKL_CONTROL_TYPE_MIC_SELECT 0x102
16 SKL_EVENT_NONE = 0,
23 SKL_CH_CFG_MONO = 0,
39 SKL_MODULE_TYPE_MIXER = 0,
49 SKL_AFFINITY_CORE_0 = 0,
54 SKL_PIPE_CONN_TYPE_NONE = 0,
59 SKL_CONN_NONE = 0,
64 SKL_DEVICE_BT = 0x0,
65 SKL_DEVICE_DMIC = 0x1,
[all …]
/kernel/linux/linux-4.19/arch/arm64/boot/dts/broadcom/stingray/
Dstingray-pcie.dtsi8 reg = <0 0x60400000 0 0x1000>;
11 bus-range = <0x0 0x1>;
16 ranges = <0x83000000 0 0x10000000 0 0x10000000 0 0x20000000>;
20 msi-map = <0x100 &gic_its 0x2000 0x1>, /* PF0 */
21 <0x108 &gic_its 0x2040 0x8>, /* PF0-VF0-7 */
22 <0x101 &gic_its 0x2080 0x1>, /* PF1 */
23 <0x110 &gic_its 0x20c8 0x8>, /* PF1-VF8-15 */
24 <0x102 &gic_its 0x2100 0x1>, /* PF2 */
25 <0x118 &gic_its 0x2150 0x8>, /* PF2-VF16-23 */
26 <0x103 &gic_its 0x2180 0x1>, /* PF3 */
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/broadcom/stingray/
Dstingray-pcie.dtsi8 reg = <0 0x60400000 0 0x1000>;
11 bus-range = <0x0 0x1>;
16 ranges = <0x83000000 0 0x10000000 0 0x10000000 0 0x20000000>;
20 msi-map = <0x100 &gic_its 0x2000 0x1>, /* PF0 */
21 <0x108 &gic_its 0x2040 0x8>, /* PF0-VF0-7 */
22 <0x101 &gic_its 0x2080 0x1>, /* PF1 */
23 <0x110 &gic_its 0x20c8 0x8>, /* PF1-VF8-15 */
24 <0x102 &gic_its 0x2100 0x1>, /* PF2 */
25 <0x118 &gic_its 0x2150 0x8>, /* PF2-VF16-23 */
26 <0x103 &gic_its 0x2180 0x1>, /* PF3 */
[all …]
/kernel/linux/linux-4.19/arch/arm/mach-omap2/
Domap-secure.h17 #define API_HAL_RET_VALUE_NS2S_CONVERSION_ERROR 0xFFFFFFFE
18 #define API_HAL_RET_VALUE_SERVICE_UNKNWON 0xFFFFFFFF
21 #define API_HAL_RET_VALUE_OK 0x00
22 #define API_HAL_RET_VALUE_FAIL 0x01
25 #define FLAG_START_CRITICAL 0x4
26 #define FLAG_IRQFIQ_MASK 0x3
27 #define FLAG_IRQ_ENABLE 0x2
28 #define FLAG_FIQ_ENABLE 0x1
29 #define NO_FLAG 0x0
34 #define OMAP3_SAVE_SECURE_RAM_SZ 0x803F
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-omap2/
Domap-secure.h16 #define API_HAL_RET_VALUE_NS2S_CONVERSION_ERROR 0xFFFFFFFE
17 #define API_HAL_RET_VALUE_SERVICE_UNKNWON 0xFFFFFFFF
20 #define API_HAL_RET_VALUE_OK 0x00
21 #define API_HAL_RET_VALUE_FAIL 0x01
24 #define FLAG_START_CRITICAL 0x4
25 #define FLAG_IRQFIQ_MASK 0x3
26 #define FLAG_IRQ_ENABLE 0x2
27 #define FLAG_FIQ_ENABLE 0x1
28 #define NO_FLAG 0x0
33 #define OMAP3_SAVE_SECURE_RAM_SZ 0x803F
[all …]
/kernel/linux/linux-4.19/arch/arm64/boot/dts/amlogic/
Dmeson-gxm.dtsi48 reg = <0x0 0x100>;
57 reg = <0x0 0x101>;
66 reg = <0x0 0x102>;
75 reg = <0x0 0x103>;
86 #phy-cells = <0>;
87 reg = <0x0 0x78040 0x0 0x20>;
105 clock-indices = <0 1>;
/kernel/linux/linux-5.10/drivers/media/i2c/
Dwm8775.c40 #define ALC_HOLD 0x85 /* R17: use zero cross detection, ALC hold time 42.6 ms */
41 #define ALC_EN 0x100 /* R17: ALC enable */
50 u8 input; /* Last selected input (0-0xf) */
68 if (reg < 0 || reg >= TOT_REGS) { in wm8775_write()
73 for (i = 0; i < 3; i++) in wm8775_write()
75 (reg << 1) | (val >> 8), val & 0xff) == 0) in wm8775_write()
76 return 0; in wm8775_write()
85 int muted = 0 != state->mute->val; in wm8775_set_audio()
89 /* normalize ( 65535 to 0 -> 255 to 0 (+24dB to -103dB) ) */ in wm8775_set_audio()
95 wm8775_write(sd, R21, 0x0c0 | state->input); in wm8775_set_audio()
[all …]
/kernel/linux/linux-5.10/drivers/usb/renesas_usbhs/
Drcar3.c13 #define LPSTS 0x102
14 #define UGCTRL 0x180 /* 32-bit register */
15 #define UGCTRL2 0x184 /* 32-bit register */
16 #define UGSTS 0x188 /* 32-bit register */
19 #define LPSTS_SUSPM 0x4000
22 #define UGCTRL_PLLRESET 0x00000001
23 #define UGCTRL_CONNECT 0x00000004
27 * Remarks: bit[31:11] and bit[9:6] should be 0
29 #define UGCTRL2_RESERVED_3 0x00000001 /* bit[3:0] should be B'0001 */
30 #define UGCTRL2_USB0SEL_HSUSB 0x00000020
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/amlogic/
Dmeson-g12b.dtsi13 #address-cells = <0x2>;
14 #size-cells = <0x0>;
46 cpu0: cpu@0 {
49 reg = <0x0 0x0>;
59 reg = <0x0 0x1>;
69 reg = <0x0 0x100>;
79 reg = <0x0 0x101>;
89 reg = <0x0 0x102>;
99 reg = <0x0 0x103>;
/kernel/linux/linux-5.10/arch/mips/boot/dts/img/
Dpistachio_marduk.dts31 reg = <0x00000000 0x10000000>;
63 linux,code = <0x101>; /* BTN_1 */
68 linux,code = <0x102>; /* BTN_2 */
81 pinctrl-0 = <&spim1_pins>, <&spim1_quad_pins>, <&spim1_cs0_pin>,
84 cs-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>, <&gpio0 1 GPIO_ACTIVE_HIGH>;
86 flash@0 {
88 reg = <0>;
135 pinctrl-0 = <&pwmpdm0_pin>, <&pwmpdm1_pin>, <&pwmpdm2_pin>,
143 adc-reserved-channels = <0x10>;
152 reg = <0x20>;
/kernel/linux/linux-4.19/drivers/usb/renesas_usbhs/
Drcar3.c13 #define LPSTS 0x102
14 #define UGCTRL 0x180 /* 32-bit register */
15 #define UGCTRL2 0x184 /* 32-bit register */
16 #define UGSTS 0x188 /* 32-bit register */
19 #define LPSTS_SUSPM 0x4000
22 #define UGCTRL_PLLRESET 0x00000001
23 #define UGCTRL_CONNECT 0x00000004
27 * Remarks: bit[31:11] and bit[9:6] should be 0
29 #define UGCTRL2_RESERVED_3 0x00000001 /* bit[3:0] should be B'0001 */
30 #define UGCTRL2_USB0SEL_EHCI 0x00000010
[all …]

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