| /kernel/linux/linux-4.19/drivers/ide/ |
| D | umc8672.c | 33 * in the beginning of the driver, which sets the speed of drive 0 to 11 (there
34 * are some lines present). 0 - 11 are allowed speed values. These values are
59 #define UMC_DRIVE1 1 /* 0 to 11 allowed */
64 static const u8 pio_to_umc [5] = {0, 3, 7, 10, 11}; /* rough guesses */
66 /* 0 1 2 3 4 5 6 7 8 9 10 11 */
68 {0x0f, 0x0b, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x1},
69 {0x03, 0x02, 0x02, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x1},
70 {0xff, 0xcb, 0xc0, 0x58, 0x36, 0x33, 0x23, 0x22, 0x21, 0x11, 0x10, 0x0}
75 outb_p(port, 0x108); in out_umc()
76 outb_p(wert, 0x109); in out_umc()
[all …]
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| /kernel/linux/linux-5.10/drivers/ide/ |
| D | umc8672.c | 34 * in the beginning of the driver, which sets the speed of drive 0 to 11 (there
35 * are some lines present). 0 - 11 are allowed speed values. These values are
60 #define UMC_DRIVE1 1 /* 0 to 11 allowed */
65 static const u8 pio_to_umc [5] = {0, 3, 7, 10, 11}; /* rough guesses */
67 /* 0 1 2 3 4 5 6 7 8 9 10 11 */
69 {0x0f, 0x0b, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x1},
70 {0x03, 0x02, 0x02, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x1},
71 {0xff, 0xcb, 0xc0, 0x58, 0x36, 0x33, 0x23, 0x22, 0x21, 0x11, 0x10, 0x0}
76 outb_p(port, 0x108); in out_umc()
77 outb_p(wert, 0x109); in out_umc()
[all …]
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| /kernel/linux/linux-4.19/arch/arm/mach-orion5x/ |
| D | bridge-regs.h | 14 #define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE + 0x100)
16 #define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE + 0x104)
18 #define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x108)
19 #define RSTOUTn_MASK_PHYS (ORION5X_BRIDGE_PHYS_BASE + 0x108)
21 #define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE + 0x10c)
23 #define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x110)
25 #define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE + 0x11C)
27 #define BRIDGE_INT_TIMER1_CLR (~0x0004)
29 #define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x200)
31 #define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x204)
[all …]
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| /kernel/linux/linux-5.10/arch/arm/mach-orion5x/ |
| D | bridge-regs.h | 14 #define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE + 0x100)
16 #define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE + 0x104)
18 #define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x108)
19 #define RSTOUTn_MASK_PHYS (ORION5X_BRIDGE_PHYS_BASE + 0x108)
21 #define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE + 0x10c)
23 #define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x110)
25 #define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE + 0x11C)
27 #define BRIDGE_INT_TIMER1_CLR (~0x0004)
29 #define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x200)
31 #define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x204)
[all …]
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| /kernel/linux/linux-5.10/arch/mips/include/asm/ |
| D | hpet.h | 9 #define HPET_ID 0x000
10 #define HPET_PERIOD 0x004
11 #define HPET_CFG 0x010
12 #define HPET_STATUS 0x020
13 #define HPET_COUNTER 0x0f0
15 #define HPET_Tn_CFG(n) (0x100 + 0x20 * n)
16 #define HPET_Tn_CMP(n) (0x108 + 0x20 * n)
17 #define HPET_Tn_ROUTE(n) (0x110 + 0x20 * n)
19 #define HPET_T0_IRS 0x001
20 #define HPET_T1_IRS 0x002
[all …]
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| /kernel/linux/linux-4.19/arch/mips/include/asm/ |
| D | hpet.h | 9 #define HPET_ID 0x000
10 #define HPET_PERIOD 0x004
11 #define HPET_CFG 0x010
12 #define HPET_STATUS 0x020
13 #define HPET_COUNTER 0x0f0
15 #define HPET_Tn_CFG(n) (0x100 + 0x20 * n)
16 #define HPET_Tn_CMP(n) (0x108 + 0x20 * n)
17 #define HPET_Tn_ROUTE(n) (0x110 + 0x20 * n)
19 #define HPET_T0_IRS 0x001
20 #define HPET_T1_IRS 0x002
[all …]
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| /kernel/linux/linux-5.10/drivers/phy/qualcomm/ |
| D | phy-qcom-qmp.h | 10 #define QSERDES_COM_BG_TIMER 0x00c
11 #define QSERDES_COM_SSC_EN_CENTER 0x010
12 #define QSERDES_COM_SSC_ADJ_PER1 0x014
13 #define QSERDES_COM_SSC_ADJ_PER2 0x018
14 #define QSERDES_COM_SSC_PER1 0x01c
15 #define QSERDES_COM_SSC_PER2 0x020
16 #define QSERDES_COM_SSC_STEP_SIZE1 0x024
17 #define QSERDES_COM_SSC_STEP_SIZE2 0x028
18 #define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034
19 #define QSERDES_COM_CLK_ENABLE1 0x038
[all …]
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| /kernel/linux/linux-4.19/arch/arm/mach-omap2/ |
| D | omap-secure.h | 17 #define API_HAL_RET_VALUE_NS2S_CONVERSION_ERROR 0xFFFFFFFE
18 #define API_HAL_RET_VALUE_SERVICE_UNKNWON 0xFFFFFFFF
21 #define API_HAL_RET_VALUE_OK 0x00
22 #define API_HAL_RET_VALUE_FAIL 0x01
25 #define FLAG_START_CRITICAL 0x4
26 #define FLAG_IRQFIQ_MASK 0x3
27 #define FLAG_IRQ_ENABLE 0x2
28 #define FLAG_FIQ_ENABLE 0x1
29 #define NO_FLAG 0x0
34 #define OMAP3_SAVE_SECURE_RAM_SZ 0x803F
[all …]
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| /kernel/linux/linux-5.10/arch/arm/mach-mmp/ |
| D | regs-icu.h | 11 #define ICU_VIRT_BASE (AXI_VIRT_BASE + 0x82000)
14 #define ICU2_VIRT_BASE (AXI_VIRT_BASE + 0x84000)
18 #define ICU_INT_CONF_MASK (0xf)
25 #define ICU_AP_FIQ_SEL_INT_NUM ICU_REG(0x108) /* AP FIQ Selected Interrupt */
26 #define ICU_AP_IRQ_SEL_INT_NUM ICU_REG(0x10C) /* AP IRQ Selected Interrupt */
27 #define ICU_AP_GBL_IRQ_MSK ICU_REG(0x114) /* AP Global Interrupt Mask */
28 #define ICU_INT_STATUS_0 ICU_REG(0x128) /* Interrupt Stuats 0 */
29 #define ICU_INT_STATUS_1 ICU_REG(0x12C) /* Interrupt Status 1 */
41 #define MMP2_ICU_PJ4_IRQ_STATUS0 ICU_REG(0x138)
42 #define MMP2_ICU_PJ4_IRQ_STATUS1 ICU_REG(0x13c)
[all …]
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| /kernel/linux/linux-5.10/arch/arm/mach-omap2/ |
| D | omap-secure.h | 16 #define API_HAL_RET_VALUE_NS2S_CONVERSION_ERROR 0xFFFFFFFE
17 #define API_HAL_RET_VALUE_SERVICE_UNKNWON 0xFFFFFFFF
20 #define API_HAL_RET_VALUE_OK 0x00
21 #define API_HAL_RET_VALUE_FAIL 0x01
24 #define FLAG_START_CRITICAL 0x4
25 #define FLAG_IRQFIQ_MASK 0x3
26 #define FLAG_IRQ_ENABLE 0x2
27 #define FLAG_FIQ_ENABLE 0x1
28 #define NO_FLAG 0x0
33 #define OMAP3_SAVE_SECURE_RAM_SZ 0x803F
[all …]
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| /kernel/linux/linux-4.19/arch/arm/mach-mmp/ |
| D | regs-icu.h | 14 #define ICU_VIRT_BASE (AXI_VIRT_BASE + 0x82000)
18 #define ICU_INT_CONF_MASK (0xf)
25 #define ICU_AP_FIQ_SEL_INT_NUM ICU_REG(0x108) /* AP FIQ Selected Interrupt */
26 #define ICU_AP_IRQ_SEL_INT_NUM ICU_REG(0x10C) /* AP IRQ Selected Interrupt */
27 #define ICU_AP_GBL_IRQ_MSK ICU_REG(0x114) /* AP Global Interrupt Mask */
28 #define ICU_INT_STATUS_0 ICU_REG(0x128) /* Interrupt Stuats 0 */
29 #define ICU_INT_STATUS_1 ICU_REG(0x12C) /* Interrupt Status 1 */
41 #define MMP2_ICU_PJ4_IRQ_STATUS0 ICU_REG(0x138)
42 #define MMP2_ICU_PJ4_IRQ_STATUS1 ICU_REG(0x13c)
43 #define MMP2_ICU_PJ4_FIQ_STATUS0 ICU_REG(0x140)
[all …]
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| /kernel/linux/linux-5.10/drivers/media/pci/cx18/ |
| D | cx18-av-audio.c | 60 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 in set_audclk_freq()
61 * AUX_PLL Integer = 0x0d, AUX PLL Post Divider = 0x20 in set_audclk_freq()
63 cx18_av_write4(cx, 0x108, 0x200d040f); in set_audclk_freq()
65 /* VID_PLL Fraction = 0x2be2fe */ in set_audclk_freq()
66 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/ in set_audclk_freq()
67 cx18_av_write4(cx, 0x10c, 0x002be2fe); in set_audclk_freq()
69 /* AUX_PLL Fraction = 0x176740c */ in set_audclk_freq()
70 /* xtal * 0xd.bb3a060/0x20 = 32000 * 384: 393 MHz p-pd*/ in set_audclk_freq()
71 cx18_av_write4(cx, 0x110, 0x0176740c); in set_audclk_freq()
74 /* 0x1.f77f = (4 * xtal/8*2/455) / 32000 */ in set_audclk_freq()
[all …]
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| /kernel/linux/linux-5.10/arch/x86/include/asm/ |
| D | hpet.h | 11 #define HPET_ID 0x000
12 #define HPET_PERIOD 0x004
13 #define HPET_CFG 0x010
14 #define HPET_STATUS 0x020
15 #define HPET_COUNTER 0x0f0
17 #define HPET_Tn_CFG(n) (0x100 + 0x20 * n)
18 #define HPET_Tn_CMP(n) (0x108 + 0x20 * n)
19 #define HPET_Tn_ROUTE(n) (0x110 + 0x20 * n)
21 #define HPET_T0_CFG 0x100
22 #define HPET_T0_CMP 0x108
[all …]
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| /kernel/linux/linux-4.19/arch/x86/include/asm/ |
| D | hpet.h | 11 #define HPET_ID 0x000
12 #define HPET_PERIOD 0x004
13 #define HPET_CFG 0x010
14 #define HPET_STATUS 0x020
15 #define HPET_COUNTER 0x0f0
17 #define HPET_Tn_CFG(n) (0x100 + 0x20 * n)
18 #define HPET_Tn_CMP(n) (0x108 + 0x20 * n)
19 #define HPET_Tn_ROUTE(n) (0x110 + 0x20 * n)
21 #define HPET_T0_CFG 0x100
22 #define HPET_T0_CMP 0x108
[all …]
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| /kernel/linux/linux-4.19/drivers/media/pci/cx18/ |
| D | cx18-av-audio.c | 69 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 in set_audclk_freq()
70 * AUX_PLL Integer = 0x0d, AUX PLL Post Divider = 0x20 in set_audclk_freq()
72 cx18_av_write4(cx, 0x108, 0x200d040f); in set_audclk_freq()
74 /* VID_PLL Fraction = 0x2be2fe */ in set_audclk_freq()
75 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/ in set_audclk_freq()
76 cx18_av_write4(cx, 0x10c, 0x002be2fe); in set_audclk_freq()
78 /* AUX_PLL Fraction = 0x176740c */ in set_audclk_freq()
79 /* xtal * 0xd.bb3a060/0x20 = 32000 * 384: 393 MHz p-pd*/ in set_audclk_freq()
80 cx18_av_write4(cx, 0x110, 0x0176740c); in set_audclk_freq()
83 /* 0x1.f77f = (4 * xtal/8*2/455) / 32000 */ in set_audclk_freq()
[all …]
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| /kernel/linux/linux-5.10/drivers/media/i2c/cx25840/ |
| D | cx25840-audio.c | 39 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 in cx25840_set_audclk_freq()
40 * AUX_PLL Integer = 0x06, AUX PLL Post Divider = 0x10 in cx25840_set_audclk_freq()
42 cx25840_write4(client, 0x108, 0x1006040f); in cx25840_set_audclk_freq()
45 * VID_PLL Fraction (register 0x10c) = 0x2be2fe in cx25840_set_audclk_freq()
46 * 28636360 * 0xf.15f17f0/4 = 108 MHz in cx25840_set_audclk_freq()
51 * AUX_PLL Fraction = 0x1bb39ee in cx25840_set_audclk_freq()
52 * 28636363 * 0x6.dd9cf70/0x10 = 32000 * 384 in cx25840_set_audclk_freq()
57 cx25840_write4(client, 0x110, 0x01bb39ee); in cx25840_set_audclk_freq()
61 * SA_MCLK_DIV = 0x10 = 384/384 * AUX_PLL post dvivider in cx25840_set_audclk_freq()
63 cx25840_write(client, 0x127, 0x50); in cx25840_set_audclk_freq()
[all …]
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| /kernel/linux/linux-4.19/drivers/media/i2c/cx25840/ |
| D | cx25840-audio.c | 48 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 in cx25840_set_audclk_freq()
49 * AUX_PLL Integer = 0x06, AUX PLL Post Divider = 0x10 in cx25840_set_audclk_freq()
51 cx25840_write4(client, 0x108, 0x1006040f); in cx25840_set_audclk_freq()
54 * VID_PLL Fraction (register 0x10c) = 0x2be2fe in cx25840_set_audclk_freq()
55 * 28636360 * 0xf.15f17f0/4 = 108 MHz in cx25840_set_audclk_freq()
60 * AUX_PLL Fraction = 0x1bb39ee in cx25840_set_audclk_freq()
61 * 28636363 * 0x6.dd9cf70/0x10 = 32000 * 384 in cx25840_set_audclk_freq()
66 cx25840_write4(client, 0x110, 0x01bb39ee); in cx25840_set_audclk_freq()
70 * SA_MCLK_DIV = 0x10 = 384/384 * AUX_PLL post dvivider in cx25840_set_audclk_freq()
72 cx25840_write(client, 0x127, 0x50); in cx25840_set_audclk_freq()
[all …]
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| /kernel/linux/linux-4.19/drivers/phy/qualcomm/ |
| D | phy-qcom-qmp.h | 10 #define QSERDES_COM_BG_TIMER 0x00c
11 #define QSERDES_COM_SSC_EN_CENTER 0x010
12 #define QSERDES_COM_SSC_ADJ_PER1 0x014
13 #define QSERDES_COM_SSC_ADJ_PER2 0x018
14 #define QSERDES_COM_SSC_PER1 0x01c
15 #define QSERDES_COM_SSC_PER2 0x020
16 #define QSERDES_COM_SSC_STEP_SIZE1 0x024
17 #define QSERDES_COM_SSC_STEP_SIZE2 0x028
18 #define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034
19 #define QSERDES_COM_CLK_ENABLE1 0x038
[all …]
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| /kernel/linux/linux-4.19/drivers/clk/renesas/ |
| D | clk-sh73a0.c | 26 #define CPG_FRQCRA 0x00
27 #define CPG_FRQCRB 0x04
28 #define CPG_SD0CKCR 0x74
29 #define CPG_SD1CKCR 0x78
30 #define CPG_SD2CKCR 0x7c
31 #define CPG_PLLECR 0xd0
32 #define CPG_PLL0CR 0xd8
33 #define CPG_PLL1CR 0x28
34 #define CPG_PLL2CR 0x2c
35 #define CPG_PLL3CR 0xdc
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/renesas/ |
| D | clk-sh73a0.c | 24 #define CPG_FRQCRA 0x00
25 #define CPG_FRQCRB 0x04
26 #define CPG_SD0CKCR 0x74
27 #define CPG_SD1CKCR 0x78
28 #define CPG_SD2CKCR 0x7c
29 #define CPG_PLLECR 0xd0
30 #define CPG_PLL0CR 0xd8
31 #define CPG_PLL1CR 0x28
32 #define CPG_PLL2CR 0x2c
33 #define CPG_PLL3CR 0xdc
[all …]
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| /kernel/linux/linux-5.10/arch/mips/pci/ |
| D | pci-vr41xx.h | 12 #define PCIU_BASE 0x0f000c00UL
13 #define PCIU_SIZE 0x200UL
15 #define PCIMMAW1REG 0x00
16 #define PCIMMAW2REG 0x04
17 #define PCITAW1REG 0x08
18 #define PCITAW2REG 0x0c
19 #define PCIMIOAWREG 0x10
20 #define IBA(addr) ((addr) & 0xff000000U)
21 #define MASTER_MSK(mask) (((mask) >> 11) & 0x000fe000U)
22 #define PCIA(addr) (((addr) >> 24) & 0x000000ffU)
[all …]
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| /kernel/linux/linux-4.19/arch/mips/pci/ |
| D | pci-vr41xx.h | 25 #define PCIU_BASE 0x0f000c00UL
26 #define PCIU_SIZE 0x200UL
28 #define PCIMMAW1REG 0x00
29 #define PCIMMAW2REG 0x04
30 #define PCITAW1REG 0x08
31 #define PCITAW2REG 0x0c
32 #define PCIMIOAWREG 0x10
33 #define IBA(addr) ((addr) & 0xff000000U)
34 #define MASTER_MSK(mask) (((mask) >> 11) & 0x000fe000U)
35 #define PCIA(addr) (((addr) >> 24) & 0x000000ffU)
[all …]
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| /kernel/linux/linux-5.10/arch/arm/mach-s3c/ |
| D | regs-sys-s3c64xx.h | 16 #define S3C64XX_AHB_CON0 S3C_SYSREG(0x100)
17 #define S3C64XX_AHB_CON1 S3C_SYSREG(0x104)
18 #define S3C64XX_AHB_CON2 S3C_SYSREG(0x108)
20 #define S3C64XX_SDMA_SEL S3C_SYSREG(0x110)
22 #define S3C64XX_OTHERS S3C_SYSREG(0x900)
|
| /kernel/linux/linux-4.19/arch/arm/mach-s3c64xx/ |
| D | regs-sys.h | 19 #define S3C64XX_AHB_CON0 S3C_SYSREG(0x100)
20 #define S3C64XX_AHB_CON1 S3C_SYSREG(0x104)
21 #define S3C64XX_AHB_CON2 S3C_SYSREG(0x108)
23 #define S3C64XX_SDMA_SEL S3C_SYSREG(0x110)
25 #define S3C64XX_OTHERS S3C_SYSREG(0x900)
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/arm64/ampere/emag/ |
| D | pipeline.json | 4 "EventCode": "0x108",
10 "EventCode": "0x109",
16 "EventCode": "0x10a",
22 "EventCode": "0x10b",
28 "EventCode": "0x10c",
34 "EventCode": "0x10d",
40 "EventCode": "0x10e",
46 "EventCode": "0x10f",
|