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/kernel/linux/linux-4.19/Documentation/devicetree/bindings/i2c/
Di2c-mv64xxx.txt41 reg = <0x11000 0x20>;
50 reg = <0x11000 0x100>;
59 reg = <0x701000 0x20>;
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/i2c/
Dmarvell,mv64xxx-i2c.yaml105 reg = <0x11000 0x20>;
113 reg = <0x11000 0x100>;
121 reg = <0x701000 0x20>;
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/powerpc/fsl/
Dsrio.txt9 Revision Register (SRIO IPBRR1) Major ID equal to 0x01c0.
20 be set to 0x11000.
83 reg = <0xf 0xfe0c0000 0 0x11000>;
94 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
102 ranges = <0 0 0xc 0x30000000 0 0x10000000>;
Dmpc5121-psc.txt55 cell-index = <0>;
56 reg = <0x11000 0x100>;
57 interrupts = <40 0x8>;
66 reg = <0x11100 0x100>;
67 interrupts = <40 0x8>;
75 reg = <0x11f00 0x100>;
76 interrupts = <40 0x8>;
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/powerpc/fsl/
Dsrio.txt9 Revision Register (SRIO IPBRR1) Major ID equal to 0x01c0.
20 be set to 0x11000.
83 reg = <0xf 0xfe0c0000 0 0x11000>;
94 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
102 ranges = <0 0 0xc 0x30000000 0 0x10000000>;
/kernel/linux/linux-5.10/drivers/media/pci/cx25821/
Dcx25821-sram.h12 /* #define RX_SRAM_START_SIZE = 0; // Start of reserved SRAM */
17 /* #define RX_SRAM_POOL_START_SIZE = 0; // Start of usable RX SRAM for buffers */
27 /* #define RX_SRAM_END_SIZE = 0; // End of RX SRAM */
29 /* #define TX_SRAM_POOL_START_SIZE = 0; // Start of transmit pool SRAM */
37 /* #define TX_SRAM_END_SIZE = 0; // End of TX SRAM */
40 #define RX_SRAM_START 0x10000
41 #define VID_A_DOWN_CMDS 0x10000
42 #define VID_B_DOWN_CMDS 0x10050
43 #define VID_C_DOWN_CMDS 0x100A0
44 #define VID_D_DOWN_CMDS 0x100F0
[all …]
/kernel/linux/linux-4.19/drivers/media/pci/cx25821/
Dcx25821-sram.h22 /* #define RX_SRAM_START_SIZE = 0; // Start of reserved SRAM */
27 /* #define RX_SRAM_POOL_START_SIZE = 0; // Start of useable RX SRAM for buffers */
37 /* #define RX_SRAM_END_SIZE = 0; // End of RX SRAM */
39 /* #define TX_SRAM_POOL_START_SIZE = 0; // Start of transmit pool SRAM */
47 /* #define TX_SRAM_END_SIZE = 0; // End of TX SRAM */
50 #define RX_SRAM_START 0x10000
51 #define VID_A_DOWN_CMDS 0x10000
52 #define VID_B_DOWN_CMDS 0x10050
53 #define VID_C_DOWN_CMDS 0x100A0
54 #define VID_D_DOWN_CMDS 0x100F0
[all …]
/kernel/linux/linux-4.19/arch/s390/kernel/
Dmachine_kexec_file.c157 for (i = 0; i < relsec->sh_size / sizeof(*relas); i++) { in arch_kexec_apply_relocations_add()
192 *(u16 *)loc &= 0xf000; in arch_kexec_apply_relocations_add()
193 *(u16 *)loc |= val & 0xfff; in arch_kexec_apply_relocations_add()
199 *(u32 *)loc &= 0xf00000ff; in arch_kexec_apply_relocations_add()
200 *(u32 *)loc |= (val & 0xfff) << 16; /* DL */ in arch_kexec_apply_relocations_add()
201 *(u32 *)loc |= (val & 0xff000) >> 4; /* DH */ in arch_kexec_apply_relocations_add()
228 return 0; in arch_kexec_apply_relocations_add()
239 * 0x11000 = sizeof(head.S) in arch_kexec_kernel_image_probe()
241 if (buf_len < 0x11000) in arch_kexec_kernel_image_probe()
/kernel/linux/linux-5.10/sound/sh/
Daica.h11 #define G2_FIFO 0xa05f688c
12 #define SPU_MEMORY_BASE 0xA0800000
13 #define ARM_RESET_REGISTER 0xA0702C00
14 #define SPU_REGISTER_BASE 0xA0700000
17 #define AICA_CONTROL_POINT 0xA0810000
18 #define AICA_CONTROL_CHANNEL_SAMPLE_NUMBER 0xA0810008
19 #define AICA_CHANNEL0_CONTROL_OFFSET 0x10004
22 #define AICA_CMD_KICK 0x80000000
23 #define AICA_CMD_NONE 0
30 #define SM_16BIT 0
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mtd/
Dlpc32xx-mlc.txt28 reg = <0x200A8000 0x11000>;
29 interrupts = <11 0>;
44 reg = <0x00000000 0x00064000>;
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/mtd/
Dlpc32xx-mlc.txt28 reg = <0x200A8000 0x11000>;
29 interrupts = <11 0>;
44 reg = <0x00000000 0x00064000>;
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/interconnect/
Dqcom,msm8916.yaml54 reg = <0x00400000 0x62000>;
63 reg = <0x00500000 0x11000>;
72 reg = <0x00580000 0x14000>;
/kernel/linux/linux-4.19/sound/sh/
Daica.h24 #define G2_FIFO 0xa05f688c
25 #define SPU_MEMORY_BASE 0xA0800000
26 #define ARM_RESET_REGISTER 0xA0702C00
27 #define SPU_REGISTER_BASE 0xA0700000
30 #define AICA_CONTROL_POINT 0xA0810000
31 #define AICA_CONTROL_CHANNEL_SAMPLE_NUMBER 0xA0810008
32 #define AICA_CHANNEL0_CONTROL_OFFSET 0x10004
35 #define AICA_CMD_KICK 0x80000000
36 #define AICA_CMD_NONE 0
43 #define SM_16BIT 0
[all …]
/kernel/linux/linux-5.10/arch/m68k/include/asm/
Dapollohw.h52 #define IO_BASE 0x80000000
62 #define SAU7_SIO01_PHYSADDR 0x10400
63 #define SAU7_SIO23_PHYSADDR 0x10500
64 #define SAU7_RTC_PHYSADDR 0x10900
65 #define SAU7_PICA 0x11000
66 #define SAU7_PICB 0x11100
67 #define SAU7_CPUCTRL 0x10100
68 #define SAU7_TIMER 0x010800
70 #define SAU8_SIO01_PHYSADDR 0x8400
71 #define SAU8_RTC_PHYSADDR 0x8900
[all …]
/kernel/linux/linux-4.19/arch/m68k/include/asm/
Dapollohw.h52 #define IO_BASE 0x80000000
62 #define SAU7_SIO01_PHYSADDR 0x10400
63 #define SAU7_SIO23_PHYSADDR 0x10500
64 #define SAU7_RTC_PHYSADDR 0x10900
65 #define SAU7_PICA 0x11000
66 #define SAU7_PICB 0x11100
67 #define SAU7_CPUCTRL 0x10100
68 #define SAU7_TIMER 0x010800
70 #define SAU8_SIO01_PHYSADDR 0x8400
71 #define SAU8_RTC_PHYSADDR 0x8900
[all …]
/kernel/linux/linux-4.19/arch/powerpc/boot/dts/
Dvirtex440-ml510.dts19 DDR2_SDRAM_DIMM0: memory@0 {
21 reg = < 0x0 0x20000000 >;
29 stdout-path = "/plb@0/serial@83e00000";
33 #cpus = <0x1>;
34 #size-cells = <0>;
35 ppc440_0: cpu@0 {
40 d-cache-line-size = <0x20>;
41 d-cache-size = <0x8000>;
45 i-cache-line-size = <0x20>;
46 i-cache-size = <0x8000>;
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-ixp4xx/include/mach/
Dixp4xx-regs.h23 * 0x00000000 0x10000000(max) PAGE_OFFSET System RAM
25 * 0x48000000 0x04000000 ioremap'd PCI Memory Space
27 * 0x50000000 0x10000000 ioremap'd EXP BUS
29 * 0xC8000000 0x00013000 0xFEF00000 On-Chip Peripherals
31 * 0xC0000000 0x00001000 0xFEF13000 PCI CFG
33 * 0xC4000000 0x00001000 0xFEF14000 EXP CFG
35 * 0x60000000 0x00004000 0xFEF15000 QMgr
41 #define IXP4XX_QMGR_BASE_PHYS 0x60000000
47 #define IXP4XX_PERIPHERAL_BASE_PHYS 0xC8000000
48 #define IXP4XX_PERIPHERAL_BASE_VIRT IOMEM(0xFEF00000)
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ti/davinci/
Dpll.txt30 - #clock-cells: shall be 0
45 - #clock-cells: shall be 0
51 - #clock-cells: shall be 0
58 reg = <0x11000 0x1000>;
64 #clock-cells = <0>;
72 #clock-cells = <0>;
76 #clock-cells = <0>;
82 reg = <0x21a000 0x1000>;
91 #clock-cells = <0>;
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/clock/ti/davinci/
Dpll.txt30 - #clock-cells: shall be 0
45 - #clock-cells: shall be 0
51 - #clock-cells: shall be 0
58 reg = <0x11000 0x1000>;
64 #clock-cells = <0>;
72 #clock-cells = <0>;
76 #clock-cells = <0>;
82 reg = <0x21a000 0x1000>;
91 #clock-cells = <0>;
/kernel/linux/linux-5.10/arch/mips/include/asm/netlogic/xlr/
Diomap.h38 #define DEFAULT_NETLOGIC_IO_BASE CKSEG1ADDR(0x1ef00000)
39 #define NETLOGIC_IO_DDR2_CHN0_OFFSET 0x01000
40 #define NETLOGIC_IO_DDR2_CHN1_OFFSET 0x02000
41 #define NETLOGIC_IO_DDR2_CHN2_OFFSET 0x03000
42 #define NETLOGIC_IO_DDR2_CHN3_OFFSET 0x04000
43 #define NETLOGIC_IO_PIC_OFFSET 0x08000
44 #define NETLOGIC_IO_UART_0_OFFSET 0x14000
45 #define NETLOGIC_IO_UART_1_OFFSET 0x15100
47 #define NETLOGIC_IO_SIZE 0x1000
49 #define NETLOGIC_IO_BRIDGE_OFFSET 0x00000
[all …]
/kernel/linux/linux-4.19/arch/mips/include/asm/netlogic/xlr/
Diomap.h38 #define DEFAULT_NETLOGIC_IO_BASE CKSEG1ADDR(0x1ef00000)
39 #define NETLOGIC_IO_DDR2_CHN0_OFFSET 0x01000
40 #define NETLOGIC_IO_DDR2_CHN1_OFFSET 0x02000
41 #define NETLOGIC_IO_DDR2_CHN2_OFFSET 0x03000
42 #define NETLOGIC_IO_DDR2_CHN3_OFFSET 0x04000
43 #define NETLOGIC_IO_PIC_OFFSET 0x08000
44 #define NETLOGIC_IO_UART_0_OFFSET 0x14000
45 #define NETLOGIC_IO_UART_1_OFFSET 0x15100
47 #define NETLOGIC_IO_SIZE 0x1000
49 #define NETLOGIC_IO_BRIDGE_OFFSET 0x00000
[all …]
/kernel/linux/linux-4.19/arch/powerpc/platforms/embedded6xx/
Dstorcenter.c35 return 0; in storcenter_device_probe()
54 hose->first_busno = bus_range ? bus_range[0] : 0; in storcenter_add_bridge()
55 hose->last_busno = bus_range ? bus_range[1] : 0xff; in storcenter_add_bridge()
57 setup_indirect_pci(hose, MPC10X_MAPB_CNFG_ADDR, MPC10X_MAPB_CNFG_DATA, 0); in storcenter_add_bridge()
64 return 0; in storcenter_add_bridge()
86 mpic = mpic_alloc(NULL, 0, 0, 16, 0, " OpenPIC "); in storcenter_init_IRQ()
91 * I2C is the second internal, so it is at 17, 0x11020. in storcenter_init_IRQ()
93 mpic_assign_isu(mpic, 0, mpic->paddr + 0x10200); in storcenter_init_IRQ()
94 mpic_assign_isu(mpic, 1, mpic->paddr + 0x11000); in storcenter_init_IRQ()
104 _nmask_and_or_msr(0, MSR_IP); in storcenter_restart()
/kernel/linux/linux-5.10/arch/powerpc/platforms/embedded6xx/
Dstorcenter.c35 return 0; in storcenter_device_probe()
54 hose->first_busno = bus_range ? bus_range[0] : 0; in storcenter_add_bridge()
55 hose->last_busno = bus_range ? bus_range[1] : 0xff; in storcenter_add_bridge()
57 setup_indirect_pci(hose, MPC10X_MAPB_CNFG_ADDR, MPC10X_MAPB_CNFG_DATA, 0); in storcenter_add_bridge()
64 return 0; in storcenter_add_bridge()
86 mpic = mpic_alloc(NULL, 0, 0, 16, 0, " OpenPIC "); in storcenter_init_IRQ()
91 * I2C is the second internal, so it is at 17, 0x11020. in storcenter_init_IRQ()
93 mpic_assign_isu(mpic, 0, mpic->paddr + 0x10200); in storcenter_init_IRQ()
94 mpic_assign_isu(mpic, 1, mpic->paddr + 0x11000); in storcenter_init_IRQ()
/kernel/linux/linux-5.10/arch/powerpc/boot/dts/fsl/
Db4860qds.dts50 board-control@3,0 {
79 reg = <0x1e>;
84 reg = <0x1f>;
92 reg = <0x7>;
98 reg = <0x6>;
106 reg = <0xf 0xfe0c0000 0 0x11000>;
109 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
112 ranges = <0 0 0xc 0x30000000 0 0x10000000>;
/kernel/linux/linux-4.19/arch/powerpc/boot/dts/fsl/
Db4860qds.dts50 board-control@3,0 {
79 reg = <0x1e>;
84 reg = <0x1f>;
92 reg = <0x7>;
98 reg = <0x6>;
106 reg = <0xf 0xfe0c0000 0 0x11000>;
109 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
112 ranges = <0 0 0xc 0x30000000 0 0x10000000>;

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