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/kernel/linux/linux-5.10/drivers/clk/renesas/
Dr8a774a1-cpg-mssr.c75 DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
96 DEF_GEN3_SD("sd0", R8A774A1_CLK_SD0, CLK_SDSRC, 0x074),
97 DEF_GEN3_SD("sd1", R8A774A1_CLK_SD1, CLK_SDSRC, 0x078),
98 DEF_GEN3_SD("sd2", R8A774A1_CLK_SD2, CLK_SDSRC, 0x268),
99 DEF_GEN3_SD("sd3", R8A774A1_CLK_SD3, CLK_SDSRC, 0x26c),
105 DEF_DIV6P1("canfd", R8A774A1_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
106 DEF_DIV6P1("csi0", R8A774A1_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
107 DEF_DIV6P1("mso", R8A774A1_CLK_MSO, CLK_PLL1_DIV4, 0x014),
108 DEF_DIV6P1("hdmi", R8A774A1_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
121 DEF_MOD("fdp1-0", 119, R8A774A1_CLK_S0D1),
[all …]
Dr8a77965-cpg-mssr.c104 DEF_GEN3_SD("sd0", R8A77965_CLK_SD0, CLK_SDSRC, 0x074),
105 DEF_GEN3_SD("sd1", R8A77965_CLK_SD1, CLK_SDSRC, 0x078),
106 DEF_GEN3_SD("sd2", R8A77965_CLK_SD2, CLK_SDSRC, 0x268),
107 DEF_GEN3_SD("sd3", R8A77965_CLK_SD3, CLK_SDSRC, 0x26c),
114 DEF_DIV6P1("canfd", R8A77965_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
115 DEF_DIV6P1("csi0", R8A77965_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
116 DEF_DIV6P1("mso", R8A77965_CLK_MSO, CLK_PLL1_DIV4, 0x014),
117 DEF_DIV6P1("hdmi", R8A77965_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
125 DEF_MOD("fdp1-0", 119, R8A77965_CLK_S0D1),
278 * 0 0 0 0 16.66 x 1 x180 x192 x192 x144 /16
[all …]
Dr8a774b1-cpg-mssr.c93 DEF_GEN3_SD("sd0", R8A774B1_CLK_SD0, CLK_SDSRC, 0x074),
94 DEF_GEN3_SD("sd1", R8A774B1_CLK_SD1, CLK_SDSRC, 0x078),
95 DEF_GEN3_SD("sd2", R8A774B1_CLK_SD2, CLK_SDSRC, 0x268),
96 DEF_GEN3_SD("sd3", R8A774B1_CLK_SD3, CLK_SDSRC, 0x26c),
102 DEF_DIV6P1("canfd", R8A774B1_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
103 DEF_DIV6P1("csi0", R8A774B1_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
104 DEF_DIV6P1("mso", R8A774B1_CLK_MSO, CLK_PLL1_DIV4, 0x014),
105 DEF_DIV6P1("hdmi", R8A774B1_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
118 DEF_MOD("fdp1-0", 119, R8A774B1_CLK_S0D1),
248 * 0 0 0 0 16.66 x 1 x180 x192 x192 x144 /16
[all …]
Dr8a7796-cpg-mssr.c87 DEF_GEN3_Z("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
109 DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, CLK_SDSRC, 0x074),
110 DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, CLK_SDSRC, 0x078),
111 DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, CLK_SDSRC, 0x268),
112 DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, CLK_SDSRC, 0x26c),
119 DEF_DIV6P1("canfd", R8A7796_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
120 DEF_DIV6P1("csi0", R8A7796_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
121 DEF_DIV6P1("mso", R8A7796_CLK_MSO, CLK_PLL1_DIV4, 0x014),
122 DEF_DIV6P1("hdmi", R8A7796_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
130 DEF_MOD("fdp1-0", 119, R8A7796_CLK_S0D1),
[all …]
Dr8a774e1-cpg-mssr.c82 DEF_GEN3_Z("z2", R8A774E1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
103 DEF_GEN3_SD("sd0", R8A774E1_CLK_SD0, CLK_SDSRC, 0x074),
104 DEF_GEN3_SD("sd1", R8A774E1_CLK_SD1, CLK_SDSRC, 0x078),
105 DEF_GEN3_SD("sd2", R8A774E1_CLK_SD2, CLK_SDSRC, 0x268),
106 DEF_GEN3_SD("sd3", R8A774E1_CLK_SD3, CLK_SDSRC, 0x26c),
113 DEF_DIV6P1("canfd", R8A774E1_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
114 DEF_DIV6P1("csi0", R8A774E1_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
115 DEF_DIV6P1("mso", R8A774E1_CLK_MSO, CLK_PLL1_DIV4, 0x014),
116 DEF_DIV6P1("hdmi", R8A774E1_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
125 DEF_MOD("fdp1-0", 119, R8A774E1_CLK_S0D1),
[all …]
Dr8a779a0-cpg-mssr.c102 DEF_PLL(".pll20", CLK_PLL20, 0x0834),
103 DEF_PLL(".pll21", CLK_PLL21, 0x0838),
104 DEF_PLL(".pll30", CLK_PLL30, 0x083c),
105 DEF_PLL(".pll31", CLK_PLL31, 0x0840),
141 DEF_DIV6P1("mso", R8A779A0_CLK_MSO, CLK_PLL5_DIV4, 0x87c),
142 DEF_DIV6P1("canfd", R8A779A0_CLK_CANFD, CLK_PLL5_DIV4, 0x878),
143 DEF_DIV6P1("csi0", R8A779A0_CLK_CSI0, CLK_PLL5_DIV4, 0x880),
172 parent = clks[core->parent & 0xffff]; /* some types use high bits */ in rcar_r8a779a0_cpg_clk_register()
188 mult = (((value >> 24) & 0x7f) + 1) * 2; in rcar_r8a779a0_cpg_clk_register()
202 div = core->div & 0xffff; in rcar_r8a779a0_cpg_clk_register()
[all …]
Dr8a7795-cpg-mssr.c85 DEF_GEN3_Z("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
107 DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, CLK_SDSRC, 0x074),
108 DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, CLK_SDSRC, 0x078),
109 DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_SDSRC, 0x268),
110 DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_SDSRC, 0x26c),
117 DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
118 DEF_DIV6P1("csi0", R8A7795_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
119 DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014),
120 DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
130 DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1),
[all …]
/kernel/linux/linux-4.19/drivers/clk/renesas/
Dr8a7796-cpg-mssr.c100 DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, CLK_SDSRC, 0x074),
101 DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, CLK_SDSRC, 0x078),
102 DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, CLK_SDSRC, 0x268),
103 DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, CLK_SDSRC, 0x26c),
108 DEF_DIV6P1("canfd", R8A7796_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
109 DEF_DIV6P1("csi0", R8A7796_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
110 DEF_DIV6P1("mso", R8A7796_CLK_MSO, CLK_PLL1_DIV4, 0x014),
111 DEF_DIV6P1("hdmi", R8A7796_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
120 DEF_MOD("fdp1-0", 119, R8A7796_CLK_S0D1),
261 * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144
[all …]
Dr8a77965-cpg-mssr.c94 DEF_GEN3_SD("sd0", R8A77965_CLK_SD0, CLK_SDSRC, 0x074),
95 DEF_GEN3_SD("sd1", R8A77965_CLK_SD1, CLK_SDSRC, 0x078),
96 DEF_GEN3_SD("sd2", R8A77965_CLK_SD2, CLK_SDSRC, 0x268),
97 DEF_GEN3_SD("sd3", R8A77965_CLK_SD3, CLK_SDSRC, 0x26c),
102 DEF_DIV6P1("canfd", R8A77965_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
103 DEF_DIV6P1("csi0", R8A77965_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
104 DEF_DIV6P1("mso", R8A77965_CLK_MSO, CLK_PLL1_DIV4, 0x014),
105 DEF_DIV6P1("hdmi", R8A77965_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
258 * 0 0 0 0 16.66 x 1 x180 x192 x192 x144
259 * 0 0 0 1 16.66 x 1 x180 x192 x128 x144
[all …]
Dr8a7795-cpg-mssr.c100 DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, CLK_SDSRC, 0x074),
101 DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, CLK_SDSRC, 0x078),
102 DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_SDSRC, 0x268),
103 DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_SDSRC, 0x26c),
109 DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
110 DEF_DIV6P1("csi0", R8A7795_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
111 DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014),
112 DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
123 DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1),
289 * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/
Dsitronix,st7735r.yaml23 Adafruit 1.8" 160x128 Color TFT LCD (Product ID 358 or 618)
29 Okaya 1.44" 128x128 Color TFT LCD (E.g. Renesas YRSK-LCD-PMOD)
66 #size-cells = <0>;
68 display@0{
70 reg = <0>;
/kernel/linux/linux-5.10/drivers/media/pci/cx18/
Dcx18-av-audio.c60 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 in set_audclk_freq()
61 * AUX_PLL Integer = 0x0d, AUX PLL Post Divider = 0x20 in set_audclk_freq()
63 cx18_av_write4(cx, 0x108, 0x200d040f); in set_audclk_freq()
65 /* VID_PLL Fraction = 0x2be2fe */ in set_audclk_freq()
66 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/ in set_audclk_freq()
67 cx18_av_write4(cx, 0x10c, 0x002be2fe); in set_audclk_freq()
69 /* AUX_PLL Fraction = 0x176740c */ in set_audclk_freq()
70 /* xtal * 0xd.bb3a060/0x20 = 32000 * 384: 393 MHz p-pd*/ in set_audclk_freq()
71 cx18_av_write4(cx, 0x110, 0x0176740c); in set_audclk_freq()
74 /* 0x1.f77f = (4 * xtal/8*2/455) / 32000 */ in set_audclk_freq()
[all …]
/kernel/linux/linux-4.19/drivers/media/pci/cx18/
Dcx18-av-audio.c69 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 in set_audclk_freq()
70 * AUX_PLL Integer = 0x0d, AUX PLL Post Divider = 0x20 in set_audclk_freq()
72 cx18_av_write4(cx, 0x108, 0x200d040f); in set_audclk_freq()
74 /* VID_PLL Fraction = 0x2be2fe */ in set_audclk_freq()
75 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/ in set_audclk_freq()
76 cx18_av_write4(cx, 0x10c, 0x002be2fe); in set_audclk_freq()
78 /* AUX_PLL Fraction = 0x176740c */ in set_audclk_freq()
79 /* xtal * 0xd.bb3a060/0x20 = 32000 * 384: 393 MHz p-pd*/ in set_audclk_freq()
80 cx18_av_write4(cx, 0x110, 0x0176740c); in set_audclk_freq()
83 /* 0x1.f77f = (4 * xtal/8*2/455) / 32000 */ in set_audclk_freq()
[all …]
/kernel/linux/linux-5.10/drivers/phy/qualcomm/
Dphy-qcom-qmp.h10 #define QSERDES_COM_BG_TIMER 0x00c
11 #define QSERDES_COM_SSC_EN_CENTER 0x010
12 #define QSERDES_COM_SSC_ADJ_PER1 0x014
13 #define QSERDES_COM_SSC_ADJ_PER2 0x018
14 #define QSERDES_COM_SSC_PER1 0x01c
15 #define QSERDES_COM_SSC_PER2 0x020
16 #define QSERDES_COM_SSC_STEP_SIZE1 0x024
17 #define QSERDES_COM_SSC_STEP_SIZE2 0x028
18 #define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034
19 #define QSERDES_COM_CLK_ENABLE1 0x038
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/
Dqcom,qmp-usb3-dp-phy.yaml81 "^usb3-phy@[0-9a-f]+$":
109 const: 0
112 const: 0
121 "^dp-phy@[0-9a-f]+$":
139 const: 0
167 reg = <0x088e9000 0x18c>,
168 <0x088e8000 0x10>,
169 <0x088ea000 0x40>;
174 ranges = <0x0 0x088e9000 0x2000>;
190 reg = <0x200 0x128>,
[all …]
Dberlin-usb-phy.txt6 - #phys-cells: should be 0
13 reg = <0xf774000 0x128>;
14 #phy-cells = <0>;
15 resets = <&chip 0x104 14>;
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/phy/
Dberlin-usb-phy.txt6 - #phys-cells: should be 0
13 reg = <0xf774000 0x128>;
14 #phy-cells = <0>;
15 resets = <&chip 0x104 14>;
/kernel/linux/linux-5.10/drivers/clk/mediatek/
Dclk-mt7622.c295 .set_ofs = 0x8,
296 .clr_ofs = 0x8,
297 .sta_ofs = 0x8,
301 .set_ofs = 0x40,
302 .clr_ofs = 0x44,
303 .sta_ofs = 0x48,
307 .set_ofs = 0x120,
308 .clr_ofs = 0x120,
309 .sta_ofs = 0x120,
313 .set_ofs = 0x128,
[all …]
/kernel/linux/linux-4.19/drivers/clk/mediatek/
Dclk-mt7622.c303 .set_ofs = 0x8,
304 .clr_ofs = 0x8,
305 .sta_ofs = 0x8,
309 .set_ofs = 0x40,
310 .clr_ofs = 0x44,
311 .sta_ofs = 0x48,
315 .set_ofs = 0x120,
316 .clr_ofs = 0x120,
317 .sta_ofs = 0x120,
321 .set_ofs = 0x128,
[all …]
/kernel/linux/linux-4.19/drivers/tty/serial/8250/
D8250_boca.c13 SERIAL8250_PORT(0x100, 12),
14 SERIAL8250_PORT(0x108, 12),
15 SERIAL8250_PORT(0x110, 12),
16 SERIAL8250_PORT(0x118, 12),
17 SERIAL8250_PORT(0x120, 12),
18 SERIAL8250_PORT(0x128, 12),
19 SERIAL8250_PORT(0x130, 12),
20 SERIAL8250_PORT(0x138, 12),
21 SERIAL8250_PORT(0x140, 12),
22 SERIAL8250_PORT(0x148, 12),
[all …]
/kernel/linux/linux-5.10/drivers/tty/serial/8250/
D8250_boca.c13 SERIAL8250_PORT(0x100, 12),
14 SERIAL8250_PORT(0x108, 12),
15 SERIAL8250_PORT(0x110, 12),
16 SERIAL8250_PORT(0x118, 12),
17 SERIAL8250_PORT(0x120, 12),
18 SERIAL8250_PORT(0x128, 12),
19 SERIAL8250_PORT(0x130, 12),
20 SERIAL8250_PORT(0x138, 12),
21 SERIAL8250_PORT(0x140, 12),
22 SERIAL8250_PORT(0x148, 12),
[all …]
/kernel/linux/linux-5.10/arch/x86/crypto/
Dcrc32-pclmul_asm.S29 * CRC32 polynomial:0x04c11db7(BE)/0xEDB88320(LE)
46 * [x4*128+32 mod P(x) << 32)]' << 1 = 0x154442bd4
47 * #define CONSTANT_R1 0x154442bd4LL
49 * [(x4*128-32 mod P(x) << 32)]' << 1 = 0x1c6e41596
50 * #define CONSTANT_R2 0x1c6e41596LL
53 .octa 0x00000001c6e415960000000154442bd4
55 * [(x128+32 mod P(x) << 32)]' << 1 = 0x1751997d0
56 * #define CONSTANT_R3 0x1751997d0LL
58 * [(x128-32 mod P(x) << 32)]' << 1 = 0x0ccaa009e
59 * #define CONSTANT_R4 0x0ccaa009eLL
[all …]
/kernel/linux/linux-4.19/arch/x86/crypto/
Dcrc32-pclmul_asm.S29 * CRC32 polynomial:0x04c11db7(BE)/0xEDB88320(LE)
47 * [x4*128+32 mod P(x) << 32)]' << 1 = 0x154442bd4
48 * #define CONSTANT_R1 0x154442bd4LL
50 * [(x4*128-32 mod P(x) << 32)]' << 1 = 0x1c6e41596
51 * #define CONSTANT_R2 0x1c6e41596LL
54 .octa 0x00000001c6e415960000000154442bd4
56 * [(x128+32 mod P(x) << 32)]' << 1 = 0x1751997d0
57 * #define CONSTANT_R3 0x1751997d0LL
59 * [(x128-32 mod P(x) << 32)]' << 1 = 0x0ccaa009e
60 * #define CONSTANT_R4 0x0ccaa009eLL
[all …]
/kernel/linux/linux-5.10/drivers/video/fbdev/
Dwm8505fb_regs.h15 * Color space select register, default value 0x1c
22 #define WMT_GOVR_COLORSPACE 0x1e4
28 #define WMT_GOVR_COLORSPACE1 0x30
30 #define WMT_GOVR_CONTRAST 0x1b8
31 #define WMT_GOVR_BRGHTNESS 0x1bc /* incompatible with RGB? */
34 #define WMT_GOVR_FBADDR 0x90
35 #define WMT_GOVR_FBADDR1 0x94 /* UV offset in YUV mode */
38 #define WMT_GOVR_XPAN 0xa4
39 #define WMT_GOVR_YPAN 0xa0
41 #define WMT_GOVR_XRES 0x98
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-davinci/
Dclock.h13 #define PLLCTL 0x100
14 #define PLLCTL_PLLEN BIT(0)
21 #define PLLM 0x110
22 #define PLLM_PLLM_MASK 0xff
24 #define PREDIV 0x114
25 #define PLLDIV1 0x118
26 #define PLLDIV2 0x11c
27 #define PLLDIV3 0x120
28 #define POSTDIV 0x128
29 #define BPDIV 0x12c
[all …]

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