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/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
Drv770_smc.c34 #define FIRST_SMC_INT_VECT_REG 0xFFD8
35 #define FIRST_INT_VECT_S19 0xFFC0
39 0x08, 0x10, 0x08, 0x10,
40 0x08, 0x10, 0x08, 0x10,
41 0x08, 0x10, 0x08, 0x10,
42 0x08, 0x10, 0x08, 0x10,
43 0x08, 0x10, 0x08, 0x10,
44 0x08, 0x10, 0x08, 0x10,
45 0x08, 0x10, 0x08, 0x10,
46 0x08, 0x10, 0x08, 0x10,
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/radeon/
Drv770_smc.c34 #define FIRST_SMC_INT_VECT_REG 0xFFD8
35 #define FIRST_INT_VECT_S19 0xFFC0
39 0x08, 0x10, 0x08, 0x10,
40 0x08, 0x10, 0x08, 0x10,
41 0x08, 0x10, 0x08, 0x10,
42 0x08, 0x10, 0x08, 0x10,
43 0x08, 0x10, 0x08, 0x10,
44 0x08, 0x10, 0x08, 0x10,
45 0x08, 0x10, 0x08, 0x10,
46 0x08, 0x10, 0x08, 0x10,
[all …]
/kernel/linux/linux-4.19/arch/arm/boot/dts/
Dimx7-colibri.dtsi47 pinctrl-0 = <&pinctrl_gpio_bl_on>;
48 pwms = <&pwm1 0 5000000 0>;
97 pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>;
103 pinctrl-0 = <&pinctrl_enet1>;
112 assigned-clock-rates = <0>, <100000000>;
120 pinctrl-0 = <&pinctrl_gpmi_nand>;
129 pinctrl-0 = <&pinctrl_i2c1 &pinctrl_i2c1_int>;
134 #sound-dai-cells = <0>;
135 reg = <0x0a>;
138 pinctrl-0 = <&pinctrl_sai1_mclk>;
[all …]
Dimx6ull-colibri.dtsi17 pinctrl-0 = <&pinctrl_gpio_bl_on>;
42 pinctrl-0 = <&pinctrl_snvs_reg_sd>;
47 states = <1800000 0x1 3300000 0x0>;
61 pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
66 pinctrl-0 = <&pinctrl_enet2>;
73 #size-cells = <0>;
85 pinctrl-0 = <&pinctrl_gpmi_nand>;
95 pinctrl-0 = <&pinctrl_i2c1>;
103 pinctrl-0 = <&pinctrl_i2c2>;
112 pinctrl-0 = <&pinctrl_snvs_ad7879_int>;
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dimx7-colibri.dtsi10 pinctrl-0 = <&pinctrl_gpio_bl_on>;
11 pwms = <&pwm1 0 5000000 0>;
62 pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>;
68 pinctrl-0 = <&pinctrl_enet1>;
78 assigned-clock-rates = <0>, <100000000>;
86 pinctrl-0 = <&pinctrl_flexcan1>;
92 pinctrl-0 = <&pinctrl_flexcan2>;
276 pinctrl-0 = <&pinctrl_gpmi_nand>;
285 pinctrl-0 = <&pinctrl_i2c1 &pinctrl_i2c1_int>;
294 #sound-dai-cells = <0>;
[all …]
Drk3288-veyron-jerry.dts25 pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
45 #size-cells = <0>;
52 0x01 0x00 0x06 0x00 0x08 0x02 0x89 0x01
53 0x24 0x00 0x67 0x09 0x14 0x01 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
54 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
55 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x02 0x00 0x0f
56 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09
57 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01
58 0x24 0x00 0x67 0x09 0x14 0x03 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
59 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
[all …]
Dimx7d-pico-pi.dts14 pinctrl-0 = <&pinctrl_gpio_leds>;
41 #sound-dai-cells = <0>;
42 reg = <0x0a>;
53 reg = <0x38>;
55 pinctrl-0 = <&pinctrl_touchscreen>;
66 pinctrl-0 = <&pinctrl_hog>;
70 MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x14
71 MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x14
72 MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x14
73 MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x14
[all …]
Dimx7d-pico-hobbit.dts14 pinctrl-0 = <&pinctrl_gpio_leds>;
41 #sound-dai-cells = <0>;
42 reg = <0x0a>;
55 reg = <0x50>;
61 ads7846@0 {
62 reg = <0>;
65 interrupts = <7 0>;
67 pendown-gpio = <&gpio2 7 0>;
69 ti,x-min = /bits/ 16 <0>;
71 ti,y-min = /bits/ 16 <0>;
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/leds/
Dleds-lp55xx.txt12 - clock-mode: Input clock mode, (0: automode, 1: internal, 2: external)
15 - led-cur: Current setting at each led channel (mA x10, 0 if led is not connected)
22 0: D1~9 are connected to VDD
35 on channel 0.
39 reg = <0x32>;
44 led-cur = /bits/ 8 <0x2f>;
45 max-cur = /bits/ 8 <0x5f>;
50 led-cur = /bits/ 8 <0x2f>;
51 max-cur = /bits/ 8 <0x5f>;
55 led-cur = /bits/ 8 <0x2f>;
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddpcs_3_0_0_sh_mask.h7 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT 0x0
8 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT 0x1
9 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT 0x2
10 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_TX_CLK_LDPCS_CLOCK_ON__SHIFT 0x3
11 …_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK 0x00000001L
12 …_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK 0x00000002L
13 …_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK 0x00000004L
14 …_TX_CLOCK_CNTL__DPCS_TX_CLK_LDPCS_CLOCK_ON_MASK 0x00000008L
16 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT 0xc
17 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT 0xd
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/hdp/
Dhdp_4_0_sh_mask.h27 #define HDP_MMHUB_TLVL__HDP_WR_TLVL__SHIFT 0x0
28 #define HDP_MMHUB_TLVL__HDP_RD_TLVL__SHIFT 0x4
29 #define HDP_MMHUB_TLVL__XDP_WR_TLVL__SHIFT 0x8
30 #define HDP_MMHUB_TLVL__XDP_RD_TLVL__SHIFT 0xc
31 #define HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL__SHIFT 0x10
32 #define HDP_MMHUB_TLVL__HDP_WR_TLVL_MASK 0x00000007L
33 #define HDP_MMHUB_TLVL__HDP_RD_TLVL_MASK 0x00000070L
34 #define HDP_MMHUB_TLVL__XDP_WR_TLVL_MASK 0x00000700L
35 #define HDP_MMHUB_TLVL__XDP_RD_TLVL_MASK 0x00007000L
36 #define HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL_MASK 0x00070000L
[all …]
Dhdp_5_0_0_sh_mask.h27 …HUB_TLVL__HDP_WR_TLVL__SHIFT 0x0
28 …HUB_TLVL__HDP_RD_TLVL__SHIFT 0x4
29 …HUB_TLVL__XDP_WR_TLVL__SHIFT 0x8
30 …HUB_TLVL__XDP_RD_TLVL__SHIFT 0xc
31 …UB_TLVL__XDP_MBX_WR_TLVL__SHIFT 0x10
32 …__HDP_WR_TLVL_MASK 0x00000007L
33 …__HDP_RD_TLVL_MASK 0x00000070L
34 …__XDP_WR_TLVL_MASK 0x00000700L
35 …__XDP_RD_TLVL_MASK 0x00007000L
36 …__XDP_MBX_WR_TLVL_MASK 0x00070000L
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/amd/include/asic_reg/hdp/
Dhdp_4_0_sh_mask.h27 #define HDP_MMHUB_TLVL__HDP_WR_TLVL__SHIFT 0x0
28 #define HDP_MMHUB_TLVL__HDP_RD_TLVL__SHIFT 0x4
29 #define HDP_MMHUB_TLVL__XDP_WR_TLVL__SHIFT 0x8
30 #define HDP_MMHUB_TLVL__XDP_RD_TLVL__SHIFT 0xc
31 #define HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL__SHIFT 0x10
32 #define HDP_MMHUB_TLVL__HDP_WR_TLVL_MASK 0x00000007L
33 #define HDP_MMHUB_TLVL__HDP_RD_TLVL_MASK 0x00000070L
34 #define HDP_MMHUB_TLVL__XDP_WR_TLVL_MASK 0x00000700L
35 #define HDP_MMHUB_TLVL__XDP_RD_TLVL_MASK 0x00007000L
36 #define HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL_MASK 0x00070000L
[all …]
/kernel/linux/linux-5.10/arch/arm64/crypto/
Dpoly1305-core.S_shipped29 mov x9,#0xfffffffc0fffffff
30 movk x9,#0x0fff,lsl#48
35 and x7,x7,x9 // &=0ffffffc0fffffff
37 and x8,x8,x9 // &=0ffffffc0ffffffc
76 lsr x14,x5,#32
88 lsr x13,x14,#12
89 adds x12,x12,x14,lsl#52
92 lsr x14,x16,#24
94 adc x14,x14,xzr
96 cmp x17,#0 // is_base2_26?
[all …]
/kernel/linux/linux-4.19/drivers/staging/rtlwifi/halmac/
Dhalmac_tx_desc_nic.h20 SET_BITS_TO_LE_4BYTE(__tx_desc + 0x00, 31, 1, __value)
22 LE_BITS_TO_4BYTE(__tx_desc + 0x00, 31, 1)
25 SET_BITS_TO_LE_4BYTE(__tx_desc + 0x00, 30, 1, __value)
26 #define GET_TX_DESC_GF(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x00, 30, 1)
28 SET_BITS_TO_LE_4BYTE(__tx_desc + 0x00, 29, 1, __value)
29 #define GET_TX_DESC_NO_ACM(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x00, 29, 1)
32 SET_BITS_TO_LE_4BYTE(__tx_desc + 0x00, 28, 1, __value)
34 LE_BITS_TO_4BYTE(__tx_desc + 0x00, 28, 1)
37 SET_BITS_TO_LE_4BYTE(__tx_desc + 0x00, 27, 1, __value)
39 LE_BITS_TO_4BYTE(__tx_desc + 0x00, 27, 1)
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/dpcs/
Ddpcs_2_1_0_sh_mask.h27 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT 0x0
28 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT 0x1
29 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT 0x2
30 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT 0x3
31 …_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK 0x00000001L
32 …_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK 0x00000002L
33 …_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK 0x00000004L
34 …_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON_MASK 0x00000008L
36 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT 0xc
37 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT 0xd
[all …]
Ddpcs_2_0_0_sh_mask.h27 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT 0x0
28 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT 0x1
29 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT 0x2
30 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT 0x3
31 …_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK 0x00000001L
32 …_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK 0x00000002L
33 …_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK 0x00000004L
34 …_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON_MASK 0x00000008L
36 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT 0xc
37 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT 0xd
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/realtek/
Dr8169_phy_config.c23 int oldpage = phy_select_page(phydev, 0x0007); in r8168d_modify_extpage()
25 __phy_write(phydev, 0x1e, extpage); in r8168d_modify_extpage()
28 phy_restore_page(phydev, oldpage, 0); in r8168d_modify_extpage()
34 int oldpage = phy_select_page(phydev, 0x0005); in r8168d_phy_param()
36 __phy_write(phydev, 0x05, parm); in r8168d_phy_param()
37 __phy_modify(phydev, 0x06, mask, val); in r8168d_phy_param()
39 phy_restore_page(phydev, oldpage, 0); in r8168d_phy_param()
45 int oldpage = phy_select_page(phydev, 0x0a43); in r8168g_phy_param()
47 __phy_write(phydev, 0x13, parm); in r8168g_phy_param()
48 __phy_modify(phydev, 0x14, mask, val); in r8168g_phy_param()
[all …]
/kernel/linux/linux-5.10/arch/mips/alchemy/common/
Dsleeper.S46 sw k0, 0x20(sp)
48 sw k0, 0x1c(sp)
50 sw k0, 0x18(sp)
52 sw k0, 0x14(sp)
56 lw t0, 0(t1)
65 lui t3, 0xb190 /* sys_xxx */
66 sw sp, 0x0018(t3)
68 sw k0, 0x001c(t3)
73 sw zero, 0x0078(t3) /* sys_slppwr */
75 sw zero, 0x007c(t3) /* sys_sleep */
[all …]
/kernel/linux/linux-5.10/include/linux/regulator/
Dpca9450.h10 PCA9450_TYPE_PCA9450A = 0,
16 PCA9450_BUCK1 = 0,
31 PCA9450_DVS_LEVEL_RUN = 0,
36 #define PCA9450_BUCK1_VOLTAGE_NUM 0x80
37 #define PCA9450_BUCK2_VOLTAGE_NUM 0x80
38 #define PCA9450_BUCK3_VOLTAGE_NUM 0x80
39 #define PCA9450_BUCK4_VOLTAGE_NUM 0x80
41 #define PCA9450_BUCK5_VOLTAGE_NUM 0x80
42 #define PCA9450_BUCK6_VOLTAGE_NUM 0x80
44 #define PCA9450_LDO1_VOLTAGE_NUM 0x08
[all …]
/kernel/linux/linux-4.19/arch/mips/alchemy/common/
Dsleeper.S50 sw k0, 0x20(sp)
52 sw k0, 0x1c(sp)
54 sw k0, 0x18(sp)
56 sw k0, 0x14(sp)
60 lw t0, 0(t1)
69 lui t3, 0xb190 /* sys_xxx */
70 sw sp, 0x0018(t3)
72 sw k0, 0x001c(t3)
77 sw zero, 0x0078(t3) /* sys_slppwr */
79 sw zero, 0x007c(t3) /* sys_sleep */
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/leds/
Dleds-lp55xx.yaml42 - 0 # automode
56 - 0 # D1~9 are connected to VDD
65 const: 0
68 "(^led@[0-9a-f]$|led)":
75 Current setting at each LED channel (mA x10, 0 if LED is not connected)
76 minimum: 0
89 - 0 # LED output D1
115 #size-cells = <0>;
119 #size-cells = <0>;
121 reg = <0x32>;
[all …]
/kernel/linux/linux-5.10/drivers/clk/bcm/
Dclk-ns2.c43 .aon = AON_VAL(0x0, 1, 15, 12),
44 .reset = RESET_VAL(0x4, 2, 1),
45 .dig_filter = DF_VAL(0x0, 9, 3, 5, 4, 2, 3),
46 .ndiv_int = REG_VAL(0x8, 4, 10),
47 .pdiv = REG_VAL(0x8, 0, 4),
48 .vco_ctrl = VCO_CTRL_VAL(0x10, 0xc),
49 .status = REG_VAL(0x0, 27, 1),
56 * it to 0.
61 .enable = ENABLE_VAL(0x0, 18, 12, 0),
62 .mdiv = REG_VAL(0x18, 0, 8),
[all …]
/kernel/linux/linux-4.19/drivers/clk/bcm/
Dclk-ns2.c43 .aon = AON_VAL(0x0, 1, 15, 12),
44 .reset = RESET_VAL(0x4, 2, 1),
45 .dig_filter = DF_VAL(0x0, 9, 3, 5, 4, 2, 3),
46 .ndiv_int = REG_VAL(0x8, 4, 10),
47 .pdiv = REG_VAL(0x8, 0, 4),
48 .vco_ctrl = VCO_CTRL_VAL(0x10, 0xc),
49 .status = REG_VAL(0x0, 27, 1),
56 * it to 0.
61 .enable = ENABLE_VAL(0x0, 18, 12, 0),
62 .mdiv = REG_VAL(0x18, 0, 8),
[all …]
/kernel/linux/linux-4.19/arch/x86/kernel/
Dsignal_compat.c46 BUILD_BUG_ON(offsetof(siginfo_t, si_signo) != 0); in signal_compat_build_tests()
50 BUILD_BUG_ON(offsetof(compat_siginfo_t, si_signo) != 0); in signal_compat_build_tests()
66 #define CHECK_CSI_SIZE(name, size) BUILD_BUG_ON(size != sizeof(((compat_siginfo_t *)0)->_sifields.n… in signal_compat_build_tests()
67 #define CHECK_SI_SIZE(name, size) BUILD_BUG_ON(size != sizeof(((siginfo_t *)0)->_sifields.name)) in signal_compat_build_tests()
73 BUILD_BUG_ON(offsetof(siginfo_t, si_pid) != 0x10); in signal_compat_build_tests()
74 BUILD_BUG_ON(offsetof(siginfo_t, si_uid) != 0x14); in signal_compat_build_tests()
75 BUILD_BUG_ON(offsetof(compat_siginfo_t, si_pid) != 0xC); in signal_compat_build_tests()
76 BUILD_BUG_ON(offsetof(compat_siginfo_t, si_uid) != 0x10); in signal_compat_build_tests()
82 BUILD_BUG_ON(offsetof(siginfo_t, si_tid) != 0x10); in signal_compat_build_tests()
83 BUILD_BUG_ON(offsetof(siginfo_t, si_overrun) != 0x14); in signal_compat_build_tests()
[all …]

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