Home
last modified time | relevance | path

Searched +full:0 +full:x17000000 (Results 1 – 25 of 49) sorted by relevance

12

/kernel/linux/linux-5.10/Documentation/devicetree/bindings/gpu/
Dnvidia,gk20a.txt46 reg = <0x0 0x57000000 0x0 0x01000000>,
47 <0x0 0x58000000 0x0 0x01000000>;
64 reg = <0x0 0x57000000 0x0 0x01000000>,
65 <0x0 0x58000000 0x0 0x01000000>;
82 reg = <0x0 0x17000000 0x0 0x1000000>,
83 <0x0 0x18000000 0x0 0x1000000>;
100 reg = <0x17000000 0x10000000>,
101 <0x18000000 0x10000000>;
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/apm/
Dscu.txt16 reg = <0x0 0x17000000 0x0 0x400>;
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/apm/
Dscu.txt16 reg = <0x0 0x17000000 0x0 0x400>;
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/mediatek/
Dmediatek,vcodecsys.txt24 reg = <0 0x17000000 0 0x10000>;
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/memory-controllers/
Dingenic,jz4780-nemc.txt16 <cs number> 0 <physical address of mapping> <size of mapping>
49 reg = <0x13410000 0x10000>;
54 ranges = <1 0 0x1b000000 0x1000000
55 2 0 0x1a000000 0x1000000
56 3 0 0x19000000 0x1000000
57 4 0 0x18000000 0x1000000
58 5 0 0x17000000 0x1000000
59 6 0 0x16000000 0x1000000>;
65 reg = <1 0 0x1000000>;
/kernel/linux/linux-5.10/arch/mips/include/asm/netlogic/xlr/
Diomap.h38 #define DEFAULT_NETLOGIC_IO_BASE CKSEG1ADDR(0x1ef00000)
39 #define NETLOGIC_IO_DDR2_CHN0_OFFSET 0x01000
40 #define NETLOGIC_IO_DDR2_CHN1_OFFSET 0x02000
41 #define NETLOGIC_IO_DDR2_CHN2_OFFSET 0x03000
42 #define NETLOGIC_IO_DDR2_CHN3_OFFSET 0x04000
43 #define NETLOGIC_IO_PIC_OFFSET 0x08000
44 #define NETLOGIC_IO_UART_0_OFFSET 0x14000
45 #define NETLOGIC_IO_UART_1_OFFSET 0x15100
47 #define NETLOGIC_IO_SIZE 0x1000
49 #define NETLOGIC_IO_BRIDGE_OFFSET 0x00000
[all …]
/kernel/linux/linux-4.19/arch/mips/include/asm/netlogic/xlr/
Diomap.h38 #define DEFAULT_NETLOGIC_IO_BASE CKSEG1ADDR(0x1ef00000)
39 #define NETLOGIC_IO_DDR2_CHN0_OFFSET 0x01000
40 #define NETLOGIC_IO_DDR2_CHN1_OFFSET 0x02000
41 #define NETLOGIC_IO_DDR2_CHN2_OFFSET 0x03000
42 #define NETLOGIC_IO_DDR2_CHN3_OFFSET 0x04000
43 #define NETLOGIC_IO_PIC_OFFSET 0x08000
44 #define NETLOGIC_IO_UART_0_OFFSET 0x14000
45 #define NETLOGIC_IO_UART_1_OFFSET 0x15100
47 #define NETLOGIC_IO_SIZE 0x1000
49 #define NETLOGIC_IO_BRIDGE_OFFSET 0x00000
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/gpu/
Dnvidia,gk20a.txt42 reg = <0x0 0x57000000 0x0 0x01000000>,
43 <0x0 0x58000000 0x0 0x01000000>;
60 reg = <0x0 0x57000000 0x0 0x01000000>,
61 <0x0 0x58000000 0x0 0x01000000>;
78 reg = <0x0 0x17000000 0x0 0x1000000>,
79 <0x0 0x18000000 0x0 0x1000000>;
/kernel/linux/linux-4.19/arch/arm64/boot/dts/apm/
Dapm-storm.dtsi20 #size-cells = <0>;
22 cpu@0 {
25 reg = <0x0 0x000>;
27 cpu-release-addr = <0x1 0x0000fff8>;
33 reg = <0x0 0x001>;
35 cpu-release-addr = <0x1 0x0000fff8>;
41 reg = <0x0 0x100>;
43 cpu-release-addr = <0x1 0x0000fff8>;
49 reg = <0x0 0x101>;
51 cpu-release-addr = <0x1 0x0000fff8>;
[all …]
Dapm-shadowcat.dtsi20 #size-cells = <0>;
22 cpu@0 {
25 reg = <0x0 0x000>;
27 cpu-release-addr = <0x1 0x0000fff8>;
30 clocks = <&pmd0clk 0>;
35 reg = <0x0 0x001>;
37 cpu-release-addr = <0x1 0x0000fff8>;
40 clocks = <&pmd0clk 0>;
45 reg = <0x0 0x100>;
47 cpu-release-addr = <0x1 0x0000fff8>;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/apm/
Dapm-storm.dtsi16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0x0 0x000>;
23 cpu-release-addr = <0x1 0x0000fff8>;
29 reg = <0x0 0x001>;
31 cpu-release-addr = <0x1 0x0000fff8>;
37 reg = <0x0 0x100>;
39 cpu-release-addr = <0x1 0x0000fff8>;
45 reg = <0x0 0x101>;
47 cpu-release-addr = <0x1 0x0000fff8>;
[all …]
Dapm-shadowcat.dtsi16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0x0 0x000>;
23 cpu-release-addr = <0x1 0x0000fff8>;
26 clocks = <&pmd0clk 0>;
31 reg = <0x0 0x001>;
33 cpu-release-addr = <0x1 0x0000fff8>;
36 clocks = <&pmd0clk 0>;
41 reg = <0x0 0x100>;
43 cpu-release-addr = <0x1 0x0000fff8>;
[all …]
/kernel/linux/linux-4.19/arch/arm/boot/dts/
Dintegrator.dtsi11 reg = <0x10000000 0x200>;
14 led@c.0 {
16 offset = <0x0c>;
17 mask = <0x01>;
26 reg = <0x12000000 0x100>;
30 reg = <0x13000000 0x100>;
36 reg = <0x13000100 0x100>;
42 reg = <0x13000200 0x100>;
51 reg = <0x14000000 0x100>;
52 clear-mask = <0xffffffff>;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/
Dingenic,nemc.yaml14 pattern: "^memory-controller@[0-9a-f]+$"
40 ".*@[0-9]+$":
91 reg = <0x13410000 0x10000>;
94 ranges = <1 0 0x1b000000 0x1000000>,
95 <2 0 0x1a000000 0x1000000>,
96 <3 0 0x19000000 0x1000000>,
97 <4 0 0x18000000 0x1000000>,
98 <5 0 0x17000000 0x1000000>,
99 <6 0 0x16000000 0x1000000>;
108 pinctrl-0 = <&pins_nemc_cs6>;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mtd/
Dingenic,nand.yaml61 reg = <0x13410000 0x10000>;
64 ranges = <1 0 0x1b000000 0x1000000>,
65 <2 0 0x1a000000 0x1000000>,
66 <3 0 0x19000000 0x1000000>,
67 <4 0 0x18000000 0x1000000>,
68 <5 0 0x17000000 0x1000000>,
69 <6 0 0x16000000 0x1000000>;
75 reg = <1 0 0x1000000>;
78 #size-cells = <0>;
89 pinctrl-0 = <&pins_nemc>;
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dintegrator.dtsi12 reg = <0x0 0x0>;
17 reg = <0x10000000 0x200>;
20 led@c.0 {
22 offset = <0x0c>;
23 mask = <0x01>;
32 reg = <0x12000000 0x100>;
36 reg = <0x13000000 0x100>;
42 reg = <0x13000100 0x100>;
48 reg = <0x13000200 0x100>;
57 reg = <0x14000000 0x100>;
[all …]
/kernel/linux/linux-4.19/arch/sh/boards/mach-se/7343/
Dsetup.c32 .offset = 0x00000000,
54 [0] = {
55 .start = 0x00000000,
56 .end = 0x01ffffff,
73 [0] = {
75 .mapbase = 0x16000000,
82 .mapbase = 0x17000000,
104 [0] = {
105 .start = 0x11800000,
106 .end = 0x11800001,
[all …]
/kernel/linux/linux-5.10/arch/sh/boards/mach-se/7343/
Dsetup.c32 .offset = 0x00000000,
54 [0] = {
55 .start = 0x00000000,
56 .end = 0x01ffffff,
73 [0] = {
75 .mapbase = 0x16000000,
82 .mapbase = 0x17000000,
104 [0] = {
105 .start = 0x11800000,
106 .end = 0x11800001,
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/clock/
Dxgene.txt50 Default is 0.
51 - csr-mask : CSR reset mask bit. Default is 0xF.
53 Default is 0x8.
54 - enable-mask : CSR enable mask bit. Default is 0xF.
56 Default is 0x0.
57 - divider-width : Width of the divider register. Default is 0.
58 - divider-shift : Bit shift of the divider register. Default is 0.
65 clocks = <&refclk 0>;
67 reg = <0x0 0x17000100 0x0 0x1000>;
69 type = <0>;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dxgene.txt50 Default is 0.
51 - csr-mask : CSR reset mask bit. Default is 0xF.
53 Default is 0x8.
54 - enable-mask : CSR enable mask bit. Default is 0xF.
56 Default is 0x0.
57 - divider-width : Width of the divider register. Default is 0.
58 - divider-shift : Bit shift of the divider register. Default is 0.
65 clocks = <&refclk 0>;
67 reg = <0x0 0x17000100 0x0 0x1000>;
69 type = <0>;
[all …]
/kernel/linux/linux-4.19/arch/arm64/boot/dts/mediatek/
Dmt6797.dtsi31 #size-cells = <0>;
33 cpu0: cpu@0 {
37 reg = <0x000>;
44 reg = <0x001>;
51 reg = <0x002>;
58 reg = <0x003>;
65 reg = <0x100>;
72 reg = <0x101>;
79 reg = <0x102>;
86 reg = <0x103>;
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-integrator/
Dhardware.h14 #define IO_BASE 0xF0000000 // VA of IO
15 #define IO_SIZE 0x0B000000 // How much?
20 #define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE)
30 #define INTEGRATOR_BOOT_ROM_LO 0x00000000
31 #define INTEGRATOR_BOOT_ROM_HI 0x20000000
45 #define INTEGRATOR_SSRAM_BASE 0x00000000
46 #define INTEGRATOR_SSRAM_ALIAS_BASE 0x10800000
49 #define INTEGRATOR_FLASH_BASE 0x24000000
52 #define INTEGRATOR_MBRD_SSRAM_BASE 0x28000000
58 #define INTEGRATOR_SDRAM_BASE 0x00040000
[all …]
/kernel/linux/linux-4.19/arch/mips/boot/dts/ingenic/
Djz4780.dtsi11 #address-cells = <0>;
19 reg = <0x10001000 0x50>;
30 #clock-cells = <0>;
35 #clock-cells = <0>;
41 reg = <0x10000000 0x100>;
51 reg = <0x10003000 0x4c>;
62 reg = <0x10010000 0x600>;
65 #size-cells = <0>;
67 gpa: gpio@0 {
69 reg = <0>;
[all …]
/kernel/linux/linux-4.19/arch/arm/mach-integrator/
Dhardware.h27 #define IO_BASE 0xF0000000 // VA of IO
28 #define IO_SIZE 0x0B000000 // How much?
33 #define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE)
43 #define INTEGRATOR_BOOT_ROM_LO 0x00000000
44 #define INTEGRATOR_BOOT_ROM_HI 0x20000000
58 #define INTEGRATOR_SSRAM_BASE 0x00000000
59 #define INTEGRATOR_SSRAM_ALIAS_BASE 0x10800000
62 #define INTEGRATOR_FLASH_BASE 0x24000000
65 #define INTEGRATOR_MBRD_SSRAM_BASE 0x28000000
71 #define INTEGRATOR_SDRAM_BASE 0x00040000
[all …]
/kernel/linux/linux-4.19/fs/freevxfs/
Dvxfs.h45 #define VXFS_SUPER_MAGIC 0xa501FCF5
201 * File modes. File types above 0xf000 are vxfs internal only, they should
206 VXFS_ISUID = 0x00000800, /* setuid */
207 VXFS_ISGID = 0x00000400, /* setgid */
208 VXFS_ISVTX = 0x00000200, /* sticky bit */
209 VXFS_IREAD = 0x00000100, /* read */
210 VXFS_IWRITE = 0x00000080, /* write */
211 VXFS_IEXEC = 0x00000040, /* exec */
213 VXFS_IFIFO = 0x00001000, /* Named pipe */
214 VXFS_IFCHR = 0x00002000, /* Character device */
[all …]

12