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/kernel/linux/linux-4.19/arch/arm/boot/dts/
Dimx53-ppd.dts63 reg = <0x70000000 0x20000000>,
64 <0xb0000000 0x20000000>;
69 #clock-cells = <0>;
100 pinctrl-0 = <&pinctrl_usb_otg_vbus>;
119 pinctrl-0 = <&pinctrl_usbh2_vbus>;
130 pinctrl-0 = <&pinctrl_usbh3_vbus>;
164 pwms = <&pwm2 0 50000>;
165 brightness-levels = <0 2 5 7 10 12 15 17 20 22 25 28 30 33 35
174 default-brightness-level = <0>;
183 pwms = <&pwm1 0 100000>;
[all …]
Dimx53-cx9020.dts26 reg = <0x70000000 0x20000000>,
27 <0xb0000000 0x20000000>;
30 display-0 {
32 #size-cells = <0>;
36 pinctrl-0 = <&pinctrl_ipu_disp0>;
38 port@0 {
39 reg = <0>;
69 #size-cells = <0>;
72 port@0 {
73 reg = <0>;
[all …]
Dimx53-qsb-common.dtsi15 reg = <0x70000000 0x20000000>,
16 <0xb0000000 0x20000000>;
23 pinctrl-0 = <&pinctrl_ipu_disp0>;
37 hsync-active = <0>;
38 vsync-active = <0>;
40 pixelclk-active = <0>;
78 pinctrl-0 = <&led_pin_gpio7_7>;
82 gpios = <&gpio7 7 0>;
90 #size-cells = <0>;
92 reg_3p2v: regulator@0 {
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dimx53-ppd.dts63 reg = <0x70000000 0x20000000>,
64 <0xb0000000 0x20000000>;
69 #clock-cells = <0>;
75 #clock-cells = <0>;
106 pinctrl-0 = <&pinctrl_usb_otg_vbus>;
125 pinctrl-0 = <&pinctrl_usbh2_vbus>;
136 pinctrl-0 = <&pinctrl_usbh3_vbus>;
170 pwms = <&pwm2 0 50000>;
171 brightness-levels = <0 2 5 7 10 12 15 17 20 22 25 28 30 33 35
180 default-brightness-level = <0>;
[all …]
Dimx53-cx9020.dts20 reg = <0x70000000 0x20000000>,
21 <0xb0000000 0x20000000>;
24 display-0 {
26 #size-cells = <0>;
30 pinctrl-0 = <&pinctrl_ipu_disp0>;
32 port@0 {
33 reg = <0>;
66 #size-cells = <0>;
68 port@0 {
69 reg = <0>;
[all …]
Dimx53-qsb-common.dtsi15 reg = <0x70000000 0x20000000>,
16 <0xb0000000 0x20000000>;
22 pinctrl-0 = <&pinctrl_ipu_disp0>;
25 #size-cells = <0>;
28 port@0 {
29 reg = <0>;
72 pinctrl-0 = <&led_pin_gpio7_7>;
76 gpios = <&gpio7 7 0>;
94 #size-cells = <0>;
96 reg_3p2v: regulator@0 {
[all …]
/kernel/linux/linux-4.19/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x_dump.h22 #define DRV_DUMP_XSTORM_WAITP_ADDRESS 0x2b8a80
23 #define DRV_DUMP_TSTORM_WAITP_ADDRESS 0x1b8a80
24 #define DRV_DUMP_USTORM_WAITP_ADDRESS 0x338a80
25 #define DRV_DUMP_CSTORM_WAITP_ADDRESS 0x238a80
45 #define BNX2X_DUMP_VERSION 0x61111111
65 static const u32 page_vals_e2[] = {0, 128};
68 {0x58000, 4608, DUMP_CHIP_E2, 0x30}
74 static const u32 page_vals_e3[] = {0, 128};
77 {0x58000, 4608, DUMP_CHIP_E3A0 | DUMP_CHIP_E3B0, 0x30}
81 { 0x2000, 1, 0x1f, 0xfff},
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x_dump.h22 #define DRV_DUMP_XSTORM_WAITP_ADDRESS 0x2b8a80
23 #define DRV_DUMP_TSTORM_WAITP_ADDRESS 0x1b8a80
24 #define DRV_DUMP_USTORM_WAITP_ADDRESS 0x338a80
25 #define DRV_DUMP_CSTORM_WAITP_ADDRESS 0x238a80
45 #define BNX2X_DUMP_VERSION 0x61111111
65 static const u32 page_vals_e2[] = {0, 128};
68 {0x58000, 4608, DUMP_CHIP_E2, 0x30}
74 static const u32 page_vals_e3[] = {0, 128};
77 {0x58000, 4608, DUMP_CHIP_E3A0 | DUMP_CHIP_E3B0, 0x30}
81 { 0x2000, 1, 0x1f, 0xfff},
[all …]
/kernel/linux/linux-4.19/drivers/media/platform/coda/
Dcoda_regs.h18 #define CODA_REG_BIT_CODE_RUN 0x000
19 #define CODA_REG_RUN_ENABLE (1 << 0)
20 #define CODA_REG_BIT_CODE_DOWN 0x004
21 #define CODA_DOWN_ADDRESS_SET(x) (((x) & 0xffff) << 16)
22 #define CODA_DOWN_DATA_SET(x) ((x) & 0xffff)
23 #define CODA_REG_BIT_HOST_IN_REQ 0x008
24 #define CODA_REG_BIT_INT_CLEAR 0x00c
25 #define CODA_REG_BIT_INT_CLEAR_SET 0x1
26 #define CODA_REG_BIT_INT_STATUS 0x010
27 #define CODA_REG_BIT_CODE_RESET 0x014
[all …]
/kernel/linux/linux-5.10/drivers/media/platform/coda/
Dcoda_regs.h14 #define CODA_REG_BIT_CODE_RUN 0x000
15 #define CODA_REG_RUN_ENABLE (1 << 0)
16 #define CODA_REG_BIT_CODE_DOWN 0x004
17 #define CODA_DOWN_ADDRESS_SET(x) (((x) & 0xffff) << 16)
18 #define CODA_DOWN_DATA_SET(x) ((x) & 0xffff)
19 #define CODA_REG_BIT_HOST_IN_REQ 0x008
20 #define CODA_REG_BIT_INT_CLEAR 0x00c
21 #define CODA_REG_BIT_INT_CLEAR_SET 0x1
22 #define CODA_REG_BIT_INT_STATUS 0x010
23 #define CODA_REG_BIT_CODE_RESET 0x014
[all …]
/kernel/linux/linux-5.10/sound/pci/oxygen/
Dwm8766.h5 #define WM8766_LDA1 0x00
6 #define WM8766_RDA1 0x01
7 #define WM8766_DAC_CTRL 0x02
8 #define WM8766_INT_CTRL 0x03
9 #define WM8766_LDA2 0x04
10 #define WM8766_RDA2 0x05
11 #define WM8766_LDA3 0x06
12 #define WM8766_RDA3 0x07
13 #define WM8766_MASTDA 0x08
14 #define WM8766_DAC_CTRL2 0x09
[all …]
Dwm8776.h14 #define WM8776_HPLVOL 0x00
15 #define WM8776_HPRVOL 0x01
16 #define WM8776_HPMASTER 0x02
17 #define WM8776_DACLVOL 0x03
18 #define WM8776_DACRVOL 0x04
19 #define WM8776_DACMASTER 0x05
20 #define WM8776_PHASESWAP 0x06
21 #define WM8776_DACCTRL1 0x07
22 #define WM8776_DACMUTE 0x08
23 #define WM8776_DACCTRL2 0x09
[all …]
/kernel/linux/linux-4.19/sound/pci/oxygen/
Dwm8766.h5 #define WM8766_LDA1 0x00
6 #define WM8766_RDA1 0x01
7 #define WM8766_DAC_CTRL 0x02
8 #define WM8766_INT_CTRL 0x03
9 #define WM8766_LDA2 0x04
10 #define WM8766_RDA2 0x05
11 #define WM8766_LDA3 0x06
12 #define WM8766_RDA3 0x07
13 #define WM8766_MASTDA 0x08
14 #define WM8766_DAC_CTRL2 0x09
[all …]
/kernel/linux/linux-5.10/drivers/clk/renesas/
Dr8a774a1-cpg-mssr.c75 DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
96 DEF_GEN3_SD("sd0", R8A774A1_CLK_SD0, CLK_SDSRC, 0x074),
97 DEF_GEN3_SD("sd1", R8A774A1_CLK_SD1, CLK_SDSRC, 0x078),
98 DEF_GEN3_SD("sd2", R8A774A1_CLK_SD2, CLK_SDSRC, 0x268),
99 DEF_GEN3_SD("sd3", R8A774A1_CLK_SD3, CLK_SDSRC, 0x26c),
105 DEF_DIV6P1("canfd", R8A774A1_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
106 DEF_DIV6P1("csi0", R8A774A1_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
107 DEF_DIV6P1("mso", R8A774A1_CLK_MSO, CLK_PLL1_DIV4, 0x014),
108 DEF_DIV6P1("hdmi", R8A774A1_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
121 DEF_MOD("fdp1-0", 119, R8A774A1_CLK_S0D1),
[all …]
Dr8a77965-cpg-mssr.c104 DEF_GEN3_SD("sd0", R8A77965_CLK_SD0, CLK_SDSRC, 0x074),
105 DEF_GEN3_SD("sd1", R8A77965_CLK_SD1, CLK_SDSRC, 0x078),
106 DEF_GEN3_SD("sd2", R8A77965_CLK_SD2, CLK_SDSRC, 0x268),
107 DEF_GEN3_SD("sd3", R8A77965_CLK_SD3, CLK_SDSRC, 0x26c),
114 DEF_DIV6P1("canfd", R8A77965_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
115 DEF_DIV6P1("csi0", R8A77965_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
116 DEF_DIV6P1("mso", R8A77965_CLK_MSO, CLK_PLL1_DIV4, 0x014),
117 DEF_DIV6P1("hdmi", R8A77965_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
125 DEF_MOD("fdp1-0", 119, R8A77965_CLK_S0D1),
278 * 0 0 0 0 16.66 x 1 x180 x192 x192 x144 /16
[all …]
Dr8a774b1-cpg-mssr.c93 DEF_GEN3_SD("sd0", R8A774B1_CLK_SD0, CLK_SDSRC, 0x074),
94 DEF_GEN3_SD("sd1", R8A774B1_CLK_SD1, CLK_SDSRC, 0x078),
95 DEF_GEN3_SD("sd2", R8A774B1_CLK_SD2, CLK_SDSRC, 0x268),
96 DEF_GEN3_SD("sd3", R8A774B1_CLK_SD3, CLK_SDSRC, 0x26c),
102 DEF_DIV6P1("canfd", R8A774B1_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
103 DEF_DIV6P1("csi0", R8A774B1_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
104 DEF_DIV6P1("mso", R8A774B1_CLK_MSO, CLK_PLL1_DIV4, 0x014),
105 DEF_DIV6P1("hdmi", R8A774B1_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
118 DEF_MOD("fdp1-0", 119, R8A774B1_CLK_S0D1),
248 * 0 0 0 0 16.66 x 1 x180 x192 x192 x144 /16
[all …]
Dr8a7796-cpg-mssr.c87 DEF_GEN3_Z("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
109 DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, CLK_SDSRC, 0x074),
110 DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, CLK_SDSRC, 0x078),
111 DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, CLK_SDSRC, 0x268),
112 DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, CLK_SDSRC, 0x26c),
119 DEF_DIV6P1("canfd", R8A7796_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
120 DEF_DIV6P1("csi0", R8A7796_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
121 DEF_DIV6P1("mso", R8A7796_CLK_MSO, CLK_PLL1_DIV4, 0x014),
122 DEF_DIV6P1("hdmi", R8A7796_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
130 DEF_MOD("fdp1-0", 119, R8A7796_CLK_S0D1),
[all …]
Dr8a774e1-cpg-mssr.c82 DEF_GEN3_Z("z2", R8A774E1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
103 DEF_GEN3_SD("sd0", R8A774E1_CLK_SD0, CLK_SDSRC, 0x074),
104 DEF_GEN3_SD("sd1", R8A774E1_CLK_SD1, CLK_SDSRC, 0x078),
105 DEF_GEN3_SD("sd2", R8A774E1_CLK_SD2, CLK_SDSRC, 0x268),
106 DEF_GEN3_SD("sd3", R8A774E1_CLK_SD3, CLK_SDSRC, 0x26c),
113 DEF_DIV6P1("canfd", R8A774E1_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
114 DEF_DIV6P1("csi0", R8A774E1_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
115 DEF_DIV6P1("mso", R8A774E1_CLK_MSO, CLK_PLL1_DIV4, 0x014),
116 DEF_DIV6P1("hdmi", R8A774E1_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
125 DEF_MOD("fdp1-0", 119, R8A774E1_CLK_S0D1),
[all …]
/kernel/linux/linux-4.19/drivers/clk/renesas/
Dr8a7796-cpg-mssr.c100 DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, CLK_SDSRC, 0x074),
101 DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, CLK_SDSRC, 0x078),
102 DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, CLK_SDSRC, 0x268),
103 DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, CLK_SDSRC, 0x26c),
108 DEF_DIV6P1("canfd", R8A7796_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
109 DEF_DIV6P1("csi0", R8A7796_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
110 DEF_DIV6P1("mso", R8A7796_CLK_MSO, CLK_PLL1_DIV4, 0x014),
111 DEF_DIV6P1("hdmi", R8A7796_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
120 DEF_MOD("fdp1-0", 119, R8A7796_CLK_S0D1),
261 * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144
[all …]
Dr8a77965-cpg-mssr.c94 DEF_GEN3_SD("sd0", R8A77965_CLK_SD0, CLK_SDSRC, 0x074),
95 DEF_GEN3_SD("sd1", R8A77965_CLK_SD1, CLK_SDSRC, 0x078),
96 DEF_GEN3_SD("sd2", R8A77965_CLK_SD2, CLK_SDSRC, 0x268),
97 DEF_GEN3_SD("sd3", R8A77965_CLK_SD3, CLK_SDSRC, 0x26c),
102 DEF_DIV6P1("canfd", R8A77965_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
103 DEF_DIV6P1("csi0", R8A77965_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
104 DEF_DIV6P1("mso", R8A77965_CLK_MSO, CLK_PLL1_DIV4, 0x014),
105 DEF_DIV6P1("hdmi", R8A77965_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
258 * 0 0 0 0 16.66 x 1 x180 x192 x192 x144
259 * 0 0 0 1 16.66 x 1 x180 x192 x128 x144
[all …]
/kernel/linux/linux-4.19/arch/m68k/include/asm/
Dm525xsim.h30 #define MCF_MBAR2 0x80000000
35 #define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */
36 #define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
37 #define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */
38 #define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog srv */
39 #define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
40 #define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pending */
41 #define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */
42 #define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */
43 #define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
[all …]
/kernel/linux/linux-5.10/arch/m68k/include/asm/
Dm525xsim.h30 #define MCF_MBAR2 0x80000000
35 #define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */
36 #define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
37 #define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */
38 #define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog srv */
39 #define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
40 #define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pending */
41 #define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */
42 #define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */
43 #define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
[all …]
/kernel/linux/linux-5.10/sound/soc/codecs/
Dwm8770.c37 { 0, 0x7f },
38 { 1, 0x7f },
39 { 2, 0x7f },
40 { 3, 0x7f },
41 { 4, 0x7f },
42 { 5, 0x7f },
43 { 6, 0x7f },
44 { 7, 0x7f },
45 { 8, 0x7f },
46 { 9, 0xff },
[all …]
/kernel/linux/linux-5.10/drivers/pinctrl/samsung/
Dpinctrl-exynos-arm.c27 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
32 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
36 #define S5P_OTHERS 0xE000
73 clk_base = of_iomap(np, 0); in s5pv210_retention_init()
93 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
94 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04),
95 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
96 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
97 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
98 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
[all …]
/kernel/linux/linux-4.19/drivers/pinctrl/samsung/
Dpinctrl-exynos-arm.c27 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
32 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
36 #define S5P_OTHERS 0xE000
73 clk_base = of_iomap(np, 0); in s5pv210_retention_init()
93 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
94 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04),
95 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
96 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
97 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
98 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
[all …]

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