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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/
Dversatile.yaml38 - const: 0x1800
39 - const: 0
40 - const: 0
58 reg = <0x10001000 0x1000>,
59 <0x41000000 0x10000>,
60 <0x42000000 0x100000>;
61 bus-range = <0 0xff>;
67 <0x01000000 0 0x00000000 0x43000000 0 0x00010000>, /* downstream I/O */
68 <0x02000000 0 0x50000000 0x50000000 0 0x10000000>, /* non-prefetchable memory */
69 <0x42000000 0 0x60000000 0x60000000 0 0x10000000>; /* prefetchable memory */
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/pci/
Dversatile.txt16 - bus-range: set to <0 0xff>
27 reg = <0x10001000 0x1000
28 0x41000000 0x10000
29 0x42000000 0x100000>;
30 bus-range = <0 0xff>;
35 ranges = <0x01000000 0 0x00000000 0x43000000 0 0x00010000 /* downstream I/O */
36 0x02000000 0 0x50000000 0x50000000 0 0x10000000 /* non-prefetchable memory */
37 0x42000000 0 0x60000000 0x60000000 0 0x10000000>; /* prefetchable memory */
39 interrupt-map-mask = <0x1800 0 0 7>;
40 interrupt-map = <0x1800 0 0 1 &sic 28
[all …]
/kernel/linux/linux-4.19/arch/arm/boot/dts/
Dversatile-pb.dts11 clear-mask = <0xffffffff>;
16 valid-mask = <0x7fe003ff>;
21 reg = <0x101e6000 0x1000>;
33 reg = <0x101e7000 0x1000>;
46 reg = <0x10001000 0x1000
47 0x41000000 0x10000
48 0x42000000 0x100000>;
49 bus-range = <0 0xff>;
54 ranges = <0x01000000 0 0x00000000 0x43000000 0 0x00010000 /* downstream I/O */
55 0x02000000 0 0x50000000 0x50000000 0 0x10000000 /* non-prefetchable memory */
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dversatile-pb.dts11 clear-mask = <0xffffffff>;
16 valid-mask = <0x7fe003ff>;
21 reg = <0x101e6000 0x1000>;
33 reg = <0x101e7000 0x1000>;
46 reg = <0x10001000 0x1000
47 0x41000000 0x10000
48 0x42000000 0x100000>;
49 bus-range = <0 0xff>;
54 ranges = <0x01000000 0 0x00000000 0x43000000 0 0x00010000 /* downstream I/O */
55 0x02000000 0 0x50000000 0x50000000 0 0x10000000 /* non-prefetchable memory */
[all …]
Dibm-power9-dual.dtsi5 cfam@0,0 {
6 reg = <0 0>;
9 chip-id = <0>;
13 reg = <0x1000 0x400>;
18 reg = <0x1800 0x400>;
20 #size-cells = <0>;
22 cfam0_i2c0: i2c-bus@0 {
23 reg = <0>;
85 reg = <0x2400 0x400>;
87 #size-cells = <0>;
[all …]
/kernel/linux/linux-5.10/arch/powerpc/boot/dts/
Dmpc7448hpc2.dts29 #size-cells =<0>;
31 PowerPC,7448@0 {
33 reg = <0x0>;
36 d-cache-size = <0x8000>; // L1, 32K bytes
37 i-cache-size = <0x8000>; // L1, 32K bytes
38 timebase-frequency = <0>; // 33 MHz, from uboot
39 clock-frequency = <0>; // From U-Boot
40 bus-frequency = <0>; // From U-Boot
46 reg = <0x0 0x20000000 // DDR2 512M at 0
54 ranges = <0x0 0xc0000000 0x10000>;
[all …]
Dholly.dts23 #size-cells =<0>;
24 PowerPC,750CL@0 {
26 reg = <0x00000000>;
39 memory@0 {
41 reg = <0x00000000 0x20000000>;
49 ranges = <0x00000000 0xc0000000 0x00010000>;
50 reg = <0xc0000000 0x00010000>;
56 interrupts = <0xe 0x2>;
57 reg = <0x00007000 0x00000400>;
62 reg = <0x00006000 0x00000050>;
[all …]
/kernel/linux/linux-4.19/arch/powerpc/boot/dts/
Dmpc7448hpc2.dts33 #size-cells =<0>;
35 PowerPC,7448@0 {
37 reg = <0x0>;
40 d-cache-size = <0x8000>; // L1, 32K bytes
41 i-cache-size = <0x8000>; // L1, 32K bytes
42 timebase-frequency = <0>; // 33 MHz, from uboot
43 clock-frequency = <0>; // From U-Boot
44 bus-frequency = <0>; // From U-Boot
50 reg = <0x0 0x20000000 // DDR2 512M at 0
58 ranges = <0x0 0xc0000000 0x10000>;
[all …]
Dholly.dts23 #size-cells =<0>;
24 PowerPC,750CL@0 {
26 reg = <0x00000000>;
39 memory@0 {
41 reg = <0x00000000 0x20000000>;
49 ranges = <0x00000000 0xc0000000 0x00010000>;
50 reg = <0xc0000000 0x00010000>;
56 interrupts = <0xe 0x2>;
57 reg = <0x00007000 0x00000400>;
62 reg = <0x00006000 0x00000050>;
[all …]
/kernel/linux/linux-5.10/drivers/bus/
Domap_l3_smx.h14 #define L3_COMPONENT 0x000
15 #define L3_CORE 0x018
16 #define L3_AGENT_CONTROL 0x020
17 #define L3_AGENT_STATUS 0x028
18 #define L3_ERROR_LOG 0x058
23 #define L3_ERROR_LOG_ADDR 0x060
26 #define L3_SI_CONTROL 0x020
27 #define L3_SI_FLAG_STATUS_0 0x510
31 #define L3_STATUS_0_MPUIA_BRST (shift << 0)
95 #define L3_SI_FLAG_STATUS_1 0x530
[all …]
/kernel/linux/linux-4.19/drivers/bus/
Domap_l3_smx.h28 #define L3_COMPONENT 0x000
29 #define L3_CORE 0x018
30 #define L3_AGENT_CONTROL 0x020
31 #define L3_AGENT_STATUS 0x028
32 #define L3_ERROR_LOG 0x058
37 #define L3_ERROR_LOG_ADDR 0x060
40 #define L3_SI_CONTROL 0x020
41 #define L3_SI_FLAG_STATUS_0 0x510
45 #define L3_STATUS_0_MPUIA_BRST (shift << 0)
109 #define L3_SI_FLAG_STATUS_1 0x530
[all …]
/kernel/linux/linux-5.10/arch/xtensa/boot/dts/
Dvirt.dts14 memory@0 {
16 reg = <0x00000000 0x80000000>;
21 #size-cells = <0>;
22 cpu@0 {
24 reg = <0>;
31 #clock-cells = <0>;
40 * two cells: second cell == 0: internal irq number
43 #address-cells = <0>;
53 #interrupt-cells = <0x1>;
55 bus-range = <0x0 0x3e>;
[all …]
/kernel/linux/linux-4.19/include/linux/mfd/wm831x/
Dregulator.h19 * R16462 (0x404E) - Current Sink 1
21 #define WM831X_CS1_ENA 0x8000 /* CS1_ENA */
22 #define WM831X_CS1_ENA_MASK 0x8000 /* CS1_ENA */
25 #define WM831X_CS1_DRIVE 0x4000 /* CS1_DRIVE */
26 #define WM831X_CS1_DRIVE_MASK 0x4000 /* CS1_DRIVE */
29 #define WM831X_CS1_SLPENA 0x1000 /* CS1_SLPENA */
30 #define WM831X_CS1_SLPENA_MASK 0x1000 /* CS1_SLPENA */
33 #define WM831X_CS1_OFF_RAMP_MASK 0x0C00 /* CS1_OFF_RAMP - [11:10] */
36 #define WM831X_CS1_ON_RAMP_MASK 0x0300 /* CS1_ON_RAMP - [9:8] */
39 #define WM831X_CS1_ISEL_MASK 0x003F /* CS1_ISEL - [5:0] */
[all …]
/kernel/linux/linux-5.10/include/linux/mfd/wm831x/
Dregulator.h14 * R16462 (0x404E) - Current Sink 1
16 #define WM831X_CS1_ENA 0x8000 /* CS1_ENA */
17 #define WM831X_CS1_ENA_MASK 0x8000 /* CS1_ENA */
20 #define WM831X_CS1_DRIVE 0x4000 /* CS1_DRIVE */
21 #define WM831X_CS1_DRIVE_MASK 0x4000 /* CS1_DRIVE */
24 #define WM831X_CS1_SLPENA 0x1000 /* CS1_SLPENA */
25 #define WM831X_CS1_SLPENA_MASK 0x1000 /* CS1_SLPENA */
28 #define WM831X_CS1_OFF_RAMP_MASK 0x0C00 /* CS1_OFF_RAMP - [11:10] */
31 #define WM831X_CS1_ON_RAMP_MASK 0x0300 /* CS1_ON_RAMP - [9:8] */
34 #define WM831X_CS1_ISEL_MASK 0x003F /* CS1_ISEL - [5:0] */
[all …]
/kernel/linux/linux-5.10/arch/mips/boot/dts/loongson/
Dloongson64v_4core_virtio.dts12 #address-cells = <0>;
22 ranges = <0 0x1fe00000 0 0x1fe00000 0x100000
23 0 0x3ff00000 0 0x3ff00000 0x100000
24 0xefd 0xfb000000 0xefd 0xfb000000 0x10000000>;
28 reg = <0 0x3ff01400 0x64>;
37 loongson,parent_int_map = <0x00000001>, /* int0 */
38 <0xfffffffe>, /* int1 */
39 <0x00000000>, /* int2 */
40 <0x00000000>; /* int3 */
46 reg = <0 0x1fe001e0 0x8>;
[all …]
/kernel/linux/linux-4.19/arch/powerpc/boot/dts/fsl/
Dmpc8540ads.dts33 #size-cells = <0>;
35 PowerPC,8540@0 {
37 reg = <0x0>;
40 d-cache-size = <0x8000>; // L1, 32K
41 i-cache-size = <0x8000>; // L1, 32K
42 timebase-frequency = <0>; // 33 MHz, from uboot
43 bus-frequency = <0>; // 166 MHz
44 clock-frequency = <0>; // 825 MHz, from uboot
51 reg = <0x0 0x8000000>; // 128M at 0x0
59 ranges = <0x0 0xe0000000 0x100000>;
[all …]
Dmpc8560ads.dts34 #size-cells = <0>;
36 PowerPC,8560@0 {
38 reg = <0x0>;
41 d-cache-size = <0x8000>; // L1, 32K
42 i-cache-size = <0x8000>; // L1, 32K
51 reg = <0x0 0x10000000>;
59 ranges = <0x0 0xe0000000 0x100000>;
62 ecm-law@0 {
64 reg = <0x0 0x1000>;
70 reg = <0x1000 0x1000>;
[all …]
/kernel/linux/linux-5.10/arch/powerpc/boot/dts/fsl/
Dmpc8540ads.dts29 #size-cells = <0>;
31 PowerPC,8540@0 {
33 reg = <0x0>;
36 d-cache-size = <0x8000>; // L1, 32K
37 i-cache-size = <0x8000>; // L1, 32K
38 timebase-frequency = <0>; // 33 MHz, from uboot
39 bus-frequency = <0>; // 166 MHz
40 clock-frequency = <0>; // 825 MHz, from uboot
47 reg = <0x0 0x8000000>; // 128M at 0x0
55 ranges = <0x0 0xe0000000 0x100000>;
[all …]
Dmpc8560ads.dts30 #size-cells = <0>;
32 PowerPC,8560@0 {
34 reg = <0x0>;
37 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <0x8000>; // L1, 32K
47 reg = <0x0 0x10000000>;
55 ranges = <0x0 0xe0000000 0x100000>;
58 ecm-law@0 {
60 reg = <0x0 0x1000>;
66 reg = <0x1000 0x1000>;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/
Dphy-mtk-tphy.txt5 controllers on MediaTek SoCs, such as, USB2.0, USB3.0, PCIe, and SATA.
23 the child's base address to 0, the physical address
72 reg = <0 0x11290000 0 0x800>;
78 reg = <0 0x11290800 0 0x100>;
85 reg = <0 0x11290800 0 0x700>;
92 reg = <0 0x11291000 0 0x100>;
113 phy-names = "usb2-0", "usb3-0";
122 shared 0x0000 SPLLC
123 0x0100 FMREG
124 u2 port0 0x0800 U2PHY_COM
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/phy/
Dphy-mtk-tphy.txt5 controllers on MediaTek SoCs, such as, USB2.0, USB3.0, PCIe, and SATA.
19 "u3phya_ref": for reference clock of usb3.0 analog phy.
60 reg = <0 0x11290000 0 0x800>;
66 reg = <0 0x11290800 0 0x100>;
73 reg = <0 0x11290800 0 0x700>;
80 reg = <0 0x11291000 0 0x100>;
101 phy-names = "usb2-0", "usb3-0";
110 shared 0x0000 SPLLC
111 0x0100 FMREG
112 u2 port0 0x0800 U2PHY_COM
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/realtek/
Drtd129x.dtsi8 /memreserve/ 0x0000000000000000 0x000000000001f000;
9 /memreserve/ 0x000000000001f000 0x00000000000e1000;
10 /memreserve/ 0x0000000001b00000 0x00000000004be000;
26 reg = <0x1f000 0x1000>;
30 reg = <0x1ffe000 0x4000>;
34 reg = <0x10100000 0xf00000>;
47 #clock-cells = <0>;
55 ranges = <0x00000000 0x00000000 0x0001f000>, /* boot ROM */
57 <0x80000000 0x80000000 0x80000000>;
61 reg = <0x98000000 0x200000>;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/dma/
Dmpc512x-dma.txt24 reg = <0x14000 0x1800>;
25 interrupts = <65 0x8>;
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/dma/
Dmpc512x-dma.txt24 reg = <0x14000 0x1800>;
25 interrupts = <65 0x8>;
/kernel/linux/linux-4.19/tools/testing/selftests/x86/
Dmpx-mini-test.c58 assert(fd >= 0); in write_int_to()
60 assert(len >= 0); in write_int_to()
84 write_int_to("", "/sys/kernel/debug/tracing/trace", 0); in trace_me()
121 : "0" (*eax), "2" (*ecx)); in __cpuid()
127 #define REX_PREFIX "0x48, "
129 #define XSAVE_OFFSET_IN_FPMEM 0
144 : "0" (*eax), "2" (*ecx)); in __cpuid()
186 asm volatile(".byte " REX_PREFIX "0x0f,0xae,0x2f\n\t" in xrstor_state()
197 asm volatile(".byte " REX_PREFIX "0x0f,0xae,0x27\n\t" in xsave_state_1()
206 asm volatile(".byte 0x0f,0x01,0xd0" /* xgetbv */ in xgetbv()
[all …]

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