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/kernel/linux/linux-4.19/drivers/media/platform/coda/
Dcoda_regs.h18 #define CODA_REG_BIT_CODE_RUN 0x000
19 #define CODA_REG_RUN_ENABLE (1 << 0)
20 #define CODA_REG_BIT_CODE_DOWN 0x004
21 #define CODA_DOWN_ADDRESS_SET(x) (((x) & 0xffff) << 16)
22 #define CODA_DOWN_DATA_SET(x) ((x) & 0xffff)
23 #define CODA_REG_BIT_HOST_IN_REQ 0x008
24 #define CODA_REG_BIT_INT_CLEAR 0x00c
25 #define CODA_REG_BIT_INT_CLEAR_SET 0x1
26 #define CODA_REG_BIT_INT_STATUS 0x010
27 #define CODA_REG_BIT_CODE_RESET 0x014
[all …]
/kernel/linux/linux-5.10/drivers/media/platform/coda/
Dcoda_regs.h14 #define CODA_REG_BIT_CODE_RUN 0x000
15 #define CODA_REG_RUN_ENABLE (1 << 0)
16 #define CODA_REG_BIT_CODE_DOWN 0x004
17 #define CODA_DOWN_ADDRESS_SET(x) (((x) & 0xffff) << 16)
18 #define CODA_DOWN_DATA_SET(x) ((x) & 0xffff)
19 #define CODA_REG_BIT_HOST_IN_REQ 0x008
20 #define CODA_REG_BIT_INT_CLEAR 0x00c
21 #define CODA_REG_BIT_INT_CLEAR_SET 0x1
22 #define CODA_REG_BIT_INT_STATUS 0x010
23 #define CODA_REG_BIT_CODE_RESET 0x014
[all …]
/kernel/linux/linux-4.19/arch/powerpc/boot/dts/
Dadder875-redboot.dts28 #size-cells = <0>;
30 PowerPC,875@0 {
32 reg = <0>;
37 timebase-frequency = <0>;
38 bus-frequency = <0>;
39 clock-frequency = <0>;
47 reg = <0 0x01000000>;
55 reg = <0xfa200100 0x40>;
58 0 0 0xfe000000 0x00800000
59 2 0 0xfa100000 0x00008000
[all …]
Dadder875-uboot.dts28 #size-cells = <0>;
30 PowerPC,875@0 {
32 reg = <0>;
37 timebase-frequency = <0>;
38 bus-frequency = <0>;
39 clock-frequency = <0>;
47 reg = <0 0x01000000>;
55 reg = <0xff000100 0x40>;
58 0 0 0xfe000000 0x01000000
61 flash@0,0 {
[all …]
Dep88xc.dts23 #size-cells = <0>;
25 PowerPC,885@0 {
27 reg = <0x0>;
32 timebase-frequency = <0>;
33 bus-frequency = <0>;
34 clock-frequency = <0>;
42 reg = <0x0 0x0>;
49 reg = <0xfa200100 0x40>;
52 0x0 0x0 0xfc000000 0x4000000
53 0x3 0x0 0xfa000000 0x1000000
[all …]
Dmpc885ads.dts23 #size-cells = <0>;
25 PowerPC,885@0 {
27 reg = <0x0>;
32 timebase-frequency = <0>;
33 bus-frequency = <0>;
34 clock-frequency = <0>;
42 reg = <0x0 0x0>;
49 reg = <0xff000100 0x40>;
52 0x0 0x0 0xfe000000 0x800000
53 0x1 0x0 0xff080000 0x8000
[all …]
Dmpc866ads.dts23 #size-cells = <0>;
25 PowerPC,866@0 {
27 reg = <0x0>;
30 d-cache-size = <0x2000>; // L1, 8K
31 i-cache-size = <0x4000>; // L1, 16K
32 timebase-frequency = <0>;
33 bus-frequency = <0>;
34 clock-frequency = <0>;
42 reg = <0x0 0x800000>;
49 reg = <0xff000100 0x40>;
[all …]
Dtqm8xx.dts30 #size-cells = <0>;
32 PowerPC,860@0 {
34 reg = <0x0>;
37 d-cache-size = <0x1000>; // L1, 4K
38 i-cache-size = <0x1000>; // L1, 4K
39 timebase-frequency = <0>;
40 bus-frequency = <0>;
41 clock-frequency = <0>;
49 reg = <0x0 0x2000000>;
56 reg = <0xfff00100 0x40>;
[all …]
/kernel/linux/linux-5.10/arch/powerpc/boot/dts/
Dadder875-redboot.dts24 #size-cells = <0>;
26 PowerPC,875@0 {
28 reg = <0>;
33 timebase-frequency = <0>;
34 bus-frequency = <0>;
35 clock-frequency = <0>;
43 reg = <0 0x01000000>;
51 reg = <0xfa200100 0x40>;
54 0 0 0xfe000000 0x00800000
55 2 0 0xfa100000 0x00008000
[all …]
Dadder875-uboot.dts24 #size-cells = <0>;
26 PowerPC,875@0 {
28 reg = <0>;
33 timebase-frequency = <0>;
34 bus-frequency = <0>;
35 clock-frequency = <0>;
43 reg = <0 0x01000000>;
51 reg = <0xff000100 0x40>;
54 0 0 0xfe000000 0x01000000
57 flash@0,0 {
[all …]
Dep88xc.dts19 #size-cells = <0>;
21 PowerPC,885@0 {
23 reg = <0x0>;
28 timebase-frequency = <0>;
29 bus-frequency = <0>;
30 clock-frequency = <0>;
38 reg = <0x0 0x0>;
45 reg = <0xfa200100 0x40>;
48 0x0 0x0 0xfc000000 0x4000000
49 0x3 0x0 0xfa000000 0x1000000
[all …]
Dmpc885ads.dts19 #size-cells = <0>;
21 PowerPC,885@0 {
23 reg = <0x0>;
28 timebase-frequency = <0>;
29 bus-frequency = <0>;
30 clock-frequency = <0>;
38 reg = <0x0 0x0>;
45 reg = <0xff000100 0x40>;
48 0x0 0x0 0xfe000000 0x800000
49 0x1 0x0 0xff080000 0x8000
[all …]
Dmpc866ads.dts19 #size-cells = <0>;
21 PowerPC,866@0 {
23 reg = <0x0>;
26 d-cache-size = <0x2000>; // L1, 8K
27 i-cache-size = <0x4000>; // L1, 16K
28 timebase-frequency = <0>;
29 bus-frequency = <0>;
30 clock-frequency = <0>;
38 reg = <0x0 0x800000>;
45 reg = <0xff000100 0x40>;
[all …]
Dtqm8xx.dts26 #size-cells = <0>;
28 PowerPC,860@0 {
30 reg = <0x0>;
33 d-cache-size = <0x1000>; // L1, 4K
34 i-cache-size = <0x1000>; // L1, 4K
35 timebase-frequency = <0>;
36 bus-frequency = <0>;
37 clock-frequency = <0>;
45 reg = <0x0 0x2000000>;
52 reg = <0xfff00100 0x40>;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/
Dphy-hi3798cv200-combphy.txt37 reg = <0x8a20000 0x1000>;
40 ranges = <0x0 0x8a20000 0x1000>;
44 reg = <0x850 0x8>;
47 resets = <&crg 0x188 4>;
53 reg = <0x858 0x8>;
56 resets = <&crg 0x188 12>;
57 hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>;
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/phy/
Dphy-hi3798cv200-combphy.txt37 reg = <0x8a20000 0x1000>;
40 ranges = <0x0 0x8a20000 0x1000>;
44 reg = <0x850 0x8>;
47 resets = <&crg 0x188 4>;
53 reg = <0x858 0x8>;
56 resets = <&crg 0x188 12>;
57 hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>;
/kernel/linux/linux-5.10/drivers/clk/hisilicon/
Dcrg-hi3798cv200.c45 { HISTB_OSC_CLK, "clk_osc", NULL, 0, 24000000, },
46 { HISTB_APB_CLK, "clk_apb", NULL, 0, 100000000, },
47 { HISTB_AHB_CLK, "clk_ahb", NULL, 0, 200000000, },
48 { HI3798CV200_FIXED_12M, "12m", NULL, 0, 12000000, },
49 { HI3798CV200_FIXED_24M, "24m", NULL, 0, 24000000, },
50 { HI3798CV200_FIXED_25M, "25m", NULL, 0, 25000000, },
51 { HI3798CV200_FIXED_48M, "48m", NULL, 0, 48000000, },
52 { HI3798CV200_FIXED_50M, "50m", NULL, 0, 50000000, },
53 { HI3798CV200_FIXED_60M, "60m", NULL, 0, 60000000, },
54 { HI3798CV200_FIXED_75M, "75m", NULL, 0, 75000000, },
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
Damdgpu_doorbell.h85 AMDGPU_DOORBELL_KIQ = 0x000,
86 AMDGPU_DOORBELL_HIQ = 0x001,
87 AMDGPU_DOORBELL_DIQ = 0x002,
88 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
89 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
90 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
91 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
92 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
93 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
94 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
[all …]
/kernel/linux/linux-4.19/drivers/clk/hisilicon/
Dcrg-hi3798cv200.c57 { HISTB_OSC_CLK, "clk_osc", NULL, 0, 24000000, },
58 { HISTB_APB_CLK, "clk_apb", NULL, 0, 100000000, },
59 { HISTB_AHB_CLK, "clk_ahb", NULL, 0, 200000000, },
60 { HI3798CV200_FIXED_12M, "12m", NULL, 0, 12000000, },
61 { HI3798CV200_FIXED_24M, "24m", NULL, 0, 24000000, },
62 { HI3798CV200_FIXED_25M, "25m", NULL, 0, 25000000, },
63 { HI3798CV200_FIXED_48M, "48m", NULL, 0, 48000000, },
64 { HI3798CV200_FIXED_50M, "50m", NULL, 0, 50000000, },
65 { HI3798CV200_FIXED_60M, "60m", NULL, 0, 60000000, },
66 { HI3798CV200_FIXED_75M, "75m", NULL, 0, 75000000, },
[all …]
/kernel/linux/linux-5.10/drivers/video/fbdev/omap2/omapfb/dss/
Dhdmi4_core.h15 #define HDMI_CORE_SYS_VND_IDL 0x0
16 #define HDMI_CORE_SYS_DEV_IDL 0x8
17 #define HDMI_CORE_SYS_DEV_IDH 0xC
18 #define HDMI_CORE_SYS_DEV_REV 0x10
19 #define HDMI_CORE_SYS_SRST 0x14
20 #define HDMI_CORE_SYS_SYS_CTRL1 0x20
21 #define HDMI_CORE_SYS_SYS_STAT 0x24
22 #define HDMI_CORE_SYS_SYS_CTRL3 0x28
23 #define HDMI_CORE_SYS_DCTL 0x34
24 #define HDMI_CORE_SYS_DE_DLY 0xC8
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/omapdrm/dss/
Dhdmi4_core.h15 #define HDMI_CORE_SYS_VND_IDL 0x0
16 #define HDMI_CORE_SYS_DEV_IDL 0x8
17 #define HDMI_CORE_SYS_DEV_IDH 0xC
18 #define HDMI_CORE_SYS_DEV_REV 0x10
19 #define HDMI_CORE_SYS_SRST 0x14
20 #define HDMI_CORE_SYS_SYS_CTRL1 0x20
21 #define HDMI_CORE_SYS_SYS_STAT 0x24
22 #define HDMI_CORE_SYS_SYS_CTRL3 0x28
23 #define HDMI_CORE_SYS_DCTL 0x34
24 #define HDMI_CORE_SYS_DE_DLY 0xC8
[all …]
/kernel/linux/linux-4.19/drivers/video/fbdev/omap2/omapfb/dss/
Dhdmi4_core.h26 #define HDMI_CORE_SYS_VND_IDL 0x0
27 #define HDMI_CORE_SYS_DEV_IDL 0x8
28 #define HDMI_CORE_SYS_DEV_IDH 0xC
29 #define HDMI_CORE_SYS_DEV_REV 0x10
30 #define HDMI_CORE_SYS_SRST 0x14
31 #define HDMI_CORE_SYS_SYS_CTRL1 0x20
32 #define HDMI_CORE_SYS_SYS_STAT 0x24
33 #define HDMI_CORE_SYS_SYS_CTRL3 0x28
34 #define HDMI_CORE_SYS_DCTL 0x34
35 #define HDMI_CORE_SYS_DE_DLY 0xC8
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/omapdrm/dss/
Dhdmi4_core.h26 #define HDMI_CORE_SYS_VND_IDL 0x0
27 #define HDMI_CORE_SYS_DEV_IDL 0x8
28 #define HDMI_CORE_SYS_DEV_IDH 0xC
29 #define HDMI_CORE_SYS_DEV_REV 0x10
30 #define HDMI_CORE_SYS_SRST 0x14
31 #define HDMI_CORE_SYS_SYS_CTRL1 0x20
32 #define HDMI_CORE_SYS_SYS_STAT 0x24
33 #define HDMI_CORE_SYS_SYS_CTRL3 0x28
34 #define HDMI_CORE_SYS_DCTL 0x34
35 #define HDMI_CORE_SYS_DE_DLY 0xC8
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/power/
Drenesas,apmu.txt31 reg = <0 0xe6152000 0 0x188>;
/kernel/linux/linux-5.10/include/dt-bindings/clock/
Ddm816.h8 #define DM816_CLKCTRL_OFFSET 0x0
12 #define DM816_USB_OTG_HS_CLKCTRL DM816_CLKCTRL_INDEX(0x58)
15 #define DM816_UART1_CLKCTRL DM816_CLKCTRL_INDEX(0x150)
16 #define DM816_UART2_CLKCTRL DM816_CLKCTRL_INDEX(0x154)
17 #define DM816_UART3_CLKCTRL DM816_CLKCTRL_INDEX(0x158)
18 #define DM816_GPIO1_CLKCTRL DM816_CLKCTRL_INDEX(0x15c)
19 #define DM816_GPIO2_CLKCTRL DM816_CLKCTRL_INDEX(0x160)
20 #define DM816_I2C1_CLKCTRL DM816_CLKCTRL_INDEX(0x164)
21 #define DM816_I2C2_CLKCTRL DM816_CLKCTRL_INDEX(0x168)
22 #define DM816_TIMER1_CLKCTRL DM816_CLKCTRL_INDEX(0x170)
[all …]

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