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/kernel/linux/linux-4.19/drivers/media/platform/coda/
Dcoda_regs.h18 #define CODA_REG_BIT_CODE_RUN 0x000
19 #define CODA_REG_RUN_ENABLE (1 << 0)
20 #define CODA_REG_BIT_CODE_DOWN 0x004
21 #define CODA_DOWN_ADDRESS_SET(x) (((x) & 0xffff) << 16)
22 #define CODA_DOWN_DATA_SET(x) ((x) & 0xffff)
23 #define CODA_REG_BIT_HOST_IN_REQ 0x008
24 #define CODA_REG_BIT_INT_CLEAR 0x00c
25 #define CODA_REG_BIT_INT_CLEAR_SET 0x1
26 #define CODA_REG_BIT_INT_STATUS 0x010
27 #define CODA_REG_BIT_CODE_RESET 0x014
[all …]
/kernel/linux/linux-5.10/drivers/media/platform/coda/
Dcoda_regs.h14 #define CODA_REG_BIT_CODE_RUN 0x000
15 #define CODA_REG_RUN_ENABLE (1 << 0)
16 #define CODA_REG_BIT_CODE_DOWN 0x004
17 #define CODA_DOWN_ADDRESS_SET(x) (((x) & 0xffff) << 16)
18 #define CODA_DOWN_DATA_SET(x) ((x) & 0xffff)
19 #define CODA_REG_BIT_HOST_IN_REQ 0x008
20 #define CODA_REG_BIT_INT_CLEAR 0x00c
21 #define CODA_REG_BIT_INT_CLEAR_SET 0x1
22 #define CODA_REG_BIT_INT_STATUS 0x010
23 #define CODA_REG_BIT_CODE_RESET 0x014
[all …]
/kernel/linux/linux-5.10/include/dt-bindings/clock/
Ddm816.h8 #define DM816_CLKCTRL_OFFSET 0x0
12 #define DM816_USB_OTG_HS_CLKCTRL DM816_CLKCTRL_INDEX(0x58)
15 #define DM816_UART1_CLKCTRL DM816_CLKCTRL_INDEX(0x150)
16 #define DM816_UART2_CLKCTRL DM816_CLKCTRL_INDEX(0x154)
17 #define DM816_UART3_CLKCTRL DM816_CLKCTRL_INDEX(0x158)
18 #define DM816_GPIO1_CLKCTRL DM816_CLKCTRL_INDEX(0x15c)
19 #define DM816_GPIO2_CLKCTRL DM816_CLKCTRL_INDEX(0x160)
20 #define DM816_I2C1_CLKCTRL DM816_CLKCTRL_INDEX(0x164)
21 #define DM816_I2C2_CLKCTRL DM816_CLKCTRL_INDEX(0x168)
22 #define DM816_TIMER1_CLKCTRL DM816_CLKCTRL_INDEX(0x170)
[all …]
Ddra7.h8 #define DRA7_CLKCTRL_OFFSET 0x20
14 #define DRA7_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
17 #define _DRA7_IPU_CLKCTRL_OFFSET 0x40
19 #define DRA7_MCASP1_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x50)
20 #define DRA7_TIMER5_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x58)
21 #define DRA7_TIMER6_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x60)
22 #define DRA7_TIMER7_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x68)
23 #define DRA7_TIMER8_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x70)
24 #define DRA7_I2C5_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x78)
25 #define DRA7_UART6_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x80)
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dvf610-pinfunc.h14 #define ALT0 0x0
15 #define ALT1 0x1
16 #define ALT2 0x2
17 #define ALT3 0x3
18 #define ALT4 0x4
19 #define ALT5 0x5
20 #define ALT6 0x6
21 #define ALT7 0x7
24 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0
25 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0
[all …]
Dox810se-wd-mbwe.dts22 reg = <0x48000000 0x8000000>;
34 #size-cells = <0>;
39 gpios = <&gpio0 0 1>;
40 linux,code = <0x198>;
46 linux,code = <0xab>;
55 gpios = <&gpio0 25 0>;
61 gpios = <&gpio0 26 0>;
67 gpios = <&gpio0 5 0>;
73 gpios = <&gpio0 6 0>;
79 gpios = <&gpio0 7 0>;
[all …]
Dimx50-pinfunc.h13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0
14 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0
15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0
16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0
17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0
18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0
19 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0
20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0
21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0
22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0
[all …]
/kernel/linux/linux-4.19/arch/arm/boot/dts/
Dvf610-pinfunc.h18 #define ALT0 0x0
19 #define ALT1 0x1
20 #define ALT2 0x2
21 #define ALT3 0x3
22 #define ALT4 0x4
23 #define ALT5 0x5
24 #define ALT6 0x6
25 #define ALT7 0x7
28 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0
29 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0
[all …]
Dox810se-wd-mbwe.dts23 reg = <0x48000000 0x8000000>;
35 #size-cells = <0>;
40 gpios = <&gpio0 0 1>;
41 linux,code = <0x198>;
47 linux,code = <0xab>;
56 gpios = <&gpio0 25 0>;
62 gpios = <&gpio0 26 0>;
68 gpios = <&gpio0 5 0>;
74 gpios = <&gpio0 6 0>;
80 gpios = <&gpio0 7 0>;
[all …]
Dimx50-pinfunc.h17 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0
18 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0
19 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0
20 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0
21 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0
22 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0
23 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0
24 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0
25 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0
26 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0
[all …]
Domap4-droid4-xt894.dts31 reg = <0x80000000 0x3fd00000>; /* 1021 MB */
37 pinctrl-0 = <&poweroff_gpio>;
44 pinctrl-0 = <&hdmi_hpd_gpio>;
76 pinctrl-0 = <&usb_mdm6600_pins>;
92 #phy-cells = <0>;
98 #phy-cells = <0>;
107 gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>; /* gpio96 */
168 pinctrl-0 = <&vibrator_direction_pin>;
173 ti,clock-source = <0x01>;
178 pinctrl-0 = <&vibrator_enable_pin>;
[all …]
/kernel/linux/linux-4.19/include/dt-bindings/clock/
Ddm816.h16 #define DM816_CLKCTRL_OFFSET 0x0
20 #define DM816_USB_OTG_HS_CLKCTRL DM816_CLKCTRL_INDEX(0x58)
23 #define DM816_UART1_CLKCTRL DM816_CLKCTRL_INDEX(0x150)
24 #define DM816_UART2_CLKCTRL DM816_CLKCTRL_INDEX(0x154)
25 #define DM816_UART3_CLKCTRL DM816_CLKCTRL_INDEX(0x158)
26 #define DM816_GPIO1_CLKCTRL DM816_CLKCTRL_INDEX(0x15c)
27 #define DM816_GPIO2_CLKCTRL DM816_CLKCTRL_INDEX(0x160)
28 #define DM816_I2C1_CLKCTRL DM816_CLKCTRL_INDEX(0x164)
29 #define DM816_I2C2_CLKCTRL DM816_CLKCTRL_INDEX(0x168)
30 #define DM816_TIMER1_CLKCTRL DM816_CLKCTRL_INDEX(0x170)
[all …]
/kernel/linux/linux-5.10/tools/power/cpupower/debug/i386/
Dcentrino-decode.c9 * USAGE: simply run it to decode the current settings on CPU 0,
26 #define MSR_IA32_PERF_STATUS 0x198
36 *lo = *hi = 0; in rdmsr()
44 if (fd < 0) in rdmsr()
53 *lo = (uint32_t )(val & 0xffffffffull); in rdmsr()
54 *hi = (uint32_t )(val>>32 & 0xffffffffull); in rdmsr()
56 retval = 0; in rdmsr()
68 multiplier = ((msr >> 8) & 0xFF); in decode()
70 mv = (((msr & 0xFF) * 16) + 700); in decode()
72 printf("0x%x means multiplier %d @ %d mV\n", msr, multiplier, mv); in decode()
[all …]
/kernel/linux/linux-4.19/tools/power/cpupower/debug/i386/
Dcentrino-decode.c10 * USAGE: simply run it to decode the current settings on CPU 0,
27 #define MSR_IA32_PERF_STATUS 0x198
37 *lo = *hi = 0; in rdmsr()
45 if (fd < 0) in rdmsr()
54 *lo = (uint32_t )(val & 0xffffffffull); in rdmsr()
55 *hi = (uint32_t )(val>>32 & 0xffffffffull); in rdmsr()
57 retval = 0; in rdmsr()
69 multiplier = ((msr >> 8) & 0xFF); in decode()
71 mv = (((msr & 0xFF) * 16) + 700); in decode()
73 printf("0x%x means multiplier %d @ %d mV\n", msr, multiplier, mv); in decode()
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/
Dimx8mq-pinfunc.h15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
Dimx8mm-pinfunc.h14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0…
20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0…
21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0…
22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0…
23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0…
[all …]
/kernel/linux/linux-5.10/drivers/crypto/caam/
Ddpseci_cmd.h29 #define DPSECI_CMDID_CLOSE DPSECI_CMD_V1(0x800)
30 #define DPSECI_CMDID_OPEN DPSECI_CMD_V1(0x809)
31 #define DPSECI_CMDID_GET_API_VERSION DPSECI_CMD_V1(0xa09)
33 #define DPSECI_CMDID_ENABLE DPSECI_CMD_V1(0x002)
34 #define DPSECI_CMDID_DISABLE DPSECI_CMD_V1(0x003)
35 #define DPSECI_CMDID_GET_ATTR DPSECI_CMD_V1(0x004)
36 #define DPSECI_CMDID_RESET DPSECI_CMD_V1(0x005)
37 #define DPSECI_CMDID_IS_ENABLED DPSECI_CMD_V1(0x006)
39 #define DPSECI_CMDID_SET_RX_QUEUE DPSECI_CMD_V1(0x194)
40 #define DPSECI_CMDID_GET_RX_QUEUE DPSECI_CMD_V1(0x196)
[all …]
/kernel/linux/linux-4.19/tools/power/cpupower/utils/helpers/
Dmsr.c12 #define MSR_IA32_PERF_STATUS 0x198
13 #define MSR_IA32_MISC_ENABLES 0x1a0
14 #define MSR_IA32_ENERGY_PERF_BIAS 0x1b0
15 #define MSR_NEHALEM_TURBO_RATIO_LIMIT 0x1ad
20 * Will return 0 on success and -1 on failure.
34 if (fd < 0) in read_msr()
41 return 0; in read_msr()
50 * Will return 0 on success and -1 on failure.
63 if (fd < 0) in write_msr()
70 return 0; in write_msr()
[all …]
/kernel/linux/linux-5.10/tools/power/cpupower/utils/helpers/
Dmsr.c12 #define MSR_IA32_PERF_STATUS 0x198
13 #define MSR_IA32_MISC_ENABLES 0x1a0
14 #define MSR_IA32_ENERGY_PERF_BIAS 0x1b0
15 #define MSR_NEHALEM_TURBO_RATIO_LIMIT 0x1ad
20 * Will return 0 on success and -1 on failure.
34 if (fd < 0) in read_msr()
41 return 0; in read_msr()
50 * Will return 0 on success and -1 on failure.
63 if (fd < 0) in write_msr()
70 return 0; in write_msr()
[all …]
/kernel/linux/linux-5.10/drivers/phy/qualcomm/
Dphy-qcom-qmp.h10 #define QSERDES_COM_BG_TIMER 0x00c
11 #define QSERDES_COM_SSC_EN_CENTER 0x010
12 #define QSERDES_COM_SSC_ADJ_PER1 0x014
13 #define QSERDES_COM_SSC_ADJ_PER2 0x018
14 #define QSERDES_COM_SSC_PER1 0x01c
15 #define QSERDES_COM_SSC_PER2 0x020
16 #define QSERDES_COM_SSC_STEP_SIZE1 0x024
17 #define QSERDES_COM_SSC_STEP_SIZE2 0x028
18 #define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034
19 #define QSERDES_COM_CLK_ENABLE1 0x038
[all …]
/kernel/linux/linux-4.19/drivers/clk/meson/
Dmeson8b.h16 * Register offsets from the HardKernel[0] data sheet are listed in comment
20 * [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
22 #define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */
23 #define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet */
24 #define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */
25 #define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet */
26 #define HHI_GCLK_AO 0x154 /* 0x55 offset in data sheet */
27 #define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data sheet */
28 #define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */
29 #define HHI_VID_CLK_CNTL 0x17c /* 0x5f offset in data sheet */
[all …]
/kernel/linux/linux-4.19/tools/perf/arch/powerpc/util/
Dbook3s_hcalls.h9 {0x4, "H_REMOVE"}, \
10 {0x8, "H_ENTER"}, \
11 {0xc, "H_READ"}, \
12 {0x10, "H_CLEAR_MOD"}, \
13 {0x14, "H_CLEAR_REF"}, \
14 {0x18, "H_PROTECT"}, \
15 {0x1c, "H_GET_TCE"}, \
16 {0x20, "H_PUT_TCE"}, \
17 {0x24, "H_SET_SPRG0"}, \
18 {0x28, "H_SET_DABR"}, \
[all …]
/kernel/linux/linux-5.10/tools/perf/arch/powerpc/util/
Dbook3s_hcalls.h9 {0x4, "H_REMOVE"}, \
10 {0x8, "H_ENTER"}, \
11 {0xc, "H_READ"}, \
12 {0x10, "H_CLEAR_MOD"}, \
13 {0x14, "H_CLEAR_REF"}, \
14 {0x18, "H_PROTECT"}, \
15 {0x1c, "H_GET_TCE"}, \
16 {0x20, "H_PUT_TCE"}, \
17 {0x24, "H_SET_SPRG0"}, \
18 {0x28, "H_SET_DABR"}, \
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/i2c/
Dsnps,designware-i2c.yaml112 reg = <0xf0000 0x1000>;
114 #size-cells = <0>;
121 reg = <0x1120000 0x1000>;
123 #size-cells = <0>;
133 reg = <0x2000 0x100>;
135 #size-cells = <0>;
138 interrupts = <0>;
142 reg = <0x64>;
148 reg = <0x100400 0x100>, <0x198 0x8>;
149 pinctrl-0 = <&i2c_pins>;
[all …]
/kernel/linux/linux-5.10/drivers/scsi/ufs/
Dufs_quirks.h12 #define UFS_ANY_VENDOR 0xFFFF
15 #define UFS_VENDOR_MICRON 0x12C
16 #define UFS_VENDOR_SAMSUNG 0x1CE
17 #define UFS_VENDOR_SKHYNIX 0x1AD
18 #define UFS_VENDOR_TOSHIBA 0x198
19 #define UFS_VENDOR_WDC 0x145
100 * Some UFS devices require VS_DebugSaveConfigTime is 0x10,

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