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/kernel/linux/linux-4.19/drivers/media/platform/coda/
Dcoda_regs.h18 #define CODA_REG_BIT_CODE_RUN 0x000
19 #define CODA_REG_RUN_ENABLE (1 << 0)
20 #define CODA_REG_BIT_CODE_DOWN 0x004
21 #define CODA_DOWN_ADDRESS_SET(x) (((x) & 0xffff) << 16)
22 #define CODA_DOWN_DATA_SET(x) ((x) & 0xffff)
23 #define CODA_REG_BIT_HOST_IN_REQ 0x008
24 #define CODA_REG_BIT_INT_CLEAR 0x00c
25 #define CODA_REG_BIT_INT_CLEAR_SET 0x1
26 #define CODA_REG_BIT_INT_STATUS 0x010
27 #define CODA_REG_BIT_CODE_RESET 0x014
[all …]
/kernel/linux/linux-5.10/drivers/media/platform/coda/
Dcoda_regs.h14 #define CODA_REG_BIT_CODE_RUN 0x000
15 #define CODA_REG_RUN_ENABLE (1 << 0)
16 #define CODA_REG_BIT_CODE_DOWN 0x004
17 #define CODA_DOWN_ADDRESS_SET(x) (((x) & 0xffff) << 16)
18 #define CODA_DOWN_DATA_SET(x) ((x) & 0xffff)
19 #define CODA_REG_BIT_HOST_IN_REQ 0x008
20 #define CODA_REG_BIT_INT_CLEAR 0x00c
21 #define CODA_REG_BIT_INT_CLEAR_SET 0x1
22 #define CODA_REG_BIT_INT_STATUS 0x010
23 #define CODA_REG_BIT_CODE_RESET 0x014
[all …]
/kernel/linux/linux-5.10/drivers/clk/sunxi-ng/
Dccu-sun50i-a100-r.c24 { .index = 3, .shift = 0, .width = 5 },
39 .reg = 0x000,
44 0),
48 static CLK_FIXED_FACTOR_HW(r_ahb_clk, "r-ahb", &r_cpus_clk.common.hw, 1, 1, 0);
51 .div = _SUNXI_CCU_DIV(0, 2),
54 .reg = 0x00c,
58 0),
74 .reg = 0x010,
79 0),
92 0x11c, BIT(0), 0);
[all …]
Dccu-sun50i-h6-r.c28 { .index = 3, .shift = 0, .width = 5 },
43 .reg = 0x000,
48 0),
52 static CLK_FIXED_FACTOR_HW(r_ahb_clk, "r-ahb", &ar100_clk.common.hw, 1, 1, 0);
54 static SUNXI_CCU_M(r_apb1_clk, "r-apb1", "r-ahb", 0x00c, 0, 2, 0);
68 .reg = 0x010,
73 0),
85 0x11c, BIT(0), 0);
87 0x12c, BIT(0), 0);
89 0x13c, BIT(0), 0);
[all …]
/kernel/linux/linux-4.19/tools/perf/pmu-events/arch/x86/jaketown/
Duncore-cache.json4 "Counter": "0,1,2,3",
11 "Counter": "0,1",
12 "EventCode": "0x34",
14 "Filter": "filter_state=0x1",
17 "UMask": "0x11",
22 "Counter": "0,1",
23 "EventCode": "0x37",
27 "UMask": "0x1",
32 "Counter": "0,1",
33 "EventCode": "0x35",
[all …]
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/jaketown/
Duncore-cache.json4 "Counter": "0,1,2,3",
11 "Counter": "0,1",
12 "EventCode": "0x34",
14 "Filter": "filter_state=0x1",
17 "UMask": "0x11",
22 "Counter": "0,1",
23 "EventCode": "0x37",
27 "UMask": "0x1",
32 "Counter": "0,1",
33 "EventCode": "0x35",
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dvf610-pinfunc.h14 #define ALT0 0x0
15 #define ALT1 0x1
16 #define ALT2 0x2
17 #define ALT3 0x3
18 #define ALT4 0x4
19 #define ALT5 0x5
20 #define ALT6 0x6
21 #define ALT7 0x7
24 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0
25 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0
[all …]
Dimx50-pinfunc.h13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0
14 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0
15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0
16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0
17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0
18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0
19 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0
20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0
21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0
22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0
[all …]
/kernel/linux/linux-4.19/arch/arm/boot/dts/
Dvf610-pinfunc.h18 #define ALT0 0x0
19 #define ALT1 0x1
20 #define ALT2 0x2
21 #define ALT3 0x3
22 #define ALT4 0x4
23 #define ALT5 0x5
24 #define ALT6 0x6
25 #define ALT7 0x7
28 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0
29 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0
[all …]
Dimx50-pinfunc.h17 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0
18 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0
19 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0
20 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0
21 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0
22 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0
23 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0
24 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0
25 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0
26 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0
[all …]
/kernel/linux/linux-4.19/drivers/clk/sunxi-ng/
Dccu-sun50i-h6-r.c28 { .index = 3, .shift = 0, .width = 5 },
43 .reg = 0x000,
48 0),
52 static CLK_FIXED_FACTOR(r_ahb_clk, "r-ahb", "ar100", 1, 1, 0);
55 .div = _SUNXI_CCU_DIV(0, 2),
58 .reg = 0x00c,
62 0),
78 .reg = 0x010,
83 0),
95 0x11c, BIT(0), 0);
[all …]
/kernel/linux/linux-5.10/drivers/phy/qualcomm/
Dphy-qcom-qmp.h10 #define QSERDES_COM_BG_TIMER 0x00c
11 #define QSERDES_COM_SSC_EN_CENTER 0x010
12 #define QSERDES_COM_SSC_ADJ_PER1 0x014
13 #define QSERDES_COM_SSC_ADJ_PER2 0x018
14 #define QSERDES_COM_SSC_PER1 0x01c
15 #define QSERDES_COM_SSC_PER2 0x020
16 #define QSERDES_COM_SSC_STEP_SIZE1 0x024
17 #define QSERDES_COM_SSC_STEP_SIZE2 0x028
18 #define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034
19 #define QSERDES_COM_CLK_ENABLE1 0x038
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/
Dimx8mq-pinfunc.h15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
Dimx8mp-pinfunc.h13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
[all …]
Dimx8mm-pinfunc.h14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0…
20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0…
21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0…
22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0…
23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0…
[all …]
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/ivytown/
Duncore-cache.json4 "Counter": "0,1,2,3",
11 "Counter": "0,1",
12 "EventCode": "0x34",
14 "Filter": "filter_state=0x1",
17 "UMask": "0x11",
22 "Counter": "0,1",
23 "EventCode": "0x37",
27 "UMask": "0x1",
32 "Counter": "0,1",
33 "EventCode": "0x35",
[all …]
/kernel/linux/linux-4.19/tools/perf/pmu-events/arch/x86/ivytown/
Duncore-cache.json4 "Counter": "0,1,2,3",
11 "Counter": "0,1",
12 "EventCode": "0x34",
14 "Filter": "filter_state=0x1",
17 "UMask": "0x11",
22 "Counter": "0,1",
23 "EventCode": "0x37",
27 "UMask": "0x1",
32 "Counter": "0,1",
33 "EventCode": "0x35",
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/display/rockchip/
Drockchip-vop.txt47 reg = <0xff930000 0x19c>;
56 #size-cells = <0>;
57 vopb_out_edp: endpoint@0 {
58 reg = <0>;
/kernel/linux/linux-5.10/drivers/crypto/qat/qat_common/
Dadf_hw_arbiter.c8 #define ADF_ARB_REG_SIZE 0x4
9 #define ADF_ARB_WTR_SIZE 0x20
10 #define ADF_ARB_OFFSET 0x30000
11 #define ADF_ARB_REG_SLOT 0x1000
12 #define ADF_ARB_WTR_OFFSET 0x010
13 #define ADF_ARB_RO_EN_OFFSET 0x090
14 #define ADF_ARB_WQCFG_OFFSET 0x100
15 #define ADF_ARB_WRK_2_SER_MAP_OFFSET 0x180
16 #define ADF_ARB_RINGSRVARBEN_OFFSET 0x19C
38 void __iomem *csr = accel_dev->transport->banks[0].csr_addr; in adf_init_arb()
[all …]
/kernel/linux/linux-5.10/drivers/clk/meson/
Daxg.h19 #define HHI_MIPI_CNTL0 0x00
20 #define HHI_GP0_PLL_CNTL 0x40
21 #define HHI_GP0_PLL_CNTL2 0x44
22 #define HHI_GP0_PLL_CNTL3 0x48
23 #define HHI_GP0_PLL_CNTL4 0x4c
24 #define HHI_GP0_PLL_CNTL5 0x50
25 #define HHI_GP0_PLL_STS 0x54
26 #define HHI_GP0_PLL_CNTL1 0x58
27 #define HHI_HIFI_PLL_CNTL 0x80
28 #define HHI_HIFI_PLL_CNTL2 0x84
[all …]
/kernel/linux/linux-4.19/drivers/clk/meson/
Daxg.h19 #define HHI_MIPI_CNTL0 0x00
20 #define HHI_GP0_PLL_CNTL 0x40
21 #define HHI_GP0_PLL_CNTL2 0x44
22 #define HHI_GP0_PLL_CNTL3 0x48
23 #define HHI_GP0_PLL_CNTL4 0x4c
24 #define HHI_GP0_PLL_CNTL5 0x50
25 #define HHI_GP0_PLL_STS 0x54
26 #define HHI_GP0_PLL_CNTL1 0x58
27 #define HHI_HIFI_PLL_CNTL 0x80
28 #define HHI_HIFI_PLL_CNTL2 0x84
[all …]
Dmeson8b.h16 * Register offsets from the HardKernel[0] data sheet are listed in comment
20 * [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
22 #define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */
23 #define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet */
24 #define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */
25 #define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet */
26 #define HHI_GCLK_AO 0x154 /* 0x55 offset in data sheet */
27 #define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data sheet */
28 #define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */
29 #define HHI_VID_CLK_CNTL 0x17c /* 0x5f offset in data sheet */
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/rockchip/
Drockchip-vop.yaml109 reg = <0xff930000 0x19c>,
110 <0xff931000 0x1000>;
124 #size-cells = <0>;
125 vopb_out_edp: endpoint@0 {
126 reg = <0>;
/kernel/linux/linux-4.19/tools/perf/arch/powerpc/util/
Dbook3s_hcalls.h9 {0x4, "H_REMOVE"}, \
10 {0x8, "H_ENTER"}, \
11 {0xc, "H_READ"}, \
12 {0x10, "H_CLEAR_MOD"}, \
13 {0x14, "H_CLEAR_REF"}, \
14 {0x18, "H_PROTECT"}, \
15 {0x1c, "H_GET_TCE"}, \
16 {0x20, "H_PUT_TCE"}, \
17 {0x24, "H_SET_SPRG0"}, \
18 {0x28, "H_SET_DABR"}, \
[all …]
/kernel/linux/linux-5.10/tools/perf/arch/powerpc/util/
Dbook3s_hcalls.h9 {0x4, "H_REMOVE"}, \
10 {0x8, "H_ENTER"}, \
11 {0xc, "H_READ"}, \
12 {0x10, "H_CLEAR_MOD"}, \
13 {0x14, "H_CLEAR_REF"}, \
14 {0x18, "H_PROTECT"}, \
15 {0x1c, "H_GET_TCE"}, \
16 {0x20, "H_PUT_TCE"}, \
17 {0x24, "H_SET_SPRG0"}, \
18 {0x28, "H_SET_DABR"}, \
[all …]

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