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/kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/mediatek/
Dmediatek,ssusbsys.txt21 reg = <0 0x1a000000 0 0x1000>;
Dmediatek,hifsys.txt22 reg = <0 0x1a000000 0 0x1000>;
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/mediatek/
Dmediatek,camsys.txt22 reg = <0 0x1a000000 0 0x1000>;
Dmediatek,ssusbsys.txt22 reg = <0 0x1a000000 0 0x1000>;
Dmediatek,hifsys.txt23 reg = <0 0x1a000000 0 0x1000>;
/kernel/linux/linux-5.10/arch/mips/boot/dts/loongson/
Drs780e-pch.dtsi8 ranges = <0 0x10000000 0 0x10000000 0 0x10000000
9 0 0x40000000 0 0x40000000 0 0x40000000
10 0xfd 0xfe000000 0xfd 0xfe000000 0 0x2000000 /* PCI Config Space */>;
18 reg = <0 0x1a000000 0 0x02000000>;
20 ranges = <0x01000000 0 0x00004000 0 0x18004000 0 0x0000c000>,
21 <0x02000000 0 0x40000000 0 0x40000000 0 0x40000000>;
28 ranges = <1 0 0 0x18000000 0x4000>;
32 reg = <1 0x70 0x8>;
39 reg = <1 0x800 0x100>;
Dloongson64v_4core_virtio.dts12 #address-cells = <0>;
22 ranges = <0 0x1fe00000 0 0x1fe00000 0x100000
23 0 0x3ff00000 0 0x3ff00000 0x100000
24 0xefd 0xfb000000 0xefd 0xfb000000 0x10000000>;
28 reg = <0 0x3ff01400 0x64>;
37 loongson,parent_int_map = <0x00000001>, /* int0 */
38 <0xfffffffe>, /* int1 */
39 <0x00000000>, /* int2 */
40 <0x00000000>; /* int3 */
46 reg = <0 0x1fe001e0 0x8>;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/
Dloongson.yaml57 reg = <0x0 0x1a000000 0x0 0x2000000>;
60 ranges = <0x01000000 0x0 0x00004000 0x0 0x00004000 0x0 0x00004000>,
61 <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>;
/kernel/linux/linux-4.19/arch/mips/pci/
Dpci-lasat.c21 .start = 0x18000000,
22 .end = 0x19ffffff,
28 .start = 0x1a000000,
29 .end = 0x1bffffff,
49 return 0; in lasat_pci_setup()
54 #define LASAT_IRQ_ETH1 (LASAT_IRQ_BASE + 0)
74 return LASAT_IRQ_ETH0; /* Ethernet 0 (LAN 1) */ in pcibios_map_irq()
78 return 0xff; /* Illegal */ in pcibios_map_irq()
87 return 0; in pcibios_plat_dev_init()
Dops-loongson3.c10 #define PCI_ACCESS_READ 0
13 #define HT1LO_PCICFG_BASE 0x1a000000
14 #define HT1LO_PCICFG_BASE_TP1 0x1b000000
28 if (busnum == 0) { in loongson3_pci_config_access()
31 addrp = (void *)(TO_UNCAC(HT1LO_PCICFG_BASE) | (addr & 0xffff)); in loongson3_pci_config_access()
32 type = 0; in loongson3_pci_config_access()
36 type = 0x10000; in loongson3_pci_config_access()
43 if (*data == 0xffffffff) { in loongson3_pci_config_access()
54 u32 data = 0; in loongson3_pci_pcibios_read()
62 *val = (data >> ((where & 3) << 3)) & 0xff; in loongson3_pci_pcibios_read()
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/memory-controllers/
Dingenic,jz4780-nemc.txt16 <cs number> 0 <physical address of mapping> <size of mapping>
49 reg = <0x13410000 0x10000>;
54 ranges = <1 0 0x1b000000 0x1000000
55 2 0 0x1a000000 0x1000000
56 3 0 0x19000000 0x1000000
57 4 0 0x18000000 0x1000000
58 5 0 0x17000000 0x1000000
59 6 0 0x16000000 0x1000000>;
65 reg = <1 0 0x1000000>;
/kernel/linux/linux-4.19/arch/arm/boot/dts/
Dintegrator.dtsi11 reg = <0x10000000 0x200>;
14 led@c.0 {
16 offset = <0x0c>;
17 mask = <0x01>;
26 reg = <0x12000000 0x100>;
30 reg = <0x13000000 0x100>;
36 reg = <0x13000100 0x100>;
42 reg = <0x13000200 0x100>;
51 reg = <0x14000000 0x100>;
52 clear-mask = <0xffffffff>;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/
Dingenic,nemc.yaml14 pattern: "^memory-controller@[0-9a-f]+$"
40 ".*@[0-9]+$":
91 reg = <0x13410000 0x10000>;
94 ranges = <1 0 0x1b000000 0x1000000>,
95 <2 0 0x1a000000 0x1000000>,
96 <3 0 0x19000000 0x1000000>,
97 <4 0 0x18000000 0x1000000>,
98 <5 0 0x17000000 0x1000000>,
99 <6 0 0x16000000 0x1000000>;
108 pinctrl-0 = <&pins_nemc_cs6>;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mtd/
Dingenic,nand.yaml61 reg = <0x13410000 0x10000>;
64 ranges = <1 0 0x1b000000 0x1000000>,
65 <2 0 0x1a000000 0x1000000>,
66 <3 0 0x19000000 0x1000000>,
67 <4 0 0x18000000 0x1000000>,
68 <5 0 0x17000000 0x1000000>,
69 <6 0 0x16000000 0x1000000>;
75 reg = <1 0 0x1000000>;
78 #size-cells = <0>;
89 pinctrl-0 = <&pins_nemc>;
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dintegrator.dtsi12 reg = <0x0 0x0>;
17 reg = <0x10000000 0x200>;
20 led@c.0 {
22 offset = <0x0c>;
23 mask = <0x01>;
32 reg = <0x12000000 0x100>;
36 reg = <0x13000000 0x100>;
42 reg = <0x13000100 0x100>;
48 reg = <0x13000200 0x100>;
57 reg = <0x14000000 0x100>;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/dsa/
Dar9331.txt26 reg = <0x19000000 0x200>;
40 reg = <0x1a000000 0x200>;
56 #size-cells = <0>;
60 #size-cells = <0>;
63 reg = <0x10>;
75 #size-cells = <0>;
77 switch_port0: port@0 {
78 reg = <0x0>;
91 reg = <0x1>;
97 reg = <0x2>;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dqca,ar71xx.yaml43 const: 0
82 reg = <0x19000000 0x200>;
95 reg = <0x1a000000 0x200>;
113 #size-cells = <0>;
117 #size-cells = <0>;
120 reg = <0x10>;
132 #size-cells = <0>;
134 switch_port0: port@0 {
135 reg = <0x0>;
148 reg = <0x1>;
[all …]
/kernel/linux/linux-5.10/arch/mips/alchemy/devboards/
Ddb1000.c50 return 0; in db1000_board_setup()
57 if ((slot < 12) || (slot > 13) || pin == 0) in db1500_map_pci_irq()
60 return (pin == 1) ? AU1500_PCI_INTA : 0xff; in db1500_map_pci_irq()
75 [0] = {
77 .end = AU1500_PCI_PHYS_ADDR + 0xfff,
89 .id = 0,
100 [0] = {
102 .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1,
114 .id = 0,
124 [0] = {
[all …]
/kernel/linux/linux-5.10/arch/powerpc/boot/dts/
Dmpc7448hpc2.dts29 #size-cells =<0>;
31 PowerPC,7448@0 {
33 reg = <0x0>;
36 d-cache-size = <0x8000>; // L1, 32K bytes
37 i-cache-size = <0x8000>; // L1, 32K bytes
38 timebase-frequency = <0>; // 33 MHz, from uboot
39 clock-frequency = <0>; // From U-Boot
40 bus-frequency = <0>; // From U-Boot
46 reg = <0x0 0x20000000 // DDR2 512M at 0
54 ranges = <0x0 0xc0000000 0x10000>;
[all …]
/kernel/linux/linux-4.19/arch/mips/alchemy/devboards/
Ddb1000.c63 return 0; in db1000_board_setup()
70 if ((slot < 12) || (slot > 13) || pin == 0) in db1500_map_pci_irq()
73 return (pin == 1) ? AU1500_PCI_INTA : 0xff; in db1500_map_pci_irq()
86 [0] = {
88 .end = AU1500_PCI_PHYS_ADDR + 0xfff,
100 .id = 0,
111 [0] = {
113 .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1,
127 .id = 0,
137 [0] = {
[all …]
/kernel/linux/linux-4.19/arch/powerpc/boot/dts/
Dmpc7448hpc2.dts33 #size-cells =<0>;
35 PowerPC,7448@0 {
37 reg = <0x0>;
40 d-cache-size = <0x8000>; // L1, 32K bytes
41 i-cache-size = <0x8000>; // L1, 32K bytes
42 timebase-frequency = <0>; // 33 MHz, from uboot
43 clock-frequency = <0>; // From U-Boot
44 bus-frequency = <0>; // From U-Boot
50 reg = <0x0 0x20000000 // DDR2 512M at 0
58 ranges = <0x0 0xc0000000 0x10000>;
[all …]
/kernel/linux/linux-5.10/arch/powerpc/boot/dts/fsl/
Dmpc8536ds.dtsi36 nor@0,0 {
40 reg = <0x0 0x0 0x8000000>;
44 partition@0 {
45 reg = <0x0 0x03000000>;
50 reg = <0x03000000 0x00e00000>;
56 reg = <0x03e00000 0x00200000>;
62 reg = <0x04000000 0x00400000>;
67 reg = <0x04400000 0x03b00000>;
72 reg = <0x07f00000 0x00080000>;
77 reg = <0x07f80000 0x00080000>;
[all …]
/kernel/linux/linux-4.19/arch/powerpc/boot/dts/fsl/
Dmpc8536ds.dtsi36 nor@0,0 {
40 reg = <0x0 0x0 0x8000000>;
44 partition@0 {
45 reg = <0x0 0x03000000>;
50 reg = <0x03000000 0x00e00000>;
56 reg = <0x03e00000 0x00200000>;
62 reg = <0x04000000 0x00400000>;
67 reg = <0x04400000 0x03b00000>;
72 reg = <0x07f00000 0x00080000>;
77 reg = <0x07f80000 0x00080000>;
[all …]
/kernel/linux/linux-5.10/arch/mips/loongson64/
Denv.c24 #define HOST_BRIDGE_CONFIG_ADDR ((void __iomem *)TO_UNCAC(0x1a000000))
31 u64 loongson_chipcfg[MAX_PACKAGES] = {0xffffffffbfc00180};
72 smp_group[0] = 0x900000003ff01000; in prom_init_env()
73 smp_group[1] = 0x900010003ff01000; in prom_init_env()
74 smp_group[2] = 0x900020003ff01000; in prom_init_env()
75 smp_group[3] = 0x900030003ff01000; in prom_init_env()
76 loongson_chipcfg[0] = 0x900000001fe00180; in prom_init_env()
77 loongson_chipcfg[1] = 0x900010001fe00180; in prom_init_env()
78 loongson_chipcfg[2] = 0x900020001fe00180; in prom_init_env()
79 loongson_chipcfg[3] = 0x900030001fe00180; in prom_init_env()
[all …]
/kernel/linux/linux-5.10/arch/mips/boot/dts/qca/
Dar9331.dtsi12 #size-cells = <0>;
14 cpu@0 {
18 reg = <0>;
34 #clock-cells = <0>;
57 reg = <0x18000000 0x100>;
64 reg = <0x18020000 0x14>;
76 reg = <0x18040000 0x34>;
92 reg = <0x18050000 0x100>;
102 reg = <0x18060010 0x8>;
113 reg = <0x1806001c 0x4>;
[all …]

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