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/kernel/linux/linux-5.10/drivers/media/usb/gspca/
Dsunplus.c29 #define BRIDGE_SPCA504 0
113 /* {0xa0, 0x0000, 0x0503}, * capture mode */
114 {0x00, 0x0000, 0x2000},
115 {0x00, 0x0013, 0x2301},
116 {0x00, 0x0003, 0x2000},
117 {0x00, 0x0001, 0x21ac},
118 {0x00, 0x0001, 0x21a6},
119 {0x00, 0x0000, 0x21a7}, /* brightness */
120 {0x00, 0x0020, 0x21a8}, /* contrast */
121 {0x00, 0x0001, 0x21ac}, /* sat/hue */
[all …]
Dspca500.c26 #define AgfaCl20 0
55 .priv = 0},
68 .priv = 0},
87 {0x00, 0x0003, 0x816b}, /* SSI not active sync with vsync,
88 * hue (H byte) = 0,
92 {0x00, 0x0000, 0x8167}, /* brightness = 0 */
93 {0x00, 0x0020, 0x8168}, /* contrast = 0 */
94 {0x00, 0x0003, 0x816b}, /* SSI not active sync with vsync,
95 * hue (H byte) = 0, saturation/hue enable,
97 * was 0x0003, now 0x0000.
[all …]
/kernel/linux/linux-4.19/drivers/media/usb/gspca/
Dsunplus.c38 #define BRIDGE_SPCA504 0
122 /* {0xa0, 0x0000, 0x0503}, * capture mode */
123 {0x00, 0x0000, 0x2000},
124 {0x00, 0x0013, 0x2301},
125 {0x00, 0x0003, 0x2000},
126 {0x00, 0x0001, 0x21ac},
127 {0x00, 0x0001, 0x21a6},
128 {0x00, 0x0000, 0x21a7}, /* brightness */
129 {0x00, 0x0020, 0x21a8}, /* contrast */
130 {0x00, 0x0001, 0x21ac}, /* sat/hue */
[all …]
Dspca500.c36 #define AgfaCl20 0
65 .priv = 0},
78 .priv = 0},
97 {0x00, 0x0003, 0x816b}, /* SSI not active sync with vsync,
98 * hue (H byte) = 0,
102 {0x00, 0x0000, 0x8167}, /* brightness = 0 */
103 {0x00, 0x0020, 0x8168}, /* contrast = 0 */
104 {0x00, 0x0003, 0x816b}, /* SSI not active sync with vsync,
105 * hue (H byte) = 0, saturation/hue enable,
107 * was 0x0003, now 0x0000.
[all …]
/kernel/linux/linux-4.19/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x_dump.h22 #define DRV_DUMP_XSTORM_WAITP_ADDRESS 0x2b8a80
23 #define DRV_DUMP_TSTORM_WAITP_ADDRESS 0x1b8a80
24 #define DRV_DUMP_USTORM_WAITP_ADDRESS 0x338a80
25 #define DRV_DUMP_CSTORM_WAITP_ADDRESS 0x238a80
45 #define BNX2X_DUMP_VERSION 0x61111111
65 static const u32 page_vals_e2[] = {0, 128};
68 {0x58000, 4608, DUMP_CHIP_E2, 0x30}
74 static const u32 page_vals_e3[] = {0, 128};
77 {0x58000, 4608, DUMP_CHIP_E3A0 | DUMP_CHIP_E3B0, 0x30}
81 { 0x2000, 1, 0x1f, 0xfff},
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x_dump.h22 #define DRV_DUMP_XSTORM_WAITP_ADDRESS 0x2b8a80
23 #define DRV_DUMP_TSTORM_WAITP_ADDRESS 0x1b8a80
24 #define DRV_DUMP_USTORM_WAITP_ADDRESS 0x338a80
25 #define DRV_DUMP_CSTORM_WAITP_ADDRESS 0x238a80
45 #define BNX2X_DUMP_VERSION 0x61111111
65 static const u32 page_vals_e2[] = {0, 128};
68 {0x58000, 4608, DUMP_CHIP_E2, 0x30}
74 static const u32 page_vals_e3[] = {0, 128};
77 {0x58000, 4608, DUMP_CHIP_E3A0 | DUMP_CHIP_E3B0, 0x30}
81 { 0x2000, 1, 0x1f, 0xfff},
[all …]
/kernel/linux/linux-5.10/drivers/media/dvb-frontends/
Dstv0900_init.h24 { 0, 11101 }, /*C/N=-0dB*/
83 { -5, 0xCAA1 }, /*-5dBm*/
84 { -10, 0xC229 }, /*-10dBm*/
85 { -15, 0xBB08 }, /*-15dBm*/
86 { -20, 0xB4BC }, /*-20dBm*/
87 { -25, 0xAD5A }, /*-25dBm*/
88 { -30, 0xA298 }, /*-30dBm*/
89 { -35, 0x98A8 }, /*-35dBm*/
90 { -40, 0x8389 }, /*-40dBm*/
91 { -45, 0x59BE }, /*-45dBm*/
[all …]
/kernel/linux/linux-4.19/drivers/media/dvb-frontends/
Dstv0900_init.h34 { 0, 11101 }, /*C/N=-0dB*/
93 { -5, 0xCAA1 }, /*-5dBm*/
94 { -10, 0xC229 }, /*-10dBm*/
95 { -15, 0xBB08 }, /*-15dBm*/
96 { -20, 0xB4BC }, /*-20dBm*/
97 { -25, 0xAD5A }, /*-25dBm*/
98 { -30, 0xA298 }, /*-30dBm*/
99 { -35, 0x98A8 }, /*-35dBm*/
100 { -40, 0x8389 }, /*-40dBm*/
101 { -45, 0x59BE }, /*-45dBm*/
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/athub/
Dathub_1_0_sh_mask.h27 #define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x0
28 #define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x1
29 #define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x2
30 #define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x8
31 #define ATC_ATS_CNTL__INVALIDATION_LOG_KEEP_ORDER__SHIFT 0x14
32 #define ATC_ATS_CNTL__TRANS_LOG_KEEP_ORDER__SHIFT 0x15
33 #define ATC_ATS_CNTL__TRANS_EXE_RETURN__SHIFT 0x16
34 #define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x00000001L
35 #define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x00000002L
36 #define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x00000004L
[all …]
Dathub_2_0_0_sh_mask.h27 …S_CNTL__DISABLE_ATC__SHIFT 0x0
28 …S_CNTL__DISABLE_PRI__SHIFT 0x1
29 …S_CNTL__DISABLE_PASID__SHIFT 0x2
30 …S_CNTL__CREDITS_ATS_RPB__SHIFT 0x8
31 …_CNTL__INVALIDATION_LOG_KEEP_ORDER__SHIFT 0x14
32 …_CNTL__TRANS_LOG_KEEP_ORDER__SHIFT 0x15
33 …_CNTL__TRANS_EXE_RETURN__SHIFT 0x16
34 …DISABLE_ATC_MASK 0x00000001L
35 …DISABLE_PRI_MASK 0x00000002L
36 …DISABLE_PASID_MASK 0x00000004L
[all …]
Dathub_2_1_0_sh_mask.h27 …ATS_MODE_CNTL__HOST_TRANS_ENABLE__SHIFT 0x0
28 …ATS_MODE_CNTL__CONSOLE_IOV_ENABLE__SHIFT 0x1
29 …_CNTL__HOST_TRANS_ENABLE_MASK 0x00000001L
30 …_CNTL__CONSOLE_IOV_ENABLE_MASK 0x00000002L
32 …SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0
33 …HARED_VIRT_RESET_REQ__PF__SHIFT 0x1f
34 …IRT_RESET_REQ__VF_MASK 0x7FFFFFFFL
35 …IRT_RESET_REQ__PF_MASK 0x80000000L
37 …SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0
38 …HARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/amd/include/asic_reg/athub/
Dathub_1_0_sh_mask.h27 #define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x0
28 #define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x1
29 #define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x2
30 #define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x8
31 #define ATC_ATS_CNTL__INVALIDATION_LOG_KEEP_ORDER__SHIFT 0x14
32 #define ATC_ATS_CNTL__TRANS_LOG_KEEP_ORDER__SHIFT 0x15
33 #define ATC_ATS_CNTL__TRANS_EXE_RETURN__SHIFT 0x16
34 #define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x00000001L
35 #define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x00000002L
36 #define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x00000004L
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/panel/
Dpanel-feixin-k101-im2ba02.c43 /* Switch to page 0 */
44 { .data = { 0xE0, 0x00 } },
47 { .data = { 0xE1, 0x93} },
48 { .data = { 0xE2, 0x65 } },
49 { .data = { 0xE3, 0xF8 } },
51 /* Lane number, 0x02 - 3 lanes, 0x03 - 4 lanes */
52 { .data = { 0x80, 0x03 } },
55 { .data = { 0x70, 0x02 } },
56 { .data = { 0x71, 0x23 } },
57 { .data = { 0x72, 0x06 } },
[all …]
/kernel/linux/linux-4.19/arch/arm/mach-imx/
Dmach-imx7d.c25 phy_write(dev, 0x1d, 0x1f); in ar8031_phy_fixup()
26 phy_write(dev, 0x1e, 0x8); in ar8031_phy_fixup()
29 phy_write(dev, 0xd, 0x3); in ar8031_phy_fixup()
30 phy_write(dev, 0xe, 0x805d); in ar8031_phy_fixup()
31 phy_write(dev, 0xd, 0x4003); in ar8031_phy_fixup()
32 val = phy_read(dev, 0xe); in ar8031_phy_fixup()
33 val &= ~(0x1 << 8); in ar8031_phy_fixup()
34 phy_write(dev, 0xe, val); in ar8031_phy_fixup()
37 phy_write(dev, 0x1d, 0x5); in ar8031_phy_fixup()
38 val = phy_read(dev, 0x1e); in ar8031_phy_fixup()
[all …]
/kernel/linux/linux-5.10/crypto/
Dtestmgr.h33 * @ksize: Length of @key in bytes (0 if no key)
101 * @crypt_error: When @novrfy=0, the expected error from encrypt(). When
192 "\x9C\xE6\x16\xCE\x62\x4A\x11\xE0\x08\x6D\x34\x1E\xBC\xAC\xA0\xA1"
210 "\x9f\x6e\xbd\x4c\x55\x84\x0c\x9b\xcf\x1a\x4b\x51\x1e\x9e\x0c\x06",
231 "\xF8\x3F\x31\x25\x1E\x06\x68\xB4\x27\x84\x81\x38\x01\x57\x96\x41"
265 "\xC6\x67\xFF\x1D\x1E\x3C\x1D\xC1\xB5\x5F\x6C\xC0\xB2\x07\x3A\x6D"
288 "\x9A\xB8\x81\xE2\xD0\x07\x35\xAA\x05\x41\xC9\x1E\xAF\xE4\x04\x3B"
289 "\x19\xB8\x73\xA2\xAC\x4B\x1E\x66\x48\xD8\x72\x1F\xAC\xF6\xCB\xBC"
295 "\xD6\xBF\x7A\x0B\x64\x21\x6D\x88\x7E\x5B\x45\x12\x1E\x63\x8D\x49"
296 "\xA7\x1D\xD9\x1E\x06\xCD\xE8\xBA\x2C\x8C\x69\x32\xEA\xBE\x60\x71"
[all …]
/kernel/linux/linux-5.10/drivers/media/tuners/
Dqt1010.c16 .flags = 0, .buf = &reg, .len = 1 }, in qt1010_readreg()
26 return 0; in qt1010_readreg()
34 .flags = 0, .buf = buf, .len = 2 }; in qt1010_writereg()
41 return 0; in qt1010_writereg()
52 { QT1010_WR, 0x01, 0x80 }, in qt1010_set_params()
53 { QT1010_WR, 0x02, 0x3f }, in qt1010_set_params()
54 { QT1010_WR, 0x05, 0xff }, /* 02 c write */ in qt1010_set_params()
55 { QT1010_WR, 0x06, 0x44 }, in qt1010_set_params()
56 { QT1010_WR, 0x07, 0xff }, /* 04 c write */ in qt1010_set_params()
57 { QT1010_WR, 0x08, 0x08 }, in qt1010_set_params()
[all …]
/kernel/linux/linux-4.19/drivers/media/tuners/
Dqt1010.c25 .flags = 0, .buf = &reg, .len = 1 }, in qt1010_readreg()
35 return 0; in qt1010_readreg()
43 .flags = 0, .buf = buf, .len = 2 }; in qt1010_writereg()
50 return 0; in qt1010_writereg()
61 { QT1010_WR, 0x01, 0x80 }, in qt1010_set_params()
62 { QT1010_WR, 0x02, 0x3f }, in qt1010_set_params()
63 { QT1010_WR, 0x05, 0xff }, /* 02 c write */ in qt1010_set_params()
64 { QT1010_WR, 0x06, 0x44 }, in qt1010_set_params()
65 { QT1010_WR, 0x07, 0xff }, /* 04 c write */ in qt1010_set_params()
66 { QT1010_WR, 0x08, 0x08 }, in qt1010_set_params()
[all …]
/kernel/linux/linux-4.19/drivers/infiniband/hw/qib/
Dqib_6120_regs.h35 #define QIB_6120_Revision_OFFS 0x0
36 #define QIB_6120_Revision_R_Simulator_LSB 0x3F
37 #define QIB_6120_Revision_R_Simulator_RMASK 0x1
38 #define QIB_6120_Revision_Reserved_LSB 0x28
39 #define QIB_6120_Revision_Reserved_RMASK 0x7FFFFF
40 #define QIB_6120_Revision_BoardID_LSB 0x20
41 #define QIB_6120_Revision_BoardID_RMASK 0xFF
42 #define QIB_6120_Revision_R_SW_LSB 0x18
43 #define QIB_6120_Revision_R_SW_RMASK 0xFF
44 #define QIB_6120_Revision_R_Arch_LSB 0x10
[all …]
/kernel/linux/linux-5.10/drivers/infiniband/hw/qib/
Dqib_6120_regs.h35 #define QIB_6120_Revision_OFFS 0x0
36 #define QIB_6120_Revision_R_Simulator_LSB 0x3F
37 #define QIB_6120_Revision_R_Simulator_RMASK 0x1
38 #define QIB_6120_Revision_Reserved_LSB 0x28
39 #define QIB_6120_Revision_Reserved_RMASK 0x7FFFFF
40 #define QIB_6120_Revision_BoardID_LSB 0x20
41 #define QIB_6120_Revision_BoardID_RMASK 0xFF
42 #define QIB_6120_Revision_R_SW_LSB 0x18
43 #define QIB_6120_Revision_R_SW_RMASK 0xFF
44 #define QIB_6120_Revision_R_Arch_LSB 0x10
[all …]
/kernel/linux/linux-4.19/crypto/
Dtestmgr.h167 "\x9C\xE6\x16\xCE\x62\x4A\x11\xE0\x08\x6D\x34\x1E\xBC\xAC\xA0\xA1"
185 "\x9f\x6e\xbd\x4c\x55\x84\x0c\x9b\xcf\x1a\x4b\x51\x1e\x9e\x0c\x06",
206 "\xF8\x3F\x31\x25\x1E\x06\x68\xB4\x27\x84\x81\x38\x01\x57\x96\x41"
240 "\xC6\x67\xFF\x1D\x1E\x3C\x1D\xC1\xB5\x5F\x6C\xC0\xB2\x07\x3A\x6D"
263 "\x9A\xB8\x81\xE2\xD0\x07\x35\xAA\x05\x41\xC9\x1E\xAF\xE4\x04\x3B"
264 "\x19\xB8\x73\xA2\xAC\x4B\x1E\x66\x48\xD8\x72\x1F\xAC\xF6\xCB\xBC"
270 "\xD6\xBF\x7A\x0B\x64\x21\x6D\x88\x7E\x5B\x45\x12\x1E\x63\x8D\x49"
271 "\xA7\x1D\xD9\x1E\x06\xCD\xE8\xBA\x2C\x8C\x69\x32\xEA\xBE\x60\x71"
304 "\xC6\x67\xFF\x1D\x1E\x3C\x1D\xC1\xB5\x5F\x6C\xC0\xB2\x07\x3A\x6D"
357 "\xAC\x82\x38\xB4\xDD\x4C\x04\x7E\x51\x36\x40\x1E\x0B\xC4\x7C\x25"
[all …]
/kernel/linux/linux-5.10/arch/powerpc/boot/dts/fsl/
Dt2081qds.dts104 #size-cells = <0>;
105 reg = <0x54 1>;
106 mux-mask = <0xe0>;
108 t2081mdio0: mdio@0 {
110 #size-cells = <0>;
111 reg = <0>;
114 reg = <0x1>;
120 #size-cells = <0>;
121 reg = <0x20>;
124 reg = <0x2>;
[all …]
/kernel/linux/linux-4.19/arch/powerpc/boot/dts/fsl/
Dt2081qds.dts104 #size-cells = <0>;
105 reg = <0x54 1>;
106 mux-mask = <0xe0>;
108 t2081mdio0: mdio@0 {
110 #size-cells = <0>;
111 reg = <0>;
114 reg = <0x1>;
120 #size-cells = <0>;
121 reg = <0x20>;
124 reg = <0x2>;
[all …]
/kernel/linux/linux-4.19/sound/soc/amd/include/
Dacp_2_2_sh_mask.h27 #define ACP_DMA_CNTL_0__DMAChRst_MASK 0x1
28 #define ACP_DMA_CNTL_0__DMAChRst__SHIFT 0x0
29 #define ACP_DMA_CNTL_0__DMAChRun_MASK 0x2
30 #define ACP_DMA_CNTL_0__DMAChRun__SHIFT 0x1
31 #define ACP_DMA_CNTL_0__DMAChIOCEn_MASK 0x4
32 #define ACP_DMA_CNTL_0__DMAChIOCEn__SHIFT 0x2
33 #define ACP_DMA_CNTL_0__Circular_DMA_En_MASK 0x8
34 #define ACP_DMA_CNTL_0__Circular_DMA_En__SHIFT 0x3
35 #define ACP_DMA_CNTL_0__DMAChGracefulRstEn_MASK 0x10
36 #define ACP_DMA_CNTL_0__DMAChGracefulRstEn__SHIFT 0x4
[all …]
/kernel/linux/linux-5.10/sound/soc/amd/include/
Dacp_2_2_sh_mask.h27 #define ACP_DMA_CNTL_0__DMAChRst_MASK 0x1
28 #define ACP_DMA_CNTL_0__DMAChRst__SHIFT 0x0
29 #define ACP_DMA_CNTL_0__DMAChRun_MASK 0x2
30 #define ACP_DMA_CNTL_0__DMAChRun__SHIFT 0x1
31 #define ACP_DMA_CNTL_0__DMAChIOCEn_MASK 0x4
32 #define ACP_DMA_CNTL_0__DMAChIOCEn__SHIFT 0x2
33 #define ACP_DMA_CNTL_0__Circular_DMA_En_MASK 0x8
34 #define ACP_DMA_CNTL_0__Circular_DMA_En__SHIFT 0x3
35 #define ACP_DMA_CNTL_0__DMAChGracefulRstEn_MASK 0x10
36 #define ACP_DMA_CNTL_0__DMAChGracefulRstEn__SHIFT 0x4
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_5_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]

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