| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/nvmem/ |
| D | qcom,qfprom.yaml | 64 reg = <0 0x00784000 0 0x8ff>,
65 <0 0x00780000 0 0x7a0>,
66 <0 0x00782000 0 0x100>,
67 <0 0x00786000 0 0x1fff>;
76 reg = <0x25b 0x1>;
89 reg = <0 0x00784000 0 0x8ff>;
94 reg = <0x1eb 0x1>;
|
| /kernel/linux/linux-5.10/drivers/staging/rtl8188eu/include/ |
| D | hal8188e_phy_cfg.h | 12 #define AntennaDiversityValue 0x80
16 #define MAX_AGGR_NUM 0x07
37 HW90_BLOCK_MAC = 0,
45 RF_PATH_A = 0, /* Radio Path A */
63 WIRELESS_MODE_UNKNOWN = 0x00,
65 WIRELESS_MODE_B = BIT(0),
85 /* 0x870~0x877[8 bytes] */
87 /* 0x8e0~0x8e7[8 bytes] */
89 /* 0x860~0x86f [16 bytes] */
91 /* 0x860~0x86f [16 bytes] */
[all …]
|
| /kernel/linux/linux-4.19/arch/x86/include/uapi/asm/ |
| D | bootparam.h | 6 #define SETUP_NONE 0
15 #define RAMDISK_IMAGE_START_MASK 0x07FF
16 #define RAMDISK_PROMPT_FLAG 0x8000
17 #define RAMDISK_LOAD_FLAG 0x4000
20 #define LOADED_HIGH (1<<0)
27 #define XLF_KERNEL_64 (1<<0)
47 __u8 data[0];
153 struct screen_info screen_info; /* 0x000 */
154 struct apm_bios_info apm_bios_info; /* 0x040 */
155 __u8 _pad2[4]; /* 0x054 */
[all …]
|
| /kernel/linux/linux-5.10/arch/x86/include/uapi/asm/ |
| D | bootparam.h | 6 #define SETUP_NONE 0
20 #define RAMDISK_IMAGE_START_MASK 0x07FF
21 #define RAMDISK_PROMPT_FLAG 0x8000
22 #define RAMDISK_LOAD_FLAG 0x4000
25 #define LOADED_HIGH (1<<0)
32 #define XLF_KERNEL_64 (1<<0)
54 __u8 data[0];
176 struct screen_info screen_info; /* 0x000 */
177 struct apm_bios_info apm_bios_info; /* 0x040 */
178 __u8 _pad2[4]; /* 0x054 */
[all …]
|
| /kernel/linux/linux-4.19/drivers/staging/rtl8188eu/include/ |
| D | hal8188e_phy_cfg.h | 14 #define AntennaDiversityValue 0x80
23 #define MAX_AGGR_NUM 0x07
49 HW90_BLOCK_MAC = 0,
57 RF_PATH_A = 0, /* Radio Path A */
75 WIRELESS_MODE_UNKNOWN = 0x00,
77 WIRELESS_MODE_B = BIT(0),
97 /* 0x870~0x877[8 bytes] */
99 /* 0x8e0~0x8e7[8 bytes] */
101 /* 0x860~0x86f [16 bytes] */
103 /* 0x860~0x86f [16 bytes] */
[all …]
|
| /kernel/linux/linux-5.10/drivers/net/wireless/realtek/rtw88/ |
| D | rtw8822c.h | 11 u8 res0[0x30]; /* 0x120 */
12 u8 vid[2]; /* 0x150 */
15 u8 mac_addr[ETH_ALEN]; /* 0x157 */
16 u8 res2[0x3d];
20 u8 mac_addr[ETH_ALEN]; /* 0x120 */
28 u8 ltr_cap; /* 0x133 */
33 u8 res0:2; /* 0x144 */
57 u8 res0[0x0e];
62 u8 channel_plan; /* 0xb8 */
66 u8 res2[5]; /* 0xbc */
[all …]
|
| /kernel/linux/linux-5.10/include/linux/mfd/ |
| D | intel_msic.h | 13 #define INTEL_MSIC_ID0 0x000 /* RO */
14 #define INTEL_MSIC_ID1 0x001 /* RO */
17 #define INTEL_MSIC_IRQLVL1 0x002
18 #define INTEL_MSIC_ADC1INT 0x003
19 #define INTEL_MSIC_CCINT 0x004
20 #define INTEL_MSIC_PWRSRCINT 0x005
21 #define INTEL_MSIC_PWRSRCINT1 0x006
22 #define INTEL_MSIC_CHRINT 0x007
23 #define INTEL_MSIC_CHRINT1 0x008
24 #define INTEL_MSIC_RTCIRQ 0x009
[all …]
|
| /kernel/linux/linux-4.19/include/linux/mfd/ |
| D | intel_msic.h | 16 #define INTEL_MSIC_ID0 0x000 /* RO */
17 #define INTEL_MSIC_ID1 0x001 /* RO */
20 #define INTEL_MSIC_IRQLVL1 0x002
21 #define INTEL_MSIC_ADC1INT 0x003
22 #define INTEL_MSIC_CCINT 0x004
23 #define INTEL_MSIC_PWRSRCINT 0x005
24 #define INTEL_MSIC_PWRSRCINT1 0x006
25 #define INTEL_MSIC_CHRINT 0x007
26 #define INTEL_MSIC_CHRINT1 0x008
27 #define INTEL_MSIC_RTCIRQ 0x009
[all …]
|
| /kernel/linux/linux-4.19/Documentation/vm/ |
| D | slub.rst | 127 .. slub_min_order=x (default 0)
147 ``debug_guardpage_minorder=N`` (N > 0), forces setting
148 ``slub_max_order`` to 0, what cause minimum possible order of
160 INFO: 0xc90f6d28-0xc90f6d2b. First byte 0x00 instead of 0xcc
161 INFO: Slab 0xc528c530 flags=0x400000c3 inuse=61 fp=0xc90f6d58
162 INFO: Object 0xc90f6d20 @offset=3360 fp=0xc90f6d58
163 INFO: Allocated in get_modalias+0x61/0xf5 age=53 cpu=1 pid=554
165 Bytes b4 0xc90f6d10: 00 00 00 00 00 00 00 00 5a 5a 5a 5a 5a 5a 5a 5a ........ZZZZZZZZ
166 Object 0xc90f6d20: 31 30 31 39 2e 30 30 35 1019.005
167 Redzone 0xc90f6d28: 00 cc cc cc .
[all …]
|
| /kernel/linux/linux-4.19/drivers/gpu/drm/amd/include/asic_reg/smu/ |
| D | smu_8_0_d.h | 27 #define ixTHM_TCON_CSR_CONFIG 0xd82014a4
28 #define ixTHM_TCON_CSR_DATA 0xd82014a8
29 #define ixTHM_TCON_HTC 0xd8200c64
30 #define ixTHM_TCON_CUR_TMP 0xd8200ca4
31 #define ixTHM_TCON_THERM_TRIP 0xd8200ce4
32 #define ixTHM_GPIO_PROCHOT_CTRL 0xd8200d00
33 #define ixTHM_GPIO_THERMTRIP_CTRL 0xd8200d04
34 #define ixTHM_THERMAL_INT_ENA 0xd8200d10
35 #define ixTHM_THERMAL_INT_CTRL 0xd8200d14
36 #define ixTHM_THERMAL_INT_STATUS 0xd8200d18
[all …]
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/smu/ |
| D | smu_8_0_d.h | 27 #define ixTHM_TCON_CSR_CONFIG 0xd82014a4
28 #define ixTHM_TCON_CSR_DATA 0xd82014a8
29 #define ixTHM_TCON_HTC 0xd8200c64
30 #define ixTHM_TCON_CUR_TMP 0xd8200ca4
31 #define ixTHM_TCON_THERM_TRIP 0xd8200ce4
32 #define ixTHM_GPIO_PROCHOT_CTRL 0xd8200d00
33 #define ixTHM_GPIO_THERMTRIP_CTRL 0xd8200d04
34 #define ixTHM_THERMAL_INT_ENA 0xd8200d10
35 #define ixTHM_THERMAL_INT_CTRL 0xd8200d14
36 #define ixTHM_THERMAL_INT_STATUS 0xd8200d18
[all …]
|
| /kernel/linux/linux-5.10/Documentation/vm/ |
| D | slub.rst | 109 If the file contains 1, the option is enabled, 0 means disabled. The debug
154 .. slub_min_order=x (default 0)
174 ``debug_guardpage_minorder=N`` (N > 0), forces setting
175 ``slub_max_order`` to 0, what cause minimum possible order of
187 INFO: 0xc90f6d28-0xc90f6d2b. First byte 0x00 instead of 0xcc
188 INFO: Slab 0xc528c530 flags=0x400000c3 inuse=61 fp=0xc90f6d58
189 INFO: Object 0xc90f6d20 @offset=3360 fp=0xc90f6d58
190 INFO: Allocated in get_modalias+0x61/0xf5 age=53 cpu=1 pid=554
192 Bytes b4 (0xc90f6d10): 00 00 00 00 00 00 00 00 5a 5a 5a 5a 5a 5a 5a 5a ........ZZZZZZZZ
193 Object (0xc90f6d20): 31 30 31 39 2e 30 30 35 1019.005
[all …]
|
| /kernel/linux/linux-4.19/drivers/gpu/drm/amd/amdgpu/ |
| D | mmhub_v1_0.c | 35 #define mmDAGB0_CNTL_MISC2_RV 0x008f
36 #define mmDAGB0_CNTL_MISC2_RV_BASE_IDX 0
40 u64 base = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE); in mmhub_v1_0_get_fb_location()
52 BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL)); in mmhub_v1_0_init_gart_pt_regs()
55 value &= 0x0000FFFFFFFFF000ULL; in mmhub_v1_0_init_gart_pt_regs()
56 value |= 0x1; /* valid bit */ in mmhub_v1_0_init_gart_pt_regs()
58 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in mmhub_v1_0_init_gart_pt_regs()
61 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in mmhub_v1_0_init_gart_pt_regs()
69 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in mmhub_v1_0_init_gart_aperture_regs()
71 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in mmhub_v1_0_init_gart_aperture_regs()
[all …]
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/gmc/ |
| D | gmc_7_1_d.h | 27 #define mmMC_CONFIG 0x800
28 #define mmMC_ARB_AGE_CNTL 0x9bf
29 #define mmMC_ARB_RET_CREDITS2 0x9c0
30 #define mmMC_ARB_FED_CNTL 0x9c1
31 #define mmMC_ARB_GECC2_STATUS 0x9c2
32 #define mmMC_ARB_GECC2_MISC 0x9c3
33 #define mmMC_ARB_GECC2_DEBUG 0x9c4
34 #define mmMC_ARB_GECC2_DEBUG2 0x9c5
35 #define mmMC_ARB_PERF_CID 0x9c6
36 #define mmMC_ARB_GECC2 0x9c9
[all …]
|
| D | gmc_8_1_d.h | 27 #define mmMC_CONFIG 0x800
28 #define mmMC_ARB_ATOMIC 0x9be
29 #define mmMC_ARB_AGE_CNTL 0x9bf
30 #define mmMC_ARB_RET_CREDITS2 0x9c0
31 #define mmMC_ARB_FED_CNTL 0x9c1
32 #define mmMC_ARB_GECC2_STATUS 0x9c2
33 #define mmMC_ARB_GECC2_MISC 0x9c3
34 #define mmMC_ARB_GECC2_DEBUG 0x9c4
35 #define mmMC_ARB_GECC2_DEBUG2 0x9c5
36 #define mmMC_ARB_PERF_CID 0x9c6
[all …]
|
| /kernel/linux/linux-4.19/drivers/gpu/drm/amd/include/asic_reg/gmc/ |
| D | gmc_7_1_d.h | 27 #define mmMC_CONFIG 0x800
28 #define mmMC_ARB_AGE_CNTL 0x9bf
29 #define mmMC_ARB_RET_CREDITS2 0x9c0
30 #define mmMC_ARB_FED_CNTL 0x9c1
31 #define mmMC_ARB_GECC2_STATUS 0x9c2
32 #define mmMC_ARB_GECC2_MISC 0x9c3
33 #define mmMC_ARB_GECC2_DEBUG 0x9c4
34 #define mmMC_ARB_GECC2_DEBUG2 0x9c5
35 #define mmMC_ARB_PERF_CID 0x9c6
36 #define mmMC_ARB_GECC2 0x9c9
[all …]
|
| D | gmc_8_1_d.h | 27 #define mmMC_CONFIG 0x800
28 #define mmMC_ARB_ATOMIC 0x9be
29 #define mmMC_ARB_AGE_CNTL 0x9bf
30 #define mmMC_ARB_RET_CREDITS2 0x9c0
31 #define mmMC_ARB_FED_CNTL 0x9c1
32 #define mmMC_ARB_GECC2_STATUS 0x9c2
33 #define mmMC_ARB_GECC2_MISC 0x9c3
34 #define mmMC_ARB_GECC2_DEBUG 0x9c4
35 #define mmMC_ARB_GECC2_DEBUG2 0x9c5
36 #define mmMC_ARB_PERF_CID 0x9c6
[all …]
|
| /kernel/linux/linux-4.19/sound/drivers/opl4/ |
| D | opl4_synth.c | 41 #define MIDI_CTL_RELEASE_TIME 0x48
42 #define MIDI_CTL_ATTACK_TIME 0x49
43 #define MIDI_CTL_DECAY_TIME 0x4b
44 #define MIDI_CTL_VIBRATO_RATE 0x4c
45 #define MIDI_CTL_VIBRATO_DEPTH 0x4d
46 #define MIDI_CTL_VIBRATO_DELAY 0x4e
52 static const s16 snd_opl4_pitch_map[0x600] = {
53 0x000,0x000,0x001,0x001,0x002,0x002,0x003,0x003,
54 0x004,0x004,0x005,0x005,0x006,0x006,0x006,0x007,
55 0x007,0x008,0x008,0x009,0x009,0x00a,0x00a,0x00b,
[all …]
|
| /kernel/linux/linux-5.10/sound/drivers/opl4/ |
| D | opl4_synth.c | 41 #define MIDI_CTL_RELEASE_TIME 0x48
42 #define MIDI_CTL_ATTACK_TIME 0x49
43 #define MIDI_CTL_DECAY_TIME 0x4b
44 #define MIDI_CTL_VIBRATO_RATE 0x4c
45 #define MIDI_CTL_VIBRATO_DEPTH 0x4d
46 #define MIDI_CTL_VIBRATO_DELAY 0x4e
52 static const s16 snd_opl4_pitch_map[0x600] = {
53 0x000,0x000,0x001,0x001,0x002,0x002,0x003,0x003,
54 0x004,0x004,0x005,0x005,0x006,0x006,0x006,0x007,
55 0x007,0x008,0x008,0x009,0x009,0x00a,0x00a,0x00b,
[all …]
|
| /kernel/linux/linux-5.10/drivers/clk/renesas/ |
| D | r9a06g032-clocks.c | 37 uint32_t source : 8; /* source index + 1 (0 == none) */
90 enum { K_GATE = 0, K_FFC, K_DIV, K_BITSEL, K_DUALGATE };
93 #define R9A06G032_CLKOUT 0
138 D_DIV(CLKOUT_D1OR2, "clkout_d1or2", CLKOUT, 0, 1, 2),
159 D_GATE(CLK_25_PG4, "clk_25_pg4", CLKOUT_D40, 0x749, 0x74a, 0x74b, 0, 0xae3, 0, 0),
160 D_GATE(CLK_25_PG5, "clk_25_pg5", CLKOUT_D40, 0x74c, 0x74d, 0x74e, 0, 0xae4, 0, 0),
161 D_GATE(CLK_25_PG6, "clk_25_pg6", CLKOUT_D40, 0x74f, 0x750, 0x751, 0, 0xae5, 0, 0),
162 D_GATE(CLK_25_PG7, "clk_25_pg7", CLKOUT_D40, 0x752, 0x753, 0x754, 0, 0xae6, 0, 0),
163 D_GATE(CLK_25_PG8, "clk_25_pg8", CLKOUT_D40, 0x755, 0x756, 0x757, 0, 0xae7, 0, 0),
164 D_GATE(CLK_ADC, "clk_adc", DIV_ADC, 0x1ea, 0x1eb, 0, 0, 0, 0, 0),
[all …]
|
| /kernel/linux/linux-4.19/drivers/clk/renesas/ |
| D | r9a06g032-clocks.c | 33 uint32_t source : 8; /* source index + 1 (0 == none) */
82 enum { K_GATE = 0, K_FFC, K_DIV, K_BITSEL, K_DUALGATE };
85 #define R9A06G032_CLKOUT 0
130 D_DIV(CLKOUT_D1OR2, "clkout_d1or2", CLKOUT, 0, 1, 2),
151 D_GATE(CLK_25_PG4, "clk_25_pg4", CLKOUT_D40, 0x749, 0x74a, 0x74b, 0, 0xae3, 0, 0),
152 D_GATE(CLK_25_PG5, "clk_25_pg5", CLKOUT_D40, 0x74c, 0x74d, 0x74e, 0, 0xae4, 0, 0),
153 D_GATE(CLK_25_PG6, "clk_25_pg6", CLKOUT_D40, 0x74f, 0x750, 0x751, 0, 0xae5, 0, 0),
154 D_GATE(CLK_25_PG7, "clk_25_pg7", CLKOUT_D40, 0x752, 0x753, 0x754, 0, 0xae6, 0, 0),
155 D_GATE(CLK_25_PG8, "clk_25_pg8", CLKOUT_D40, 0x755, 0x756, 0x757, 0, 0xae7, 0, 0),
156 D_GATE(CLK_ADC, "clk_adc", DIV_ADC, 0x1ea, 0x1eb, 0, 0, 0, 0, 0),
[all …]
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/ |
| D | v10_structs.h | 29 uint32_t reserved_0; // offset: 0 (0x0)
30 uint32_t reserved_1; // offset: 1 (0x1)
31 uint32_t reserved_2; // offset: 2 (0x2)
32 uint32_t reserved_3; // offset: 3 (0x3)
33 uint32_t reserved_4; // offset: 4 (0x4)
34 uint32_t reserved_5; // offset: 5 (0x5)
35 uint32_t reserved_6; // offset: 6 (0x6)
36 uint32_t reserved_7; // offset: 7 (0x7)
37 uint32_t reserved_8; // offset: 8 (0x8)
38 uint32_t reserved_9; // offset: 9 (0x9)
[all …]
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| /kernel/linux/linux-4.19/drivers/net/wireless/broadcom/b43/ |
| D | phy_n.h | 11 #define B43_NPHY_BBCFG B43_PHY_N(0x001) /* BB config */
12 #define B43_NPHY_BBCFG_RSTCCA 0x4000 /* Reset CCA */
13 #define B43_NPHY_BBCFG_RSTRX 0x8000 /* Reset RX */
14 #define B43_NPHY_CHANNEL B43_PHY_N(0x005) /* Channel */
15 #define B43_NPHY_TXERR B43_PHY_N(0x007) /* TX error */
16 #define B43_NPHY_BANDCTL B43_PHY_N(0x009) /* Band control */
17 #define B43_NPHY_BANDCTL_5GHZ 0x0001 /* Use the 5GHz band */
18 #define B43_NPHY_4WI_ADDR B43_PHY_N(0x00B) /* Four-wire bus address */
19 #define B43_NPHY_4WI_DATAHI B43_PHY_N(0x00C) /* Four-wire bus data high */
20 #define B43_NPHY_4WI_DATALO B43_PHY_N(0x00D) /* Four-wire bus data low */
[all …]
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| /kernel/linux/linux-5.10/drivers/net/wireless/broadcom/b43/ |
| D | phy_n.h | 11 #define B43_NPHY_BBCFG B43_PHY_N(0x001) /* BB config */
12 #define B43_NPHY_BBCFG_RSTCCA 0x4000 /* Reset CCA */
13 #define B43_NPHY_BBCFG_RSTRX 0x8000 /* Reset RX */
14 #define B43_NPHY_CHANNEL B43_PHY_N(0x005) /* Channel */
15 #define B43_NPHY_TXERR B43_PHY_N(0x007) /* TX error */
16 #define B43_NPHY_BANDCTL B43_PHY_N(0x009) /* Band control */
17 #define B43_NPHY_BANDCTL_5GHZ 0x0001 /* Use the 5GHz band */
18 #define B43_NPHY_4WI_ADDR B43_PHY_N(0x00B) /* Four-wire bus address */
19 #define B43_NPHY_4WI_DATAHI B43_PHY_N(0x00C) /* Four-wire bus data high */
20 #define B43_NPHY_4WI_DATALO B43_PHY_N(0x00D) /* Four-wire bus data low */
[all …]
|
| /kernel/linux/linux-5.10/arch/arm64/boot/dts/qcom/ |
| D | sdm845.dtsi | 73 reg = <0 0x80000000 0 0>;
82 reg = <0 0x85700000 0 0x600000>;
87 reg = <0 0x85e00000 0 0x100000>;
92 reg = <0 0x85fc0000 0 0x20000>;
98 reg = <0x0 0x85fe0000 0 0x20000>;
103 reg = <0x0 0x86000000 0 0x200000>;
108 reg = <0 0x86200000 0 0x2d00000>;
114 reg = <0 0x88f00000 0 0x200000>;
122 reg = <0 0x8ab00000 0 0x1400000>;
127 reg = <0 0x8bf00000 0 0x500000>;
[all …]
|