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/kernel/linux/linux-4.19/arch/powerpc/boot/
Dgamecube-head.S33 rlwinm 9, 9, 0, ~((1<<4)|(1<<5)) /* MSR_DR|MSR_IR */
47 li 8, 0
48 mtspr 0x210, 8 /* IBAT0U */
49 mtspr 0x212, 8 /* IBAT1U */
50 mtspr 0x214, 8 /* IBAT2U */
51 mtspr 0x216, 8 /* IBAT3U */
52 mtspr 0x218, 8 /* DBAT0U */
53 mtspr 0x21a, 8 /* DBAT1U */
54 mtspr 0x21c, 8 /* DBAT2U */
55 mtspr 0x21e, 8 /* DBAT3U */
[all …]
Dwii-head.S34 rlwinm 9, 9, 0, ~((1<<4)|(1<<5)) /* MSR_DR|MSR_IR */
48 li 8, 0
49 mtspr 0x210, 8 /* IBAT0U */
50 mtspr 0x212, 8 /* IBAT1U */
51 mtspr 0x214, 8 /* IBAT2U */
52 mtspr 0x216, 8 /* IBAT3U */
53 mtspr 0x218, 8 /* DBAT0U */
54 mtspr 0x21a, 8 /* DBAT1U */
55 mtspr 0x21c, 8 /* DBAT2U */
56 mtspr 0x21e, 8 /* DBAT3U */
[all …]
/kernel/linux/linux-5.10/arch/powerpc/boot/
Dgamecube-head.S28 rlwinm 9, 9, 0, ~((1<<4)|(1<<5)) /* MSR_DR|MSR_IR */
42 li 8, 0
43 mtspr 0x210, 8 /* IBAT0U */
44 mtspr 0x212, 8 /* IBAT1U */
45 mtspr 0x214, 8 /* IBAT2U */
46 mtspr 0x216, 8 /* IBAT3U */
47 mtspr 0x218, 8 /* DBAT0U */
48 mtspr 0x21a, 8 /* DBAT1U */
49 mtspr 0x21c, 8 /* DBAT2U */
50 mtspr 0x21e, 8 /* DBAT3U */
[all …]
Dwii-head.S29 rlwinm 9, 9, 0, ~((1<<4)|(1<<5)) /* MSR_DR|MSR_IR */
43 li 8, 0
44 mtspr 0x210, 8 /* IBAT0U */
45 mtspr 0x212, 8 /* IBAT1U */
46 mtspr 0x214, 8 /* IBAT2U */
47 mtspr 0x216, 8 /* IBAT3U */
48 mtspr 0x218, 8 /* DBAT0U */
49 mtspr 0x21a, 8 /* DBAT1U */
50 mtspr 0x21c, 8 /* DBAT2U */
51 mtspr 0x21e, 8 /* DBAT3U */
[all …]
/kernel/linux/linux-4.19/drivers/scsi/qedi/
Dqedi_nvm_iscsi_cfg.h40 union nvm_iscsi_ipv4_addr addr; /* 0x0 */
41 union nvm_iscsi_ipv4_addr subnet_mask; /* 0x4 */
42 union nvm_iscsi_ipv4_addr gateway; /* 0x8 */
43 union nvm_iscsi_ipv4_addr primary_dns; /* 0xC */
44 union nvm_iscsi_ipv4_addr secondary_dns; /* 0x10 */
45 union nvm_iscsi_ipv4_addr dhcp_addr; /* 0x14 */
47 union nvm_iscsi_ipv4_addr isns_server; /* 0x18 */
48 union nvm_iscsi_ipv4_addr slp_server; /* 0x1C */
49 union nvm_iscsi_ipv4_addr primay_radius_server; /* 0x20 */
50 union nvm_iscsi_ipv4_addr secondary_radius_server; /* 0x24 */
[all …]
/kernel/linux/linux-5.10/drivers/scsi/qedi/
Dqedi_nvm_iscsi_cfg.h37 union nvm_iscsi_ipv4_addr addr; /* 0x0 */
38 union nvm_iscsi_ipv4_addr subnet_mask; /* 0x4 */
39 union nvm_iscsi_ipv4_addr gateway; /* 0x8 */
40 union nvm_iscsi_ipv4_addr primary_dns; /* 0xC */
41 union nvm_iscsi_ipv4_addr secondary_dns; /* 0x10 */
42 union nvm_iscsi_ipv4_addr dhcp_addr; /* 0x14 */
44 union nvm_iscsi_ipv4_addr isns_server; /* 0x18 */
45 union nvm_iscsi_ipv4_addr slp_server; /* 0x1C */
46 union nvm_iscsi_ipv4_addr primay_radius_server; /* 0x20 */
47 union nvm_iscsi_ipv4_addr secondary_radius_server; /* 0x24 */
[all …]
/kernel/linux/linux-4.19/Documentation/ioctl/
Dioctl-decoding.txt18 7-0 function #
21 So for example 0x82187201 is a read with arg length of 0x218,
/kernel/linux/linux-4.19/Documentation/input/
Dgameport-programming.rst16 Make sure struct gameport is initialized to 0 in all other fields. The
22 0x201 address is smaller.
24 Eg. if your driver supports addresses 0x200, 0x208, 0x210 and 0x218, then
25 0x218 would be the address of first choice.
28 space (is above 0x1000), use that one, and don't map the ISA mirror.
52 my_mmio = 0xff;
79 for (i = 0; i < 4; i++)
166 outb(0xff, io) will be used.
180 read function. It should fill axes[0..3] with four values of the joystick axes
181 and buttons[0] with four bits representing the buttons.
[all …]
/kernel/linux/linux-5.10/Documentation/input/
Dgameport-programming.rst16 Make sure struct gameport is initialized to 0 in all other fields. The
22 0x201 address is smaller.
24 Eg. if your driver supports addresses 0x200, 0x208, 0x210 and 0x218, then
25 0x218 would be the address of first choice.
28 space (is above 0x1000), use that one, and don't map the ISA mirror.
52 my_mmio = 0xff;
79 for (i = 0; i < 4; i++)
166 outb(0xff, io) will be used.
180 read function. It should fill axes[0..3] with four values of the joystick axes
181 and buttons[0] with four bits representing the buttons.
[all …]
/kernel/linux/linux-5.10/Documentation/userspace-api/ioctl/
Dioctl-decoding.rst24 7-0 function #
28 So for example 0x82187201 is a read with arg length of 0x218,
/kernel/linux/linux-5.10/arch/sh/drivers/pci/
Dpci-sh7780.h13 #define PCIECR 0xFE000008
14 #define PCIECR_ENBL 0x01
17 #define SH7780_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */
18 #define SH7780_PCI_CONFIG_SIZE 0x01000000 /* Config space size */
20 #define SH7780_PCIREG_BASE 0xFE040000 /* PCI regs base address */
23 #define SH7780_PCIIR 0x114 /* PCI Interrupt Register */
24 #define SH7780_PCIIMR 0x118 /* PCI Interrupt Mask Register */
25 #define SH7780_PCIAIR 0x11C /* Error Address Register */
26 #define SH7780_PCICIR 0x120 /* Error Command/Data Register */
27 #define SH7780_PCIAINT 0x130 /* Arbiter Interrupt Register */
[all …]
/kernel/linux/linux-4.19/include/dt-bindings/clock/
Dlpc18xx-ccu.h13 #define CLK_APB3_BUS 0x100
14 #define CLK_APB3_I2C1 0x108
15 #define CLK_APB3_DAC 0x110
16 #define CLK_APB3_ADC0 0x118
17 #define CLK_APB3_ADC1 0x120
18 #define CLK_APB3_CAN0 0x128
19 #define CLK_APB1_BUS 0x200
20 #define CLK_APB1_MOTOCON_PWM 0x208
21 #define CLK_APB1_I2C0 0x210
22 #define CLK_APB1_I2S 0x218
[all …]
/kernel/linux/linux-5.10/include/dt-bindings/clock/
Dlpc18xx-ccu.h13 #define CLK_APB3_BUS 0x100
14 #define CLK_APB3_I2C1 0x108
15 #define CLK_APB3_DAC 0x110
16 #define CLK_APB3_ADC0 0x118
17 #define CLK_APB3_ADC1 0x120
18 #define CLK_APB3_CAN0 0x128
19 #define CLK_APB1_BUS 0x200
20 #define CLK_APB1_MOTOCON_PWM 0x208
21 #define CLK_APB1_I2C0 0x210
22 #define CLK_APB1_I2S 0x218
[all …]
/kernel/linux/linux-4.19/arch/sh/drivers/pci/
Dpci-sh7780.h16 #define PCIECR 0xFE000008
17 #define PCIECR_ENBL 0x01
20 #define SH7780_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */
21 #define SH7780_PCI_CONFIG_SIZE 0x01000000 /* Config space size */
23 #define SH7780_PCIREG_BASE 0xFE040000 /* PCI regs base address */
26 #define SH7780_PCIIR 0x114 /* PCI Interrupt Register */
27 #define SH7780_PCIIMR 0x118 /* PCI Interrupt Mask Register */
28 #define SH7780_PCIAIR 0x11C /* Error Address Register */
29 #define SH7780_PCICIR 0x120 /* Error Command/Data Register */
30 #define SH7780_PCIAINT 0x130 /* Arbiter Interrupt Register */
[all …]
/kernel/linux/linux-4.19/drivers/tty/
Dmoxa.h5 #define MOXA 0x400
17 #define Magic_code 0x404
22 #define C218_ConfBase 0x800
23 #define C218_status (C218_ConfBase + 0) /* BIOS running status */
25 #define C218_key (C218_ConfBase + 4) /* WORD (0x218 for C218) */
28 #define C218chksum_ok (C218_ConfBase + 0x0a) /* BYTE (1:ok) */
29 #define C218_TestRx (C218_ConfBase + 0x10) /* 8 bytes for 8 ports */
30 #define C218_TestTx (C218_ConfBase + 0x18) /* 8 bytes for 8 ports */
31 #define C218_RXerr (C218_ConfBase + 0x20) /* 8 bytes for 8 ports */
32 #define C218_ErrFlag (C218_ConfBase + 0x28) /* 8 bytes for 8 ports */
[all …]
/kernel/linux/linux-5.10/drivers/tty/
Dmoxa.h5 #define MOXA 0x400
17 #define Magic_code 0x404
22 #define C218_ConfBase 0x800
23 #define C218_status (C218_ConfBase + 0) /* BIOS running status */
25 #define C218_key (C218_ConfBase + 4) /* WORD (0x218 for C218) */
28 #define C218chksum_ok (C218_ConfBase + 0x0a) /* BYTE (1:ok) */
29 #define C218_TestRx (C218_ConfBase + 0x10) /* 8 bytes for 8 ports */
30 #define C218_TestTx (C218_ConfBase + 0x18) /* 8 bytes for 8 ports */
31 #define C218_RXerr (C218_ConfBase + 0x20) /* 8 bytes for 8 ports */
32 #define C218_ErrFlag (C218_ConfBase + 0x28) /* 8 bytes for 8 ports */
[all …]
/kernel/linux/linux-4.19/arch/arm/mach-ks8695/
Dregs-pci.h14 #define KS8695_PCI_OFFSET (0xF0000 + 0x2000)
19 #define KS8695_CRCFID (0x000) /* Configuration: Identification */
20 #define KS8695_CRCFCS (0x004) /* Configuration: Command and Status */
21 #define KS8695_CRCFRV (0x008) /* Configuration: Revision */
22 #define KS8695_CRCFLT (0x00C) /* Configuration: Latency Timer */
23 #define KS8695_CRCBMA (0x010) /* Configuration: Base Memory Address */
24 #define KS8695_CRCSID (0x02C) /* Configuration: Subsystem ID */
25 #define KS8695_CRCFIT (0x03C) /* Configuration: Interrupt */
26 #define KS8695_PBCA (0x100) /* Bridge Configuration Address */
27 #define KS8695_PBCD (0x104) /* Bridge Configuration Data */
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/marvell/octeontx2/nic/
Dotx2_reg.h17 #define RVU_PF_VFX_PFVF_MBOX0 (0x00000)
18 #define RVU_PF_VFX_PFVF_MBOX1 (0x00008)
19 #define RVU_PF_VFX_PFVF_MBOXX(a, b) (0x0 | (a) << 12 | (b) << 3)
20 #define RVU_PF_VF_BAR4_ADDR (0x10)
21 #define RVU_PF_BLOCK_ADDRX_DISC(a) (0x200 | (a) << 3)
22 #define RVU_PF_VFME_STATUSX(a) (0x800 | (a) << 3)
23 #define RVU_PF_VFTRPENDX(a) (0x820 | (a) << 3)
24 #define RVU_PF_VFTRPEND_W1SX(a) (0x840 | (a) << 3)
25 #define RVU_PF_VFPF_MBOX_INTX(a) (0x880 | (a) << 3)
26 #define RVU_PF_VFPF_MBOX_INT_W1SX(a) (0x8A0 | (a) << 3)
[all …]
/kernel/linux/linux-5.10/include/linux/bcma/
Dbcma_driver_gmac_cmn.h7 #define BCMA_GMAC_CMN_STAG0 0x000
8 #define BCMA_GMAC_CMN_STAG1 0x004
9 #define BCMA_GMAC_CMN_STAG2 0x008
10 #define BCMA_GMAC_CMN_STAG3 0x00C
11 #define BCMA_GMAC_CMN_PARSER_CTL 0x020
12 #define BCMA_GMAC_CMN_MIB_MAX_LEN 0x024
13 #define BCMA_GMAC_CMN_PHY_ACCESS 0x100
14 #define BCMA_GMAC_CMN_PA_DATA_MASK 0x0000ffff
15 #define BCMA_GMAC_CMN_PA_ADDR_MASK 0x001f0000
17 #define BCMA_GMAC_CMN_PA_REG_MASK 0x1f000000
[all …]
/kernel/linux/linux-4.19/include/linux/bcma/
Dbcma_driver_gmac_cmn.h7 #define BCMA_GMAC_CMN_STAG0 0x000
8 #define BCMA_GMAC_CMN_STAG1 0x004
9 #define BCMA_GMAC_CMN_STAG2 0x008
10 #define BCMA_GMAC_CMN_STAG3 0x00C
11 #define BCMA_GMAC_CMN_PARSER_CTL 0x020
12 #define BCMA_GMAC_CMN_MIB_MAX_LEN 0x024
13 #define BCMA_GMAC_CMN_PHY_ACCESS 0x100
14 #define BCMA_GMAC_CMN_PA_DATA_MASK 0x0000ffff
15 #define BCMA_GMAC_CMN_PA_ADDR_MASK 0x001f0000
17 #define BCMA_GMAC_CMN_PA_REG_MASK 0x1f000000
[all …]
/kernel/linux/linux-4.19/arch/mips/pci/
Dpci-emma2rh.c52 .mem_offset = -0x04000000,
53 .io_offset = 0,
59 emma2rh_out32(EMMA2RH_PCI_ARBIT_CTR, 0x70f); in emma2rh_pci_init()
61 emma2rh_out32(EMMA2RH_PCI_IWIN0_CTR, 0x80000a18); in emma2rh_pci_init()
65 emma2rh_out32(EMMA2RH_PCI_CONFIG_BASE + PCI_BASE_ADDRESS_0, 0x10000000); in emma2rh_pci_init()
66 emma2rh_out32(EMMA2RH_PCI_CONFIG_BASE + PCI_BASE_ADDRESS_1, 0x00000000); in emma2rh_pci_init()
68 emma2rh_out32(EMMA2RH_PCI_IWIN0_CTR, 0x12000000 | 0x218); in emma2rh_pci_init()
69 emma2rh_out32(EMMA2RH_PCI_IWIN1_CTR, 0x18000000 | 0x600); in emma2rh_pci_init()
70 emma2rh_out32(EMMA2RH_PCI_INIT_ESWP, 0x00000200); in emma2rh_pci_init()
72 emma2rh_out32(EMMA2RH_PCI_TWIN_CTR, 0x00009200); in emma2rh_pci_init()
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/sun4i/
Dsun4i_frontend.h12 #define SUN4I_FRONTEND_EN_REG 0x000
13 #define SUN4I_FRONTEND_EN_EN BIT(0)
15 #define SUN4I_FRONTEND_FRM_CTRL_REG 0x004
19 #define SUN4I_FRONTEND_FRM_CTRL_REG_RDY BIT(0)
21 #define SUN4I_FRONTEND_BYPASS_REG 0x008
24 #define SUN4I_FRONTEND_BUF_ADDR0_REG 0x020
26 #define SUN4I_FRONTEND_LINESTRD0_REG 0x040
28 #define SUN4I_FRONTEND_INPUT_FMT_REG 0x04c
33 #define SUN4I_FRONTEND_OUTPUT_FMT_REG 0x05c
36 #define SUN4I_FRONTEND_CH0_INSIZE_REG 0x100
[all …]
/kernel/linux/linux-5.10/drivers/media/common/b2c2/
Dflexcop-reg.h11 FLEXCOP_UNK = 0,
18 FC_UNK = 0,
32 FC_USB = 0,
47 #define fc_data_Tag_ID_DVB 0x3e
48 #define fc_data_Tag_ID_ATSC 0x3f
49 #define fc_data_Tag_ID_IDSB 0x8b
51 #define fc_key_code_default 0x1
52 #define fc_key_code_even 0x2
53 #define fc_key_code_odd 0x3
64 FC_WRITE = 0,
[all …]
/kernel/linux/linux-4.19/drivers/media/common/b2c2/
Dflexcop-reg.h11 FLEXCOP_UNK = 0,
18 FC_UNK = 0,
32 FC_USB = 0,
47 #define fc_data_Tag_ID_DVB 0x3e
48 #define fc_data_Tag_ID_ATSC 0x3f
49 #define fc_data_Tag_ID_IDSB 0x8b
51 #define fc_key_code_default 0x1
52 #define fc_key_code_even 0x2
53 #define fc_key_code_odd 0x3
64 FC_WRITE = 0,
[all …]
/kernel/linux/linux-5.10/sound/soc/fsl/
Dfsl_audmix.h15 #define FSL_AUDMIX_CTR 0x200 /* Control */
16 #define FSL_AUDMIX_STR 0x204 /* Status */
18 #define FSL_AUDMIX_ATCR0 0x208 /* Attenuation Control */
19 #define FSL_AUDMIX_ATIVAL0 0x20c /* Attenuation Initial Value */
20 #define FSL_AUDMIX_ATSTPUP0 0x210 /* Attenuation step up factor */
21 #define FSL_AUDMIX_ATSTPDN0 0x214 /* Attenuation step down factor */
22 #define FSL_AUDMIX_ATSTPTGT0 0x218 /* Attenuation step target */
23 #define FSL_AUDMIX_ATTNVAL0 0x21c /* Attenuation Value */
24 #define FSL_AUDMIX_ATSTP0 0x220 /* Attenuation step number */
26 #define FSL_AUDMIX_ATCR1 0x228 /* Attenuation Control */
[all …]

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