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/kernel/linux/linux-4.19/drivers/memory/tegra/
Dtegra210.c15 .id = 0x00,
19 .id = 0x01,
23 .reg = 0x228,
27 .reg = 0x2e8,
28 .shift = 0,
29 .mask = 0xff,
30 .def = 0xc2,
33 .id = 0x02,
37 .reg = 0x228,
41 .reg = 0x2f4,
[all …]
Dtegra124.c16 #define MC_EMEM_ARB_CFG 0x90
17 #define MC_EMEM_ARB_OUTSTANDING_REQ 0x94
18 #define MC_EMEM_ARB_TIMING_RCD 0x98
19 #define MC_EMEM_ARB_TIMING_RP 0x9c
20 #define MC_EMEM_ARB_TIMING_RC 0xa0
21 #define MC_EMEM_ARB_TIMING_RAS 0xa4
22 #define MC_EMEM_ARB_TIMING_FAW 0xa8
23 #define MC_EMEM_ARB_TIMING_RRD 0xac
24 #define MC_EMEM_ARB_TIMING_RAP2PRE 0xb0
25 #define MC_EMEM_ARB_TIMING_WAP2PRE 0xb4
[all …]
/kernel/linux/linux-5.10/drivers/memory/tegra/
Dtegra210.c12 .id = 0x00,
16 .id = 0x01,
20 .reg = 0x228,
24 .reg = 0x2e8,
25 .shift = 0,
26 .mask = 0xff,
27 .def = 0xc2,
30 .id = 0x02,
34 .reg = 0x228,
38 .reg = 0x2f4,
[all …]
Dtegra124.c15 .id = 0x00,
19 .id = 0x01,
23 .reg = 0x228,
27 .reg = 0x2e8,
28 .shift = 0,
29 .mask = 0xff,
30 .def = 0xc2,
33 .id = 0x02,
37 .reg = 0x228,
41 .reg = 0x2f4,
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/
Dintel_lrc.h38 #define RING_ELSP(base) _MMIO((base) + 0x230)
39 #define RING_EXECLIST_STATUS_LO(base) _MMIO((base) + 0x234)
40 #define RING_EXECLIST_STATUS_HI(base) _MMIO((base) + 0x234 + 4)
41 #define RING_CONTEXT_CONTROL(base) _MMIO((base) + 0x244)
43 #define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT (1 << 0)
47 #define RING_CONTEXT_STATUS_PTR(base) _MMIO((base) + 0x3a0)
48 #define RING_EXECLIST_SQ_CONTENTS(base) _MMIO((base) + 0x510)
49 #define RING_EXECLIST_CONTROL(base) _MMIO((base) + 0x550)
51 #define EL_CTRL_LOAD (1 << 0)
55 * wraps to 0."
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/i915/
Dintel_lrc.h33 #define RING_ELSP(engine) _MMIO((engine)->mmio_base + 0x230)
34 #define RING_EXECLIST_STATUS_LO(engine) _MMIO((engine)->mmio_base + 0x234)
35 #define RING_EXECLIST_STATUS_HI(engine) _MMIO((engine)->mmio_base + 0x234 + 4)
36 #define RING_CONTEXT_CONTROL(engine) _MMIO((engine)->mmio_base + 0x244)
38 #define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT (1 << 0)
41 #define RING_CONTEXT_STATUS_BUF_BASE(engine) _MMIO((engine)->mmio_base + 0x370)
42 #define RING_CONTEXT_STATUS_BUF_LO(engine, i) _MMIO((engine)->mmio_base + 0x370 + (i) * 8)
43 #define RING_CONTEXT_STATUS_BUF_HI(engine, i) _MMIO((engine)->mmio_base + 0x370 + (i) * 8 + 4)
44 #define RING_CONTEXT_STATUS_PTR(engine) _MMIO((engine)->mmio_base + 0x3a0)
45 #define RING_EXECLIST_SQ_CONTENTS(engine) _MMIO((engine)->mmio_base + 0x510)
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/media/
Dst-rc.txt18 - pinctrl-names, pinctrl-0: the pincontrol settings to configure muxing
26 reg = <0xfe518000 0x234>;
27 interrupts = <0 203 0>;
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/media/
Dst-rc.txt18 - pinctrl-names, pinctrl-0: the pincontrol settings to configure muxing
26 reg = <0xfe518000 0x234>;
27 interrupts = <0 203 0>;
/kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/
Dimx8mp-pinfunc.h13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
[all …]
Dimx8mq-pinfunc.h15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
Dimx8mm-pinfunc.h14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0…
20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0…
21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0…
22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0…
23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0…
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/
Dfsl,imx8mq-pinctrl.yaml72 reg = <0x30330000 0x10000>;
76 <0x234 0x49C 0x4F4 0x0 0x0 0x49>,
77 <0x238 0x4A0 0x4F4 0x0 0x0 0x49>;
/kernel/linux/linux-5.10/include/linux/bcma/
Dbcma_driver_gmac_cmn.h7 #define BCMA_GMAC_CMN_STAG0 0x000
8 #define BCMA_GMAC_CMN_STAG1 0x004
9 #define BCMA_GMAC_CMN_STAG2 0x008
10 #define BCMA_GMAC_CMN_STAG3 0x00C
11 #define BCMA_GMAC_CMN_PARSER_CTL 0x020
12 #define BCMA_GMAC_CMN_MIB_MAX_LEN 0x024
13 #define BCMA_GMAC_CMN_PHY_ACCESS 0x100
14 #define BCMA_GMAC_CMN_PA_DATA_MASK 0x0000ffff
15 #define BCMA_GMAC_CMN_PA_ADDR_MASK 0x001f0000
17 #define BCMA_GMAC_CMN_PA_REG_MASK 0x1f000000
[all …]
/kernel/linux/linux-4.19/include/linux/bcma/
Dbcma_driver_gmac_cmn.h7 #define BCMA_GMAC_CMN_STAG0 0x000
8 #define BCMA_GMAC_CMN_STAG1 0x004
9 #define BCMA_GMAC_CMN_STAG2 0x008
10 #define BCMA_GMAC_CMN_STAG3 0x00C
11 #define BCMA_GMAC_CMN_PARSER_CTL 0x020
12 #define BCMA_GMAC_CMN_MIB_MAX_LEN 0x024
13 #define BCMA_GMAC_CMN_PHY_ACCESS 0x100
14 #define BCMA_GMAC_CMN_PA_DATA_MASK 0x0000ffff
15 #define BCMA_GMAC_CMN_PA_ADDR_MASK 0x001f0000
17 #define BCMA_GMAC_CMN_PA_REG_MASK 0x1f000000
[all …]
/kernel/linux/linux-5.10/arch/powerpc/include/asm/
Dtsi108.h18 #define TSI108_REG_SIZE (0x10000)
21 #define TSI108_HLP_SIZE 0x1000
22 #define TSI108_PCI_SIZE 0x1000
23 #define TSI108_CLK_SIZE 0x1000
24 #define TSI108_PB_SIZE 0x1000
25 #define TSI108_SD_SIZE 0x1000
26 #define TSI108_DMA_SIZE 0x1000
27 #define TSI108_ETH_SIZE 0x1000
28 #define TSI108_I2C_SIZE 0x400
29 #define TSI108_MPIC_SIZE 0x400
[all …]
/kernel/linux/linux-4.19/arch/powerpc/include/asm/
Dtsi108.h22 #define TSI108_REG_SIZE (0x10000)
25 #define TSI108_HLP_SIZE 0x1000
26 #define TSI108_PCI_SIZE 0x1000
27 #define TSI108_CLK_SIZE 0x1000
28 #define TSI108_PB_SIZE 0x1000
29 #define TSI108_SD_SIZE 0x1000
30 #define TSI108_DMA_SIZE 0x1000
31 #define TSI108_ETH_SIZE 0x1000
32 #define TSI108_I2C_SIZE 0x400
33 #define TSI108_MPIC_SIZE 0x400
[all …]
/kernel/linux/linux-5.10/sound/soc/fsl/
Dfsl_audmix.h15 #define FSL_AUDMIX_CTR 0x200 /* Control */
16 #define FSL_AUDMIX_STR 0x204 /* Status */
18 #define FSL_AUDMIX_ATCR0 0x208 /* Attenuation Control */
19 #define FSL_AUDMIX_ATIVAL0 0x20c /* Attenuation Initial Value */
20 #define FSL_AUDMIX_ATSTPUP0 0x210 /* Attenuation step up factor */
21 #define FSL_AUDMIX_ATSTPDN0 0x214 /* Attenuation step down factor */
22 #define FSL_AUDMIX_ATSTPTGT0 0x218 /* Attenuation step target */
23 #define FSL_AUDMIX_ATTNVAL0 0x21c /* Attenuation Value */
24 #define FSL_AUDMIX_ATSTP0 0x220 /* Attenuation step number */
26 #define FSL_AUDMIX_ATCR1 0x228 /* Attenuation Control */
[all …]
/kernel/linux/linux-4.19/arch/arm/boot/dts/
Dimx25-pinfunc.h20 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
21 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
23 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
24 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
25 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
27 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
28 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
29 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
30 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
32 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/bridge/
Dnwl-dsi.h12 #define NWL_DSI_CFG_NUM_LANES 0x0
13 #define NWL_DSI_CFG_NONCONTINUOUS_CLK 0x4
14 #define NWL_DSI_CFG_T_PRE 0x8
15 #define NWL_DSI_CFG_T_POST 0xc
16 #define NWL_DSI_CFG_TX_GAP 0x10
17 #define NWL_DSI_CFG_AUTOINSERT_EOTP 0x14
18 #define NWL_DSI_CFG_EXTRA_CMDS_AFTER_EOTP 0x18
19 #define NWL_DSI_CFG_HTX_TO_COUNT 0x1c
20 #define NWL_DSI_CFG_LRX_H_TO_COUNT 0x20
21 #define NWL_DSI_CFG_BTA_H_TO_COUNT 0x24
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dimx25-pinfunc.h16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
/kernel/linux/linux-5.10/drivers/scsi/mvsas/
Dmv_64xx.h19 MVS_GBL_CTL = 0x04, /* global control */
20 MVS_GBL_INT_STAT = 0x08, /* global irq status */
21 MVS_GBL_PI = 0x0C, /* ports implemented bitmask */
23 MVS_PHY_CTL = 0x40, /* SOC PHY Control */
24 MVS_PORTS_IMP = 0x9C, /* SOC Port Implemented */
26 MVS_GBL_PORT_TYPE = 0xa0, /* port type */
28 MVS_CTL = 0x100, /* SAS/SATA port configuration */
29 MVS_PCS = 0x104, /* SAS/SATA port control/status */
30 MVS_CMD_LIST_LO = 0x108, /* cmd list addr */
31 MVS_CMD_LIST_HI = 0x10C,
[all …]
/kernel/linux/linux-5.10/arch/powerpc/boot/
Dwii-head.S29 rlwinm 9, 9, 0, ~((1<<4)|(1<<5)) /* MSR_DR|MSR_IR */
43 li 8, 0
44 mtspr 0x210, 8 /* IBAT0U */
45 mtspr 0x212, 8 /* IBAT1U */
46 mtspr 0x214, 8 /* IBAT2U */
47 mtspr 0x216, 8 /* IBAT3U */
48 mtspr 0x218, 8 /* DBAT0U */
49 mtspr 0x21a, 8 /* DBAT1U */
50 mtspr 0x21c, 8 /* DBAT2U */
51 mtspr 0x21e, 8 /* DBAT3U */
[all …]
/kernel/linux/linux-4.19/arch/powerpc/boot/
Dwii-head.S34 rlwinm 9, 9, 0, ~((1<<4)|(1<<5)) /* MSR_DR|MSR_IR */
48 li 8, 0
49 mtspr 0x210, 8 /* IBAT0U */
50 mtspr 0x212, 8 /* IBAT1U */
51 mtspr 0x214, 8 /* IBAT2U */
52 mtspr 0x216, 8 /* IBAT3U */
53 mtspr 0x218, 8 /* DBAT0U */
54 mtspr 0x21a, 8 /* DBAT1U */
55 mtspr 0x21c, 8 /* DBAT2U */
56 mtspr 0x21e, 8 /* DBAT3U */
[all …]
/kernel/linux/linux-5.10/drivers/media/pci/tw68/
Dtw68-reg.h23 #define TW68_DMAC 0x000
24 #define TW68_DMAP_SA 0x004
25 #define TW68_DMAP_EXE 0x008
26 #define TW68_DMAP_PP 0x00c
27 #define TW68_VBIC 0x010
28 #define TW68_SBUSC 0x014
29 #define TW68_SBUSSD 0x018
30 #define TW68_INTSTAT 0x01C
31 #define TW68_INTMASK 0x020
32 #define TW68_GPIOC 0x024
[all …]
/kernel/linux/linux-4.19/drivers/scsi/mvsas/
Dmv_64xx.h35 MVS_GBL_CTL = 0x04, /* global control */
36 MVS_GBL_INT_STAT = 0x08, /* global irq status */
37 MVS_GBL_PI = 0x0C, /* ports implemented bitmask */
39 MVS_PHY_CTL = 0x40, /* SOC PHY Control */
40 MVS_PORTS_IMP = 0x9C, /* SOC Port Implemented */
42 MVS_GBL_PORT_TYPE = 0xa0, /* port type */
44 MVS_CTL = 0x100, /* SAS/SATA port configuration */
45 MVS_PCS = 0x104, /* SAS/SATA port control/status */
46 MVS_CMD_LIST_LO = 0x108, /* cmd list addr */
47 MVS_CMD_LIST_HI = 0x10C,
[all …]

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