Home
last modified time | relevance | path

Searched +full:0 +full:x3000 (Results 1 – 25 of 1008) sorted by relevance

12345678910>>...41

/kernel/linux/linux-5.10/arch/arm64/boot/dts/sprd/
Dsharkl3.dtsi22 reg = <0 0x20e00000 0 0x4000>;
25 ranges = <0 0 0x20e00000 0x4000>;
29 reg = <0x0 0x1020>;
37 reg = <0 0x402b0000 0 0x4000>;
40 ranges = <0 0 0x402b0000 0x4000>;
44 reg = <0 0x1200>;
54 reg = <0 0x402e0000 0 0x4000>;
57 ranges = <0 0 0x402e0000 0x4000>;
61 reg = <0 0x1100>;
69 reg = <0 0x40353000 0 0x3000>;
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dimx6ul-ccimx6ulsom.dtsi12 reg = <0x80000000 0>; /* will be filled by U-Boot */
23 size = <0x4000000>;
35 pinctrl-0 = <&pinctrl_gpmi_nand>;
42 pinctrl-0 = <&pinctrl_i2c1>;
47 reg = <0x08>;
172 pinctrl-0 = <&pinctrl_uart1>;
180 pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_wifibt_ctrl>;
191 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1
192 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1
193 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1
[all …]
Datlas7.dtsi29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0>;
46 #clock-cells = <0>;
52 #clock-cells = <0>;
60 interrupts = <0 29 4>, <0 82 4>;
67 ranges = <0x10000000 0x10000000 0xc0000000>;
73 reg = <0x10301000 0x1000>,
74 <0x10302000 0x0100>;
79 reg = <0x10E30020 0x4>;
[all …]
Dimx6ul-ccimx6ulsbcpro.dts21 pwms = <&pwm5 0 50000>;
22 brightness-levels = <0 4 8 16 32 64 128 255>;
51 pinctrl-0 = <&pinctrl_adc1>;
57 pinctrl-0 = <&pinctrl_flexcan1>;
65 pinctrl-0 = <&pinctrl_flexcan2>;
73 pinctrl-0 = <&pinctrl_ecspi1_master>;
79 pinctrl-0 = <&pinctrl_enet1>;
87 pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>;
96 #size-cells = <0>;
98 ethphy0: ethernet-phy@0 {
[all …]
/kernel/linux/linux-5.10/drivers/misc/habanalabs/include/goya/asic_reg/
Dcpu_ca53_cfg_masks.h23 #define CPU_CA53_CFG_ARM_CFG_AA64NAA32_SHIFT 0
24 #define CPU_CA53_CFG_ARM_CFG_AA64NAA32_MASK 0x3
26 #define CPU_CA53_CFG_ARM_CFG_END_MASK 0x30
28 #define CPU_CA53_CFG_ARM_CFG_TE_MASK 0x300
30 #define CPU_CA53_CFG_ARM_CFG_VINITHI_MASK 0x3000
33 #define CPU_CA53_CFG_RST_ADDR_LSB_VECTOR_SHIFT 0
34 #define CPU_CA53_CFG_RST_ADDR_LSB_VECTOR_MASK 0xFFFFFFFF
37 #define CPU_CA53_CFG_RST_ADDR_MSB_VECTOR_SHIFT 0
38 #define CPU_CA53_CFG_RST_ADDR_MSB_VECTOR_MASK 0xFF
41 #define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_SHIFT 0
[all …]
Dgoya_blocks.h16 #define mmPCI_NRTR_BASE 0x7FFC000000ull
17 #define PCI_NRTR_MAX_OFFSET 0x608
18 #define PCI_NRTR_SECTION 0x4000
19 #define mmPCI_RD_REGULATOR_BASE 0x7FFC004000ull
20 #define PCI_RD_REGULATOR_MAX_OFFSET 0x74
21 #define PCI_RD_REGULATOR_SECTION 0x1000
22 #define mmPCI_WR_REGULATOR_BASE 0x7FFC005000ull
23 #define PCI_WR_REGULATOR_MAX_OFFSET 0x74
24 #define PCI_WR_REGULATOR_SECTION 0x3B000
25 #define mmMME1_RTR_BASE 0x7FFC040000ull
[all …]
/kernel/linux/linux-4.19/arch/arm/boot/dts/
Datlas7.dtsi31 #size-cells = <0>;
33 cpu@0 {
36 reg = <0>;
48 #clock-cells = <0>;
54 #clock-cells = <0>;
62 interrupts = <0 29 4>, <0 82 4>;
69 ranges = <0x10000000 0x10000000 0xc0000000>;
75 reg = <0x10301000 0x1000>,
76 <0x10302000 0x0100>;
81 reg = <0x10E30020 0x4>;
[all …]
/kernel/linux/linux-4.19/arch/powerpc/boot/dts/fsl/
Dmpc8548cds.dtsi36 nor@0,0 {
40 reg = <0x0 0x0 0x01000000>;
44 partition@0 {
45 reg = <0x0 0x0b00000>;
50 reg = <0x0b00000 0x0400000>;
55 reg = <0x0f00000 0x060000>;
60 reg = <0x0f60000 0x020000>;
66 reg = <0x0f80000 0x080000>;
72 board-control@1,0 {
74 reg = <0x1 0x0 0x1000>;
[all …]
/kernel/linux/linux-5.10/arch/powerpc/boot/dts/fsl/
Dmpc8548cds.dtsi36 nor@0,0 {
40 reg = <0x0 0x0 0x01000000>;
44 partition@0 {
45 reg = <0x0 0x0b00000>;
50 reg = <0x0b00000 0x0400000>;
55 reg = <0x0f00000 0x060000>;
60 reg = <0x0f60000 0x020000>;
66 reg = <0x0f80000 0x080000>;
72 board-control@1,0 {
74 reg = <0x1 0x0 0x1000>;
[all …]
/kernel/linux/linux-5.10/sound/isa/msnd/
Dmsnd.c48 writew(0, base + JQS_wHead); in snd_msnd_init_queue()
49 writew(0, base + JQS_wTail); in snd_msnd_init_queue()
58 while (timeout-- > 0) in snd_msnd_wait_TXDE()
60 return 0; in snd_msnd_wait_TXDE()
70 while (timeout-- > 0) in snd_msnd_wait_HC0()
72 return 0; in snd_msnd_wait_HC0()
82 if (snd_msnd_wait_HC0(dev) == 0) { in snd_msnd_send_dsp_cmd()
85 return 0; in snd_msnd_send_dsp_cmd()
100 if (snd_msnd_wait_TXDE(dev) == 0) { in snd_msnd_send_word()
104 return 0; in snd_msnd_send_word()
[all …]
/kernel/linux/linux-4.19/sound/isa/msnd/
Dmsnd.c61 writew(0, base + JQS_wHead); in snd_msnd_init_queue()
62 writew(0, base + JQS_wTail); in snd_msnd_init_queue()
71 while (timeout-- > 0) in snd_msnd_wait_TXDE()
73 return 0; in snd_msnd_wait_TXDE()
83 while (timeout-- > 0) in snd_msnd_wait_HC0()
85 return 0; in snd_msnd_wait_HC0()
95 if (snd_msnd_wait_HC0(dev) == 0) { in snd_msnd_send_dsp_cmd()
98 return 0; in snd_msnd_send_dsp_cmd()
113 if (snd_msnd_wait_TXDE(dev) == 0) { in snd_msnd_send_word()
117 return 0; in snd_msnd_send_word()
[all …]
/kernel/linux/linux-4.19/drivers/net/dsa/mv88e6xxx/
Dglobal1.h20 /* Offset 0x00: Switch Global Status Register */
21 #define MV88E6XXX_G1_STS 0x00
22 #define MV88E6352_G1_STS_PPU_STATE 0x8000
23 #define MV88E6185_G1_STS_PPU_STATE_MASK 0xc000
24 #define MV88E6185_G1_STS_PPU_STATE_DISABLED_RST 0x0000
25 #define MV88E6185_G1_STS_PPU_STATE_INITIALIZING 0x4000
26 #define MV88E6185_G1_STS_PPU_STATE_DISABLED 0x8000
27 #define MV88E6185_G1_STS_PPU_STATE_POLLING 0xc000
28 #define MV88E6XXX_G1_STS_INIT_READY 0x0800
37 #define MV88E6XXX_G1_STS_IRQ_EEPROM_DONE 0
[all …]
/kernel/linux/linux-5.10/arch/alpha/kernel/
Dbinfmt_loader.c16 if (eh->fh.f_magic != 0x183 || (eh->fh.f_flags & 0x3000) != 0x3000) in load_binary()
30 bprm->taso = eh->ah.entry < 0x100000000UL; in load_binary()
34 return 0; in load_binary()
44 return 0; in init_loader_binfmt()
/kernel/linux/linux-5.10/arch/powerpc/include/asm/
Dkdump.h7 #define KDUMP_KERNELBASE 0x2000000
12 #define KDUMP_RESERVE_LIMIT 0x10000 /* 64K */
23 #define KDUMP_TRAMPOLINE_START 0x0100
24 #define KDUMP_TRAMPOLINE_END 0x3000
26 #define KDUMP_TRAMPOLINE_START (0x0100 + PAGE_OFFSET)
27 #define KDUMP_TRAMPOLINE_END (0x3000 + PAGE_OFFSET)
/kernel/linux/linux-4.19/arch/powerpc/include/asm/
Dkdump.h7 #define KDUMP_KERNELBASE 0x2000000
12 #define KDUMP_RESERVE_LIMIT 0x10000 /* 64K */
23 #define KDUMP_TRAMPOLINE_START 0x0100
24 #define KDUMP_TRAMPOLINE_END 0x3000
26 #define KDUMP_TRAMPOLINE_START (0x0100 + PAGE_OFFSET)
27 #define KDUMP_TRAMPOLINE_END (0x3000 + PAGE_OFFSET)
/kernel/linux/linux-5.10/drivers/net/dsa/mv88e6xxx/
Dport.h16 /* Offset 0x00: Port Status Register */
17 #define MV88E6XXX_PORT_STS 0x00
18 #define MV88E6XXX_PORT_STS_PAUSE_EN 0x8000
19 #define MV88E6XXX_PORT_STS_MY_PAUSE 0x4000
20 #define MV88E6XXX_PORT_STS_HD_FLOW 0x2000
21 #define MV88E6XXX_PORT_STS_PHY_DETECT 0x1000
22 #define MV88E6250_PORT_STS_LINK 0x1000
23 #define MV88E6250_PORT_STS_PORTMODE_MASK 0x0f00
24 #define MV88E6250_PORT_STS_PORTMODE_PHY_10_HALF 0x0800
25 #define MV88E6250_PORT_STS_PORTMODE_PHY_100_HALF 0x0900
[all …]
Dglobal1.h16 /* Offset 0x00: Switch Global Status Register */
17 #define MV88E6XXX_G1_STS 0x00
18 #define MV88E6352_G1_STS_PPU_STATE 0x8000
19 #define MV88E6185_G1_STS_PPU_STATE_MASK 0xc000
20 #define MV88E6185_G1_STS_PPU_STATE_DISABLED_RST 0x0000
21 #define MV88E6185_G1_STS_PPU_STATE_INITIALIZING 0x4000
22 #define MV88E6185_G1_STS_PPU_STATE_DISABLED 0x8000
23 #define MV88E6185_G1_STS_PPU_STATE_POLLING 0xc000
24 #define MV88E6XXX_G1_STS_INIT_READY 0x0800
33 #define MV88E6XXX_G1_STS_IRQ_EEPROM_DONE 0
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_2_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
Duvd_5_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
Duvd_6_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_2_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
Duvd_5_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
Duvd_6_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
Duvd_3_1_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
/kernel/linux/linux-4.19/arch/alpha/kernel/
Dbinfmt_loader.c16 if (eh->fh.f_magic != 0x183 || (eh->fh.f_flags & 0x3000) != 0x3000) in load_binary()
34 bprm->taso = eh->ah.entry < 0x100000000UL; in load_binary()
39 if (retval < 0) in load_binary()
51 return 0; in init_loader_binfmt()

12345678910>>...41