Searched +full:0 +full:x328 (Results 1 – 25 of 199) sorted by relevance
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/power/reset/ |
| D | keystone-reset.txt | 32 in format: <0>, <2>; It can be in random order and
33 begins from 0 to 3, as keystone can contain up to 4 SoC
42 reg = <0x02310000 0x200>;
47 reg = <0x02620000 0x1000>;
52 ti,syscon-pll = <&pllctrl 0xe4>;
53 ti,syscon-dev = <&devctrl 0x328>;
54 ti,wdt-list = <0>;
63 ti,syscon-pll = <&pllctrl 0xe4>;
64 ti,syscon-dev = <&devctrl 0x328>;
65 ti,wdt-list = <0>, <2>;
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/power/reset/ |
| D | keystone-reset.txt | 32 in format: <0>, <2>; It can be in random order and
33 begins from 0 to 3, as keystone can contain up to 4 SoC
42 reg = <0x02310000 0x200>;
47 reg = <0x02620000 0x1000>;
52 ti,syscon-pll = <&pllctrl 0xe4>;
53 ti,syscon-dev = <&devctrl 0x328>;
54 ti,wdt-list = <0>;
63 ti,syscon-pll = <&pllctrl 0xe4>;
64 ti,syscon-dev = <&devctrl 0x328>;
65 ti,wdt-list = <0>, <2>;
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| /kernel/linux/linux-4.19/arch/s390/kernel/ |
| D | swsusp.S | 20 * Save register context in absolute 0 lowcore and call swsusp_save() to
41 stnsm __SF_EMPTY(%r15),0xfb
50 lghi %r1,0x1000
56 mvc 0x318(4,%r1),__SF_EMPTY(%r15) /* move prefix to lowcore */
57 stam %a0,%a15,0x340(%r1) /* store access registers */
58 stctg %c0,%c15,0x380(%r1) /* store control registers */
59 stmg %r0,%r15,0x280(%r1) /* store general registers */
61 stpt 0x328(%r1) /* store timer */
63 stckc 0x330(%r1) /* store clock comparator */
67 slg %r0,0x328(%r1)
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/mmc/ |
| D | tmio_mmc.txt | 57 - pinctrl-0: should contain default/high speed pin ctrl
64 reg = <0 0xee100000 0 0x328>;
67 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
68 <&dmac1 0xcd>, <&dmac1 0xce>;
77 reg = <0 0xee120000 0 0x328>;
80 dmas = <&dmac0 0xc9>, <&dmac0 0xca>,
81 <&dmac1 0xc9>, <&dmac1 0xca>;
90 reg = <0 0xee140000 0 0x100>;
93 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
94 <&dmac1 0xc1>, <&dmac1 0xc2>;
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/ |
| D | renesas,sdhi.yaml | 100 pinctrl-0:
148 reg = <0xee100000 0x328>;
151 dmas = <&dmac0 0xcd>, <&dmac0 0xce>, <&dmac1 0xcd>, <&dmac1 0xce>;
160 reg = <0xee120000 0x328>;
163 dmas = <&dmac0 0xc9>, <&dmac0 0xca>, <&dmac1 0xc9>, <&dmac1 0xca>;
172 reg = <0xee140000 0x100>;
175 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, <&dmac1 0xc1>, <&dmac1 0xc2>;
184 reg = <0xee160000 0x100>;
187 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, <&dmac1 0xd3>, <&dmac1 0xd4>;
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| /kernel/linux/linux-5.10/drivers/memory/tegra/ |
| D | tegra210-mc.h | 12 #define MC_LATENCY_ALLOWANCE_AVPC_0 0x2e4
13 #define MC_LATENCY_ALLOWANCE_HC_0 0x310
14 #define MC_LATENCY_ALLOWANCE_HC_1 0x314
15 #define MC_LATENCY_ALLOWANCE_MPCORE_0 0x320
16 #define MC_LATENCY_ALLOWANCE_NVENC_0 0x328
17 #define MC_LATENCY_ALLOWANCE_PPCS_0 0x344
18 #define MC_LATENCY_ALLOWANCE_PPCS_1 0x348
19 #define MC_LATENCY_ALLOWANCE_ISP2_0 0x370
20 #define MC_LATENCY_ALLOWANCE_ISP2_1 0x374
21 #define MC_LATENCY_ALLOWANCE_XUSB_0 0x37c
[all …]
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| /kernel/linux/linux-5.10/drivers/net/wireless/quantenna/qtnfmac/pcie/ |
| D | topaz_pcie_regs.h | 8 #define PCIE_DMA_WR_INTR_STATUS(base) ((base) + 0x9bc)
9 #define PCIE_DMA_WR_INTR_MASK(base) ((base) + 0x9c4)
10 #define PCIE_DMA_WR_INTR_CLR(base) ((base) + 0x9c8)
11 #define PCIE_DMA_WR_ERR_STATUS(base) ((base) + 0x9cc)
12 #define PCIE_DMA_WR_DONE_IMWR_ADDR_LOW(base) ((base) + 0x9D0)
13 #define PCIE_DMA_WR_DONE_IMWR_ADDR_HIGH(base) ((base) + 0x9d4)
15 #define PCIE_DMA_RD_INTR_STATUS(base) ((base) + 0x310)
16 #define PCIE_DMA_RD_INTR_MASK(base) ((base) + 0x319)
17 #define PCIE_DMA_RD_INTR_CLR(base) ((base) + 0x31c)
18 #define PCIE_DMA_RD_ERR_STATUS_LOW(base) ((base) + 0x324)
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/radeon/ |
| D | avivod.h | 31 #define D1CRTC_CONTROL 0x6080
32 #define CRTC_EN (1 << 0)
33 #define D1CRTC_STATUS 0x609c
34 #define D1CRTC_UPDATE_LOCK 0x60E8
35 #define D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110
36 #define D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118
38 #define D2CRTC_CONTROL 0x6880
39 #define D2CRTC_STATUS 0x689c
40 #define D2CRTC_UPDATE_LOCK 0x68E8
41 #define D2GRPH_PRIMARY_SURFACE_ADDRESS 0x6910
[all …]
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| /kernel/linux/linux-4.19/drivers/gpu/drm/radeon/ |
| D | avivod.h | 31 #define D1CRTC_CONTROL 0x6080
32 #define CRTC_EN (1 << 0)
33 #define D1CRTC_STATUS 0x609c
34 #define D1CRTC_UPDATE_LOCK 0x60E8
35 #define D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110
36 #define D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118
38 #define D2CRTC_CONTROL 0x6880
39 #define D2CRTC_STATUS 0x689c
40 #define D2CRTC_UPDATE_LOCK 0x68E8
41 #define D2GRPH_PRIMARY_SURFACE_ADDRESS 0x6910
[all …]
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| /kernel/linux/linux-5.10/include/dt-bindings/clock/ |
| D | am4.h | 8 #define AM4_CLKCTRL_OFFSET 0x20
14 #define AM4_ADC_TSC_CLKCTRL AM4_CLKCTRL_INDEX(0x120)
15 #define AM4_L4_WKUP_CLKCTRL AM4_CLKCTRL_INDEX(0x220)
16 #define AM4_WKUP_M3_CLKCTRL AM4_CLKCTRL_INDEX(0x228)
17 #define AM4_COUNTER_32K_CLKCTRL AM4_CLKCTRL_INDEX(0x230)
18 #define AM4_TIMER1_CLKCTRL AM4_CLKCTRL_INDEX(0x328)
19 #define AM4_WD_TIMER2_CLKCTRL AM4_CLKCTRL_INDEX(0x338)
20 #define AM4_I2C1_CLKCTRL AM4_CLKCTRL_INDEX(0x340)
21 #define AM4_UART1_CLKCTRL AM4_CLKCTRL_INDEX(0x348)
22 #define AM4_SMARTREFLEX0_CLKCTRL AM4_CLKCTRL_INDEX(0x350)
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/clock/ |
| D | vt8500.txt | 19 - #clock-cells : from common clock binding; shall be set to 0.
24 - #clock-cells : from common clock binding; shall be set to 0.
47 - divisor-mask : shall be the mask for the divisor register. Defaults to 0x1f
54 #clock-cells = <0>;
60 #clock-cells = <0>;
63 reg = <0x200>;
67 #clock-cells = <0>;
70 divisor-reg = <0x328>;
71 divisor-mask = <0x3f>;
72 enable-reg = <0x254>;
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | vt8500.txt | 19 - #clock-cells : from common clock binding; shall be set to 0.
24 - #clock-cells : from common clock binding; shall be set to 0.
47 - divisor-mask : shall be the mask for the divisor register. Defaults to 0x1f
54 #clock-cells = <0>;
60 #clock-cells = <0>;
63 reg = <0x200>;
67 #clock-cells = <0>;
70 divisor-reg = <0x328>;
71 divisor-mask = <0x3f>;
72 enable-reg = <0x254>;
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| /kernel/linux/linux-5.10/include/linux/bcma/ |
| D | bcma_driver_gmac_cmn.h | 7 #define BCMA_GMAC_CMN_STAG0 0x000
8 #define BCMA_GMAC_CMN_STAG1 0x004
9 #define BCMA_GMAC_CMN_STAG2 0x008
10 #define BCMA_GMAC_CMN_STAG3 0x00C
11 #define BCMA_GMAC_CMN_PARSER_CTL 0x020
12 #define BCMA_GMAC_CMN_MIB_MAX_LEN 0x024
13 #define BCMA_GMAC_CMN_PHY_ACCESS 0x100
14 #define BCMA_GMAC_CMN_PA_DATA_MASK 0x0000ffff
15 #define BCMA_GMAC_CMN_PA_ADDR_MASK 0x001f0000
17 #define BCMA_GMAC_CMN_PA_REG_MASK 0x1f000000
[all …]
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| /kernel/linux/linux-4.19/include/linux/bcma/ |
| D | bcma_driver_gmac_cmn.h | 7 #define BCMA_GMAC_CMN_STAG0 0x000
8 #define BCMA_GMAC_CMN_STAG1 0x004
9 #define BCMA_GMAC_CMN_STAG2 0x008
10 #define BCMA_GMAC_CMN_STAG3 0x00C
11 #define BCMA_GMAC_CMN_PARSER_CTL 0x020
12 #define BCMA_GMAC_CMN_MIB_MAX_LEN 0x024
13 #define BCMA_GMAC_CMN_PHY_ACCESS 0x100
14 #define BCMA_GMAC_CMN_PA_DATA_MASK 0x0000ffff
15 #define BCMA_GMAC_CMN_PA_ADDR_MASK 0x001f0000
17 #define BCMA_GMAC_CMN_PA_REG_MASK 0x1f000000
[all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | imx25-pinfunc.h | 16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
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| D | imx50-pinfunc.h | 13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0
14 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0
15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0
16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0
17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0
18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0
19 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0
20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0
21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0
22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0
[all …]
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| D | keystone.dtsi | 27 reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
34 reg = <0x0 0x02561000 0x0 0x1000>,
35 <0x0 0x02562000 0x0 0x2000>,
36 <0x0 0x02564000 0x0 0x2000>,
37 <0x0 0x02566000 0x0 0x2000>;
66 cpu_suspend = <0x84000001>;
67 cpu_off = <0x84000002>;
68 cpu_on = <0x84000003>;
71 soc0: soc@0 {
76 ranges = <0x0 0x0 0x0 0xc0000000>;
[all …]
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| /kernel/linux/linux-5.10/drivers/scsi/cxlflash/ |
| D | main.h | 25 #define PCI_DEVICE_ID_IBM_CORSA 0x04F0
26 #define PCI_DEVICE_ID_IBM_FLASH_GT 0x0600
27 #define PCI_DEVICE_ID_IBM_BRIARD 0x0624
29 /* Since there is only one target, make it 0 */
30 #define CXLFLASH_TARGET 0
40 #define FC_MTIP_CMDCONFIG 0x010
41 #define FC_MTIP_STATUS 0x018
42 #define FC_MAX_NUM_LUNS 0x080 /* Max LUNs host can provision for port */
43 #define FC_CUR_NUM_LUNS 0x088 /* Cur number LUNs provisioned for port */
44 #define FC_MAX_CAP_PORT 0x090 /* Max capacity all LUNs for port (4K blocks) */
[all …]
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| /kernel/linux/linux-5.10/arch/m68k/ |
| D | Kconfig.machine | 189 Initialize the LCD controller of the 68x328 processor.
195 Reserve certain memory regions on 68x328 based boards.
340 default "0"
343 0, the base of the address space. And this is the default. Some
348 hex "Size of RAM (in bytes), or 0 for automatic"
349 default "0x400000"
351 Define the size of the system RAM. If you select 0 then the
357 default "0"
366 default "0x10000000"
372 ColdFire boards use the default 0x10000000 value, so if unsure then
[all …]
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| /kernel/linux/linux-4.19/arch/m68k/ |
| D | Kconfig.machine | 183 Initialize the LCD controller of the 68x328 processor.
189 Reserve certain memory regions on 68x328 based boards.
335 default "0"
338 0, the base of the address space. And this is the default. Some
343 hex "Size of RAM (in bytes), or 0 for automatic"
344 default "0x400000"
346 Define the size of the system RAM. If you select 0 then the
352 default "0"
361 default "0x10000000"
367 ColdFire boards use the default 0x10000000 value, so if unsure then
[all …]
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/ |
| D | imx8mn-pinfunc.h | 14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
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| /kernel/linux/linux-4.19/arch/arm/boot/dts/ |
| D | imx50-pinfunc.h | 17 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0
18 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0
19 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0
20 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0
21 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0
22 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0
23 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0
24 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0
25 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0
26 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0
[all …]
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| D | keystone.dtsi | 27 reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
34 reg = <0x0 0x02561000 0x0 0x1000>,
35 <0x0 0x02562000 0x0 0x2000>,
36 <0x0 0x02564000 0x0 0x2000>,
37 <0x0 0x02566000 0x0 0x2000>;
66 cpu_suspend = <0x84000001>;
67 cpu_off = <0x84000002>;
68 cpu_on = <0x84000003>;
71 soc0: soc@0 {
76 ranges = <0x0 0x0 0x0 0xc0000000>;
[all …]
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| /kernel/linux/linux-4.19/drivers/scsi/cxlflash/ |
| D | main.h | 29 #define PCI_DEVICE_ID_IBM_CORSA 0x04F0
30 #define PCI_DEVICE_ID_IBM_FLASH_GT 0x0600
31 #define PCI_DEVICE_ID_IBM_BRIARD 0x0624
33 /* Since there is only one target, make it 0 */
34 #define CXLFLASH_TARGET 0
44 #define FC_MTIP_CMDCONFIG 0x010
45 #define FC_MTIP_STATUS 0x018
46 #define FC_MAX_NUM_LUNS 0x080 /* Max LUNs host can provision for port */
47 #define FC_CUR_NUM_LUNS 0x088 /* Cur number LUNs provisioned for port */
48 #define FC_MAX_CAP_PORT 0x090 /* Max capacity all LUNs for port (4K blocks) */
[all …]
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| /kernel/linux/linux-5.10/drivers/misc/habanalabs/include/goya/asic_reg/ |
| D | pci_nrtr_regs.h | 22 #define mmPCI_NRTR_HBW_MAX_CRED 0x100
24 #define mmPCI_NRTR_LBW_MAX_CRED 0x120
26 #define mmPCI_NRTR_DBG_E_ARB 0x300
28 #define mmPCI_NRTR_DBG_W_ARB 0x304
30 #define mmPCI_NRTR_DBG_N_ARB 0x308
32 #define mmPCI_NRTR_DBG_S_ARB 0x30C
34 #define mmPCI_NRTR_DBG_L_ARB 0x310
36 #define mmPCI_NRTR_DBG_E_ARB_MAX 0x320
38 #define mmPCI_NRTR_DBG_W_ARB_MAX 0x324
40 #define mmPCI_NRTR_DBG_N_ARB_MAX 0x328
[all …]
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