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/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dstm32mp151.dtsi16 #size-cells = <0>;
18 cpu0: cpu@0 {
22 reg = <0>;
42 reg = <0xa0021000 0x1000>,
43 <0xa0022000 0x2000>;
57 #clock-cells = <0>;
63 #clock-cells = <0>;
69 #clock-cells = <0>;
75 #clock-cells = <0>;
81 #clock-cells = <0>;
[all …]
Dstm32f429.dtsi58 #clock-cells = <0>;
60 clock-frequency = <0>;
64 #clock-cells = <0>;
70 #clock-cells = <0>;
76 #clock-cells = <0>;
78 clock-frequency = <0>;
85 reg = <0x1fff7800 0x400>;
89 reg = <0x22c 0x2>;
92 reg = <0x22e 0x2>;
98 reg = <0x40000000 0x400>;
[all …]
Dstm32f746.dtsi53 #clock-cells = <0>;
55 clock-frequency = <0>;
59 #clock-cells = <0>;
65 #clock-cells = <0>;
71 #clock-cells = <0>;
80 reg = <0x40000000 0x400>;
82 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
88 #size-cells = <0>;
90 reg = <0x40000000 0x400>;
91 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
[all …]
Dkeystone-k2hk-clocks.dtsi10 #clock-cells = <0>;
14 reg = <0x02620370 4>;
19 #clock-cells = <0>;
22 reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
27 #clock-cells = <0>;
31 reg = <0x02620358 4>;
36 #clock-cells = <0>;
40 reg = <0x02620360 4>;
45 #clock-cells = <0>;
49 reg = <0x02620368 4>;
[all …]
Defm32gg.dtsi32 reg = <0x40002000 0x400>;
40 reg = <0x40006000 0x1000>;
52 #size-cells = <0>;
54 reg = <0x4000a000 0x400>;
63 #size-cells = <0>;
65 reg = <0x4000a400 0x400>;
74 #size-cells = <0>;
76 reg = <0x4000c000 0x400>;
84 #size-cells = <0>;
86 reg = <0x4000c400 0x400>;
[all …]
Dkeystone-k2l-clocks.dtsi10 #clock-cells = <0>;
14 reg = <0x02620370 4>;
19 #clock-cells = <0>;
22 reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
27 #clock-cells = <0>;
31 reg = <0x02620358 4>;
36 #clock-cells = <0>;
40 reg = <0x02620360 4>;
45 #clock-cells = <0>;
50 reg = <0x02350004 0xb00>, <0x02350000 0x400>;
[all …]
Dkeystone-clocks.dtsi14 #clock-cells = <0>;
17 reg = <0x02310108 4>;
24 #clock-cells = <0>;
33 #clock-cells = <0>;
42 #clock-cells = <0>;
45 reg = <0x02310120 4>;
46 bit-shift = <0>;
52 #clock-cells = <0>;
55 reg = <0x02310164 4>;
56 bit-shift = <0>;
[all …]
Dstm32h743.dtsi54 #clock-cells = <0>;
56 clock-frequency = <0>;
60 #clock-cells = <0>;
66 #clock-cells = <0>;
68 clock-frequency = <0>;
75 reg = <0x40000c00 0x400>;
82 #size-cells = <0>;
84 reg = <0x40002400 0x400>;
95 trigger@0 {
97 reg = <0>;
[all …]
Domap2.dtsi32 #address-cells = <0>;
33 #size-cells = <0>;
64 reg = <0x480a6000 0x50>;
72 reg = <0x480b2000 0x1000>;
80 reg = <0x480FE000 0x1000>;
85 reg = <0x48056000 0x4>,
86 <0x4805602c 0x4>,
87 <0x48056028 0x4>;
101 ranges = <0 0x48056000 0x1000>;
103 sdma: dma-controller@0 {
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/crypto/
Dhisilicon,hip07-sec.txt9 Region 0 has registers to control the backend processing engines.
16 Interrupt 0 is for the SEC unit error queue.
29 reg = <0x400 0xd0000000 0x0 0x10000
30 0x400 0xd2000000 0x0 0x10000
31 0x400 0xd2010000 0x0 0x10000
32 0x400 0xd2020000 0x0 0x10000
33 0x400 0xd2030000 0x0 0x10000
34 0x400 0xd2040000 0x0 0x10000
35 0x400 0xd2050000 0x0 0x10000
36 0x400 0xd2060000 0x0 0x10000
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/crypto/
Dhisilicon,hip07-sec.txt9 Region 0 has registers to control the backend processing engines.
16 Interrupt 0 is for the SEC unit error queue.
29 reg = <0x400 0xd0000000 0x0 0x10000
30 0x400 0xd2000000 0x0 0x10000
31 0x400 0xd2010000 0x0 0x10000
32 0x400 0xd2020000 0x0 0x10000
33 0x400 0xd2030000 0x0 0x10000
34 0x400 0xd2040000 0x0 0x10000
35 0x400 0xd2050000 0x0 0x10000
36 0x400 0xd2060000 0x0 0x10000
[all …]
/kernel/linux/linux-4.19/drivers/soc/renesas/
Dr8a77980-sysc.c17 { "always-on", 0, 0, R8A77980_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
18 { "ca53-scu", 0x140, 0, R8A77980_PD_CA53_SCU, R8A77980_PD_ALWAYS_ON,
20 { "ca53-cpu0", 0x200, 0, R8A77980_PD_CA53_CPU0, R8A77980_PD_CA53_SCU,
22 { "ca53-cpu1", 0x200, 1, R8A77980_PD_CA53_CPU1, R8A77980_PD_CA53_SCU,
24 { "ca53-cpu2", 0x200, 2, R8A77980_PD_CA53_CPU2, R8A77980_PD_CA53_SCU,
26 { "ca53-cpu3", 0x200, 3, R8A77980_PD_CA53_CPU3, R8A77980_PD_CA53_SCU,
28 { "cr7", 0x240, 0, R8A77980_PD_CR7, R8A77980_PD_ALWAYS_ON },
29 { "a3ir", 0x180, 0, R8A77980_PD_A3IR, R8A77980_PD_ALWAYS_ON },
30 { "a2ir0", 0x400, 0, R8A77980_PD_A2IR0, R8A77980_PD_A3IR },
31 { "a2ir1", 0x400, 1, R8A77980_PD_A2IR1, R8A77980_PD_A3IR },
[all …]
/kernel/linux/linux-5.10/drivers/soc/renesas/
Dr8a77980-sysc.c17 { "always-on", 0, 0, R8A77980_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
18 { "ca53-scu", 0x140, 0, R8A77980_PD_CA53_SCU, R8A77980_PD_ALWAYS_ON,
20 { "ca53-cpu0", 0x200, 0, R8A77980_PD_CA53_CPU0, R8A77980_PD_CA53_SCU,
22 { "ca53-cpu1", 0x200, 1, R8A77980_PD_CA53_CPU1, R8A77980_PD_CA53_SCU,
24 { "ca53-cpu2", 0x200, 2, R8A77980_PD_CA53_CPU2, R8A77980_PD_CA53_SCU,
26 { "ca53-cpu3", 0x200, 3, R8A77980_PD_CA53_CPU3, R8A77980_PD_CA53_SCU,
28 { "cr7", 0x240, 0, R8A77980_PD_CR7, R8A77980_PD_ALWAYS_ON },
29 { "a3ir", 0x180, 0, R8A77980_PD_A3IR, R8A77980_PD_ALWAYS_ON },
30 { "a2ir0", 0x400, 0, R8A77980_PD_A2IR0, R8A77980_PD_A3IR },
31 { "a2ir1", 0x400, 1, R8A77980_PD_A2IR1, R8A77980_PD_A3IR },
[all …]
/kernel/linux/linux-4.19/arch/arm/boot/dts/
Dstm32mp157c.dtsi16 #size-cells = <0>;
18 cpu0: cpu@0 {
21 reg = <0>;
34 cpu_off = <0x84000002>;
35 cpu_on = <0x84000003>;
42 reg = <0xa0021000 0x1000>,
43 <0xa0022000 0x2000>;
57 #clock-cells = <0>;
63 #clock-cells = <0>;
69 #clock-cells = <0>;
[all …]
Dstm32f429.dtsi56 #clock-cells = <0>;
58 clock-frequency = <0>;
62 #clock-cells = <0>;
68 #clock-cells = <0>;
74 #clock-cells = <0>;
76 clock-frequency = <0>;
83 reg = <0x40000000 0x400>;
85 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
91 #size-cells = <0>;
93 reg = <0x40000000 0x400>;
[all …]
Dstm32f746.dtsi51 #clock-cells = <0>;
53 clock-frequency = <0>;
57 #clock-cells = <0>;
63 #clock-cells = <0>;
69 #clock-cells = <0>;
78 reg = <0x40000000 0x400>;
80 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
86 #size-cells = <0>;
88 reg = <0x40000000 0x400>;
89 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
[all …]
Dkeystone-k2hk-clocks.dtsi10 #clock-cells = <0>;
14 reg = <0x02620370 4>;
19 #clock-cells = <0>;
22 reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
27 #clock-cells = <0>;
31 reg = <0x02620358 4>;
36 #clock-cells = <0>;
40 reg = <0x02620360 4>;
45 #clock-cells = <0>;
49 reg = <0x02620368 4>;
[all …]
Defm32gg.dtsi32 reg = <0x40002000 0x400>;
40 reg = <0x40006000 0x1000>;
52 #size-cells = <0>;
54 reg = <0x4000a000 0x400>;
63 #size-cells = <0>;
65 reg = <0x4000a400 0x400>;
74 #size-cells = <0>;
76 reg = <0x4000c000 0x400>;
84 #size-cells = <0>;
86 reg = <0x4000c400 0x400>;
[all …]
Dkeystone-k2l-clocks.dtsi10 #clock-cells = <0>;
14 reg = <0x02620370 4>;
19 #clock-cells = <0>;
22 reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
27 #clock-cells = <0>;
31 reg = <0x02620358 4>;
36 #clock-cells = <0>;
40 reg = <0x02620360 4>;
45 #clock-cells = <0>;
50 reg = <0x02350004 0xb00>, <0x02350000 0x400>;
[all …]
Dstm32h743.dtsi52 #clock-cells = <0>;
54 clock-frequency = <0>;
58 #clock-cells = <0>;
64 #clock-cells = <0>;
66 clock-frequency = <0>;
73 reg = <0x40000c00 0x400>;
80 #size-cells = <0>;
82 reg = <0x40002400 0x400>;
93 trigger@0 {
95 reg = <0>;
[all …]
Dkeystone-clocks.dtsi14 #clock-cells = <0>;
17 reg = <0x02310108 4>;
24 #clock-cells = <0>;
33 #clock-cells = <0>;
42 #clock-cells = <0>;
45 reg = <0x02310120 4>;
46 bit-shift = <0>;
52 #clock-cells = <0>;
55 reg = <0x02310164 4>;
56 bit-shift = <0>;
[all …]
Domap2.dtsi31 #address-cells = <0>;
32 #size-cells = <0>;
63 reg = <0x480a6000 0x50>;
71 reg = <0x480b2000 0x1000>;
79 reg = <0x480FE000 0x1000>;
85 reg = <0x48056000 0x1000>;
98 reg = <0x48070000 0x80>;
100 #size-cells = <0>;
109 reg = <0x48072000 0x80>;
111 #size-cells = <0>;
[all …]
/kernel/linux/linux-4.19/drivers/staging/xgifb/
Dvb_table.h5 {0x16, 0x01, 0x01, 166},
6 {0x19, 0x02, 0x01, 124},
7 {0x7C, 0x08, 0x01, 200},
11 {0x5c, 0x23, 0x01, 166},
12 {0x19, 0x02, 0x01, 124},
13 {0x7C, 0x08, 0x80, 200},
17 {0x5c, 0x23, 0x01, 166},
18 {0x55, 0x84, 0x01, 123},
19 {0x7C, 0x08, 0x01, 200},
23 0x32, 0x32, 0x42 /* SR18 */
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/mfd/
Dstm32-timers.txt35 #size-cells = <0>;
37 reg = <0x40010000 0x400>;
38 clocks = <&rcc 0 160>;
43 pinctrl-0 = <&pwm1_pins>;
47 timer@0 {
49 reg = <0>;
56 dmas = <&dmamux1 11 0x400 0x0>,
57 <&dmamux1 12 0x400 0x0>,
58 <&dmamux1 13 0x400 0x0>,
59 <&dmamux1 14 0x400 0x0>,
[all …]
/kernel/linux/linux-5.10/sound/soc/uniphier/
Daio-reg.h14 #define SG_AOUTEN 0x1c04
17 #define A2CHNMAPCTR0(n) (0x00000 + 0x40 * (n))
18 #define A2RBNMAPCTR0(n) (0x01000 + 0x40 * (n))
19 #define A2IPORTNMAPCTR0(n) (0x02000 + 0x40 * (n))
20 #define A2IPORTNMAPCTR1(n) (0x02004 + 0x40 * (n))
21 #define A2IIFNMAPCTR0(n) (0x03000 + 0x40 * (n))
22 #define A2OPORTNMAPCTR0(n) (0x04000 + 0x40 * (n))
23 #define A2OPORTNMAPCTR1(n) (0x04004 + 0x40 * (n))
24 #define A2OPORTNMAPCTR2(n) (0x04008 + 0x40 * (n))
25 #define A2OIFNMAPCTR0(n) (0x05000 + 0x40 * (n))
[all …]

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