Searched +full:0 +full:x414 (Results 1 – 25 of 174) sorted by relevance
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/serial/ |
| D | st,stm32-usart.txt | 26 reg = <0x40004c00 0x400>;
30 pinctrl-0 = <&pinctrl_usart4>;
35 reg = <0x40004400 0x400>;
40 pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rtscts>;
45 reg = <0x40011000 0x400>;
47 clocks = <&rcc 0 164>;
48 dmas = <&dma2 2 4 0x414 0x0>,
49 <&dma2 7 4 0x414 0x0>;
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/serial/ |
| D | st,stm32-uart.yaml | 88 reg = <0x40011000 0x400>;
90 clocks = <&rcc 0 164>;
91 dmas = <&dma2 2 4 0x414 0x0>,
92 <&dma2 7 4 0x414 0x0>;
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/dma/ |
| D | stm32-dmamux.txt | 27 reg = <0x40020000 0x400>;
47 reg = <0x40020400 0x400>;
67 reg = <0x40020800 0x3c>;
78 reg = <0x40011000 0x400>;
81 dmas = <&dmamux1 41 0x414 0>,
82 <&dmamux1 42 0x414 0>;
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| /kernel/linux/linux-5.10/arch/arm/mach-omap2/ |
| D | omap-wakeupgen.h | 12 #define OMAP_WKUPGEN_BASE 0x48281000
14 #define OMAP_WKG_CONTROL_0 0x00
15 #define OMAP_WKG_ENB_A_0 0x10
16 #define OMAP_WKG_ENB_B_0 0x14
17 #define OMAP_WKG_ENB_C_0 0x18
18 #define OMAP_WKG_ENB_D_0 0x1c
19 #define OMAP_WKG_ENB_E_0 0x20
20 #define OMAP_WKG_ENB_A_1 0x410
21 #define OMAP_WKG_ENB_B_1 0x414
22 #define OMAP_WKG_ENB_C_1 0x418
[all …]
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| /kernel/linux/linux-4.19/arch/arm/mach-omap2/ |
| D | omap-wakeupgen.h | 15 #define OMAP_WKUPGEN_BASE 0x48281000
17 #define OMAP_WKG_CONTROL_0 0x00
18 #define OMAP_WKG_ENB_A_0 0x10
19 #define OMAP_WKG_ENB_B_0 0x14
20 #define OMAP_WKG_ENB_C_0 0x18
21 #define OMAP_WKG_ENB_D_0 0x1c
22 #define OMAP_WKG_ENB_E_0 0x20
23 #define OMAP_WKG_ENB_A_1 0x410
24 #define OMAP_WKG_ENB_B_1 0x414
25 #define OMAP_WKG_ENB_C_1 0x418
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/dpu1/ |
| D | dpu_hwio.h | 13 #define DISP_INTF_SEL 0x004
14 #define INTR_EN 0x010
15 #define INTR_STATUS 0x014
16 #define INTR_CLEAR 0x018
17 #define INTR2_EN 0x008
18 #define INTR2_STATUS 0x00c
19 #define INTR2_CLEAR 0x02c
20 #define HIST_INTR_EN 0x01c
21 #define HIST_INTR_STATUS 0x020
22 #define HIST_INTR_CLEAR 0x024
[all …]
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| /kernel/linux/linux-4.19/drivers/usb/musb/ |
| D | omap2430.h | 15 #define OTG_REVISION 0x400
17 #define OTG_SYSCONFIG 0x404
19 # define FORCESTDBY (0 << MIDLEMODE)
24 # define FORCEIDLE (0 << SIDLEMODE)
30 # define AUTOIDLE (1 << 0)
32 #define OTG_SYSSTATUS 0x408
33 # define RESETDONE (1 << 0)
35 #define OTG_INTERFSEL 0x40c
37 # define PHYSEL 0 /* bit position */
38 # define UTMI_8BIT (0 << PHYSEL)
[all …]
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| /kernel/linux/linux-5.10/drivers/usb/musb/ |
| D | omap2430.h | 15 #define OTG_REVISION 0x400
17 #define OTG_SYSCONFIG 0x404
19 # define FORCESTDBY (0 << MIDLEMODE)
24 # define FORCEIDLE (0 << SIDLEMODE)
30 # define AUTOIDLE (1 << 0)
32 #define OTG_SYSSTATUS 0x408
33 # define RESETDONE (1 << 0)
35 #define OTG_INTERFSEL 0x40c
37 # define PHYSEL 0 /* bit position */
38 # define UTMI_8BIT (0 << PHYSEL)
[all …]
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| /kernel/linux/linux-4.19/drivers/gpu/drm/msm/disp/dpu1/ |
| D | dpu_hwio.h | 21 #define DISP_INTF_SEL 0x004
22 #define INTR_EN 0x010
23 #define INTR_STATUS 0x014
24 #define INTR_CLEAR 0x018
25 #define INTR2_EN 0x008
26 #define INTR2_STATUS 0x00c
27 #define INTR2_CLEAR 0x02c
28 #define HIST_INTR_EN 0x01c
29 #define HIST_INTR_STATUS 0x020
30 #define HIST_INTR_CLEAR 0x024
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/media/ |
| D | st,stm32-dcmi.txt | 27 reg = <0x50050000 0x400>;
30 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
33 pinctrl-0 = <&dcmi_pins>;
34 dmas = <&dma2 1 1 0x414 0x3>;
40 hsync-active = <0>;
41 vsync-active = <0>;
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| /kernel/linux/linux-5.10/arch/mips/include/asm/netlogic/xlp-hal/ |
| D | cpucontrol.h | 38 #define CPU_BLOCKID_IFU 0
49 #define IFU_BRUB_RESERVE 0x007
51 #define ICU_DEFEATURE 0x100
53 #define LSU_DEFEATURE 0x304
54 #define LSU_DEBUG_ADDR 0x305
55 #define LSU_DEBUG_DATA0 0x306
56 #define LSU_CERRLOG_REGID 0x309
57 #define SCHED_DEFEATURE 0x700
60 #define MAP_THREADMODE 0x00
61 #define MAP_EXT_EBASE_ENABLE 0x04
[all …]
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| /kernel/linux/linux-4.19/arch/mips/include/asm/netlogic/xlp-hal/ |
| D | cpucontrol.h | 38 #define CPU_BLOCKID_IFU 0
49 #define IFU_BRUB_RESERVE 0x007
51 #define ICU_DEFEATURE 0x100
53 #define LSU_DEFEATURE 0x304
54 #define LSU_DEBUG_ADDR 0x305
55 #define LSU_DEBUG_DATA0 0x306
56 #define LSU_CERRLOG_REGID 0x309
57 #define SCHED_DEFEATURE 0x700
60 #define MAP_THREADMODE 0x00
61 #define MAP_EXT_EBASE_ENABLE 0x04
[all …]
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/ |
| D | imx8mp-pinfunc.h | 13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
[all …]
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| D | imx8mm-pinfunc.h | 14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0…
20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0…
21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0…
22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0…
23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0…
[all …]
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| D | imx8mq-pinfunc.h | 15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
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| /kernel/linux/linux-5.10/drivers/misc/habanalabs/include/goya/asic_reg/ |
| D | pci_nrtr_regs.h | 22 #define mmPCI_NRTR_HBW_MAX_CRED 0x100
24 #define mmPCI_NRTR_LBW_MAX_CRED 0x120
26 #define mmPCI_NRTR_DBG_E_ARB 0x300
28 #define mmPCI_NRTR_DBG_W_ARB 0x304
30 #define mmPCI_NRTR_DBG_N_ARB 0x308
32 #define mmPCI_NRTR_DBG_S_ARB 0x30C
34 #define mmPCI_NRTR_DBG_L_ARB 0x310
36 #define mmPCI_NRTR_DBG_E_ARB_MAX 0x320
38 #define mmPCI_NRTR_DBG_W_ARB_MAX 0x324
40 #define mmPCI_NRTR_DBG_N_ARB_MAX 0x328
[all …]
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| /kernel/linux/linux-4.19/drivers/media/pci/cx18/ |
| D | cx18-av-core.h | 41 CX18_AV_SVIDEO_LUMA1 = 0x10,
42 CX18_AV_SVIDEO_LUMA2 = 0x20,
43 CX18_AV_SVIDEO_LUMA3 = 0x30,
44 CX18_AV_SVIDEO_LUMA4 = 0x40,
45 CX18_AV_SVIDEO_LUMA5 = 0x50,
46 CX18_AV_SVIDEO_LUMA6 = 0x60,
47 CX18_AV_SVIDEO_LUMA7 = 0x70,
48 CX18_AV_SVIDEO_LUMA8 = 0x80,
49 CX18_AV_SVIDEO_CHROMA4 = 0x400,
50 CX18_AV_SVIDEO_CHROMA5 = 0x500,
[all …]
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| /kernel/linux/linux-5.10/drivers/media/pci/cx18/ |
| D | cx18-av-core.h | 32 CX18_AV_SVIDEO_LUMA1 = 0x10,
33 CX18_AV_SVIDEO_LUMA2 = 0x20,
34 CX18_AV_SVIDEO_LUMA3 = 0x30,
35 CX18_AV_SVIDEO_LUMA4 = 0x40,
36 CX18_AV_SVIDEO_LUMA5 = 0x50,
37 CX18_AV_SVIDEO_LUMA6 = 0x60,
38 CX18_AV_SVIDEO_LUMA7 = 0x70,
39 CX18_AV_SVIDEO_LUMA8 = 0x80,
40 CX18_AV_SVIDEO_CHROMA4 = 0x400,
41 CX18_AV_SVIDEO_CHROMA5 = 0x500,
[all …]
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| /kernel/linux/linux-4.19/drivers/staging/mt7621-pci/ |
| D | pci-mt7621.c | 69 #define RALINK_PCI_CONFIG_ADDR 0x20
70 #define RALINK_PCI_CONFIG_DATA 0x24
71 #define RALINK_PCI_MEMBASE 0x28
72 #define RALINK_PCI_IOBASE 0x2C
77 #define RALINK_PCI_PCICFG_ADDR 0x0000
78 #define RALINK_PCI_PCIMSK_ADDR 0x000C
80 #define RT6855_PCIE0_OFFSET 0x2000
81 #define RT6855_PCIE1_OFFSET 0x3000
82 #define RT6855_PCIE2_OFFSET 0x4000
84 #define RALINK_PCI_BAR0SETUP_ADDR 0x0010
[all …]
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| /kernel/linux/linux-4.19/arch/arm/boot/dts/ |
| D | imx6sl-pinfunc.h | 17 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
18 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
19 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
20 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
21 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
22 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
23 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
24 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
25 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
26 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
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| D | imx53-pinfunc.h | 17 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
18 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
19 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
20 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
21 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
22 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
23 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
24 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
25 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
26 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
[all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | imx6sl-pinfunc.h | 13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
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| D | imx53-pinfunc.h | 13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
[all …]
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| D | imx51-pinfunc.h | 13 #define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0
14 #define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0
15 #define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0
16 #define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0
17 #define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0
18 #define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0
19 #define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0
20 #define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0
21 #define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0
22 #define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0
[all …]
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| /kernel/linux/linux-4.19/drivers/ntb/hw/amd/ |
| D | ntb_hw_amd.h | 55 #define PCI_DEVICE_ID_AMD_NTB 0x145B
57 #define AMD_LINK_STATUS_OFFSET 0x68
58 #define NTB_LIN_STA_ACTIVE_BIT 0x00000002
59 #define NTB_LNK_STA_SPEED_MASK 0x000F0000
60 #define NTB_LNK_STA_WIDTH_MASK 0x03F00000
102 AMD_CNTL_OFFSET = 0x200,
111 AMD_STA_OFFSET = 0x204,
112 AMD_PGSLV_OFFSET = 0x208,
113 AMD_SPAD_MUX_OFFSET = 0x20C,
114 AMD_SPAD_OFFSET = 0x210,
[all …]
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