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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/
Damlogic,meson-g12a-usb3-pcie-phy.yaml53 reg = <0x46000 0x2000>;
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5_cfg.c22 0,
35 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
36 .flush_hw_mask = 0x0003ffff,
40 .base = { 0x01100, 0x01500, 0x01900 },
45 0,
49 .base = { 0x01d00, 0x02100, 0x02500 },
53 0,
57 .base = { 0x02900, 0x02d00 },
60 0,
64 .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5_cfg.c30 0,
43 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
44 .flush_hw_mask = 0x0003ffff,
48 .base = { 0x01100, 0x01500, 0x01900 },
53 0,
57 .base = { 0x01d00, 0x02100, 0x02500 },
61 0,
65 .base = { 0x02900, 0x02d00 },
68 0,
72 .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_catalog.c46 #define INTF_SDM845_MASK (0)
69 .max_mixer_blendstages = 0xb,
85 .max_mixer_blendstages = 0x9,
97 .max_mixer_blendstages = 0xb,
113 .max_mixer_blendstages = 0xb,
129 .base = 0x0, .len = 0x45C,
130 .features = 0,
131 .highest_bank_bit = 0x2,
133 .reg_off = 0x2AC, .bit_off = 0},
135 .reg_off = 0x2B4, .bit_off = 0},
[all …]
/kernel/linux/linux-4.19/drivers/staging/gasket/
Dapex_driver.c35 #define APEX_PCI_VENDOR_ID 0x1ac1
36 #define APEX_PCI_DEVICE_ID 0x089a
39 #define APEX_BAR_OFFSET 0
40 #define APEX_CM_OFFSET 0x1000000
43 #define APEX_BAR_BYTES 0x100000
77 APEX_BAR2_REG_SCU_BASE = 0x1A300,
78 APEX_BAR2_REG_KERNEL_HIB_PAGE_TABLE_SIZE = 0x46000,
79 APEX_BAR2_REG_KERNEL_HIB_EXTENDED_TABLE = 0x46008,
80 APEX_BAR2_REG_KERNEL_HIB_TRANSLATION_ENABLE = 0x46010,
81 APEX_BAR2_REG_KERNEL_HIB_INSTR_QUEUE_INTVECCTL = 0x46018,
[all …]
/kernel/linux/linux-5.10/drivers/staging/gasket/
Dapex_driver.c35 #define APEX_PCI_VENDOR_ID 0x1ac1
36 #define APEX_PCI_DEVICE_ID 0x089a
39 #define APEX_BAR_OFFSET 0
40 #define APEX_CM_OFFSET 0x1000000
43 #define APEX_BAR_BYTES 0x100000
77 APEX_BAR2_REG_SCU_BASE = 0x1A300,
78 APEX_BAR2_REG_KERNEL_HIB_PAGE_TABLE_SIZE = 0x46000,
79 APEX_BAR2_REG_KERNEL_HIB_EXTENDED_TABLE = 0x46008,
80 APEX_BAR2_REG_KERNEL_HIB_TRANSLATION_ENABLE = 0x46010,
81 APEX_BAR2_REG_KERNEL_HIB_INSTR_QUEUE_INTVECCTL = 0x46018,
[all …]
/kernel/linux/linux-5.10/arch/powerpc/boot/dts/fsl/
Dp4080si-post.dtsi37 alloc-ranges = <0 0 0x10 0>;
42 alloc-ranges = <0 0 0x10 0>;
47 alloc-ranges = <0 0 0x10 0>;
52 interrupts = <25 2 0 0>;
57 /* controller at 0x200000 */
63 bus-range = <0x0 0xff>;
67 fsl,liodn-reg = <&guts 0x500>; /* PEX1LIODNR */
68 pcie@0 {
69 reg = <0 0 0 0 0>;
75 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
/kernel/linux/linux-4.19/arch/powerpc/boot/dts/fsl/
Dp4080si-post.dtsi37 alloc-ranges = <0 0 0x10 0>;
42 alloc-ranges = <0 0 0x10 0>;
47 alloc-ranges = <0 0 0x10 0>;
52 interrupts = <25 2 0 0>;
57 /* controller at 0x200000 */
63 bus-range = <0x0 0xff>;
67 fsl,liodn-reg = <&guts 0x500>; /* PEX1LIODNR */
68 pcie@0 {
69 reg = <0 0 0 0 0>;
75 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_catalog.c59 .max_mixer_blendstages = 0xb,
71 .base = 0x0, .len = 0x45C,
72 .features = 0,
73 .highest_bank_bit = 0x2,
76 .reg_off = 0x2AC, .bit_off = 0},
78 .reg_off = 0x2B4, .bit_off = 0},
80 .reg_off = 0x2BC, .bit_off = 0},
82 .reg_off = 0x2C4, .bit_off = 0},
84 .reg_off = 0x2AC, .bit_off = 8},
86 .reg_off = 0x2B4, .bit_off = 8},
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dam33xx-l4.dtsi1 &l4_wkup { /* 0x44c00000 */
3 reg = <0x44c00000 0x800>,
4 <0x44c00800 0x800>,
5 <0x44c01000 0x400>,
6 <0x44c01400 0x400>;
10 ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */
11 <0x00100000 0x44d00000 0x100000>, /* segment 1 */
12 <0x00200000 0x44e00000 0x100000>; /* segment 2 */
14 segment@0 { /* 0x44c00000 */
18 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
[all …]
Dam437x-l4.dtsi1 &l4_wkup { /* 0x44c00000 */
3 reg = <0x44c00000 0x800>,
4 <0x44c00800 0x800>,
5 <0x44c01000 0x400>,
6 <0x44c01400 0x400>;
10 ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */
11 <0x00100000 0x44d00000 0x100000>, /* segment 1 */
12 <0x00200000 0x44e00000 0x100000>; /* segment 2 */
14 segment@0 { /* 0x44c00000 */
18 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
[all …]
Ddra7-l4.dtsi1 &l4_cfg { /* 0x4a000000 */
3 reg = <0x4a000000 0x800>,
4 <0x4a000800 0x800>,
5 <0x4a001000 0x1000>;
9 ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */
10 <0x00100000 0x4a100000 0x100000>, /* segment 1 */
11 <0x00200000 0x4a200000 0x100000>; /* segment 2 */
13 segment@0 { /* 0x4a000000 */
17 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
18 <0x00000800 0x00000800 0x000800>, /* ap 1 */
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/marvell/octeontx2/af/
Drvu_reg.h15 #define RVU_AF_MSIXTR_BASE (0x10)
16 #define RVU_AF_ECO (0x20)
17 #define RVU_AF_BLK_RST (0x30)
18 #define RVU_AF_PF_BAR4_ADDR (0x40)
19 #define RVU_AF_RAS (0x100)
20 #define RVU_AF_RAS_W1S (0x108)
21 #define RVU_AF_RAS_ENA_W1S (0x110)
22 #define RVU_AF_RAS_ENA_W1C (0x118)
23 #define RVU_AF_GEN_INT (0x120)
24 #define RVU_AF_GEN_INT_W1S (0x128)
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/amlogic/
Dmeson-g12-common.dtsi100 reg = <0x0 0x05000000 0x0 0x300000>;
107 size = <0x0 0x10000000>;
108 alignment = <0x0 0x400000>;
125 reg = <0x0 0xfc000000 0x0 0x400000
126 0x0 0xff648000 0x0 0x2000
127 0x0 0xfc400000 0x0 0x200000>;
131 interrupt-map-mask = <0 0 0 0>;
132 interrupt-map = <0 0 0 0 &gic GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
133 bus-range = <0x0 0xff>;
137 ranges = <0x81000000 0 0 0x0 0xfc600000 0 0x00100000
[all …]
/kernel/linux/linux-5.10/drivers/clk/qcom/
Dgcc-qcs404.c42 { P_XO, 0 },
60 { P_XO, 0 },
70 { P_XO, 0 },
84 { P_XO, 0 },
98 { P_XO, 0 },
110 { P_XO, 0 },
124 { P_XO, 0 },
138 { P_XO, 0 },
156 { P_XO, 0 },
168 { P_XO, 0 },
[all …]
Dgcc-msm8916.c46 { P_XO, 0 },
56 { P_XO, 0 },
68 { P_XO, 0 },
82 { P_XO, 0 },
94 { P_XO, 0 },
104 { P_XO, 0 },
118 { P_XO, 0 },
130 { P_XO, 0, },
140 { P_XO, 0 },
152 { P_XO, 0 },
[all …]
Dgcc-msm8939.c54 .l_reg = 0x21004,
55 .m_reg = 0x21008,
56 .n_reg = 0x2100c,
57 .config_reg = 0x21010,
58 .mode_reg = 0x21000,
59 .status_reg = 0x2101c,
72 .enable_reg = 0x45000,
73 .enable_mask = BIT(0),
85 .l_reg = 0x20004,
86 .m_reg = 0x20008,
[all …]
Dgcc-ipq6018.c53 .offset = 0x21000,
56 .enable_reg = 0x0b000,
57 .enable_mask = BIT(0),
83 .offset = 0x21000,
103 { P_XO, 0 },
109 .offset = 0x25000,
113 .enable_reg = 0x0b000,
127 .offset = 0x25000,
141 .offset = 0x37000,
144 .enable_reg = 0x0b000,
[all …]
/kernel/linux/linux-4.19/drivers/clk/qcom/
Dgcc-msm8916.c54 { P_XO, 0 },
64 { P_XO, 0 },
76 { P_XO, 0 },
90 { P_XO, 0 },
102 { P_XO, 0 },
112 { P_XO, 0 },
126 { P_XO, 0 },
138 { P_XO, 0, },
148 { P_XO, 0 },
160 { P_XO, 0 },
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/i915/gvt/
Dhandlers.c44 #define PCH_PP_STATUS _MMIO(0xc7200)
45 #define PCH_PP_CONTROL _MMIO(0xc7204)
46 #define PCH_PP_ON_DELAYS _MMIO(0xc7208)
47 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
48 #define PCH_PP_DIVISOR _MMIO(0xc7210)
61 return 0; in intel_gvt_get_device_type()
103 return 0; in new_mmio_info()
139 return 0; in new_mmio_info()
156 offset &= ~GENMASK(11, 0); in intel_gvt_render_mmio_to_ring_id()
165 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3)
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/i915/
Di915_reg.h105 * #define _FOO_A 0xf000
106 * #define _FOO_B 0xf001
109 * #define FOO_MODE_MASK (0xf << 16)
111 * #define FOO_MODE_BAR (0 << 16)
115 * #define BAR _MMIO(0xb000)
116 * #define GEN8_BAR _MMIO(0xb888)
125 #define INVALID_MMIO_REG _MMIO(0)
144 * numbers, pick the 0-based __index'th value.
151 * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
178 BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/
Di915_reg.h106 * #define _FOO_A 0xf000
107 * #define _FOO_B 0xf001
111 * #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0)
115 * #define BAR _MMIO(0xb000)
116 * #define GEN8_BAR _MMIO(0xb888)
121 * @__n: 0-based bit number
130 ((__n) < 0 || (__n) > 31))))
134 * @__high: 0-based high bit
135 * @__low: 0-based low bit
145 ((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
[all …]