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3 The UniPhier System Bus is an external bus that connects on-board devices to4 the UniPhier SoC. It is a simple (semi-)parallel bus with address, data, and9 within each bank to the CPU-viewed address. The needed setup includes the base14 - compatible: should be "socionext,uniphier-system-bus".15 - reg: offset and length of the register set for the bus controller device.16 - #address-cells: should be 2. The first cell is the bank number (chip select).18 - #size-cells: should be 1.19 - ranges: should provide a proper address translation from the System Bus to24 defined. Some SoCs can use 0x00000000-0x0fffffff and 0x40000000-0x4fffffff,25 while other SoCs can only use 0x40000000-0x4fffffff. There might be additional[all …]
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause3 ---4 $id: http://devicetree.org/schemas/bus/socionext,uniphier-system-bus.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 The UniPhier System Bus is an external bus that connects on-board devices to11 the UniPhier SoC. It is a simple (semi-)parallel bus with address, data, and16 within each bank to the CPU-viewed address. The needed setup includes the21 - Masahiro Yamada <yamada.masahiro@socionext.com>25 const: socionext,uniphier-system-bus30 "#address-cells":[all …]