Searched +full:0 +full:x68000000 (Results 1 – 25 of 71) sorted by relevance
123
| /kernel/linux/linux-5.10/arch/arm/mach-imx/ |
| D | hardware.h | 21 (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0)
35 * whole address space to [0xf4000000, 0xf5ffffff]. So [0xf6000000,0xfeffffff]
41 * IO 0x00200000+0x100000 -> 0xf4000000+0x100000
43 * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000
44 * SAHB1 0x80000000+0x100000 -> 0xf5000000+0x100000
45 * X_MEMC 0xdf000000+0x004000 -> 0xf5f00000+0x004000
47 * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
48 * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
49 * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
51 * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000
[all …]
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| D | mx35.h | 5 #define MX35_AIPS1_BASE_ADDR 0x43f00000
7 #define MX35_SPBA0_BASE_ADDR 0x50000000
9 #define MX35_AIPS2_BASE_ADDR 0x53f00000
11 #define MX35_AVIC_BASE_ADDR 0x68000000
13 #define MX35_X_MEMC_BASE_ADDR 0xb8000000
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| D | mx31.h | 5 #define MX31_AIPS1_BASE_ADDR 0x43f00000
7 #define MX31_SPBA0_BASE_ADDR 0x50000000
9 #define MX31_AIPS2_BASE_ADDR 0x53f00000
11 #define MX31_AVIC_BASE_ADDR 0x68000000
13 #define MX31_X_MEMC_BASE_ADDR 0xb8000000
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| D | mx3x.h | 36 #define MX3x_L2CC_BASE_ADDR 0x30000000
42 #define MX3x_AIPS1_BASE_ADDR 0x43f00000
44 #define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000)
45 #define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000)
46 #define MX3x_CLKCTL_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x0c000)
47 #define MX3x_ETB_SLOT4_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x10000)
48 #define MX3x_ETB_SLOT5_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x14000)
49 #define MX3x_ECT_CTIO_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x18000)
50 #define MX3x_I2C_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x80000)
51 #define MX3x_I2C3_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x84000)
[all …]
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| /kernel/linux/linux-4.19/arch/arm/mach-imx/ |
| D | hardware.h | 34 (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0)
48 * whole address space to [0xf4000000, 0xf5ffffff]. So [0xf6000000,0xfeffffff]
54 * IO 0x00200000+0x100000 -> 0xf4000000+0x100000
56 * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000
57 * SAHB1 0x80000000+0x100000 -> 0xf5000000+0x100000
58 * X_MEMC 0xdf000000+0x004000 -> 0xf5f00000+0x004000
60 * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
61 * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
62 * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
64 * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000
[all …]
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| D | mx35.h | 8 #define MX35_IRAM_BASE_ADDR 0x10000000 /* internal ram */
11 #define MX35_L2CC_BASE_ADDR 0x30000000
14 #define MX35_AIPS1_BASE_ADDR 0x43f00000
16 #define MX35_MAX_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x04000)
17 #define MX35_EVTMON_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x08000)
18 #define MX35_CLKCTL_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x0c000)
19 #define MX35_ETB_SLOT4_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x10000)
20 #define MX35_ETB_SLOT5_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x14000)
21 #define MX35_ECT_CTIO_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x18000)
22 #define MX35_I2C1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x80000)
[all …]
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| D | mx3x.h | 40 #define MX3x_L2CC_BASE_ADDR 0x30000000
46 #define MX3x_AIPS1_BASE_ADDR 0x43f00000
48 #define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000)
49 #define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000)
50 #define MX3x_CLKCTL_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x0c000)
51 #define MX3x_ETB_SLOT4_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x10000)
52 #define MX3x_ETB_SLOT5_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x14000)
53 #define MX3x_ECT_CTIO_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x18000)
54 #define MX3x_I2C_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x80000)
55 #define MX3x_I2C3_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x84000)
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/usb/ |
| D | faraday,fotg210.txt | 29 reg = <0x68000000 0x1000>;
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| D | octeon-usb.txt | 49 reg = <0x11800 0x68000000 0x0 0x1000>;
58 reg = <0x16f00 0x10000000 0x0 0x80000>;
59 interrupts = <0 56>;
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| /kernel/linux/linux-5.10/arch/arm/mach-omap2/ |
| D | omap34xx.h | 17 #define L4_34XX_BASE 0x48000000
18 #define L4_WK_34XX_BASE 0x48300000
19 #define L4_PER_34XX_BASE 0x49000000
20 #define L4_EMU_34XX_BASE 0x54000000
21 #define L3_34XX_BASE 0x68000000
23 #define L4_WK_AM33XX_BASE 0x44C00000
25 #define OMAP3430_32KSYNCT_BASE 0x48320000
26 #define OMAP3430_CM_BASE 0x48004800
27 #define OMAP3430_PRM_BASE 0x48306800
28 #define OMAP343X_SMS_BASE 0x6C000000
[all …]
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| D | omap24xx.h | 19 #define L4_24XX_BASE 0x48000000
20 #define L4_WK_243X_BASE 0x49000000
21 #define L3_24XX_BASE 0x68000000
24 #define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000)
25 #define OMAP24XX_IVA_INTC_BASE 0x40000000
28 #define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000)
29 #define OMAP2420_PRCM_BASE (L4_24XX_BASE + 0x8000)
30 #define OMAP2420_CM_BASE (L4_24XX_BASE + 0x8000)
32 #define OMAP2420_SDRC_BASE (L3_24XX_BASE + 0x9000)
33 #define OMAP2420_SMS_BASE 0x68008000
[all …]
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| D | iomap.h | 33 #define OMAP2_L3_IO_OFFSET 0x90000000
36 #define OMAP2_L4_IO_OFFSET 0xb2000000
39 #define OMAP4_L3_IO_OFFSET 0xb4000000
42 #define AM33XX_L4_WK_IO_OFFSET 0xb5000000
45 #define OMAP4_L3_PER_IO_OFFSET 0xb1100000
48 #define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */
58 #define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/
61 #define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */
65 #define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */
70 /* 0x6e000000 --> 0xfe000000 */
[all …]
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| /kernel/linux/linux-4.19/arch/arm/boot/dts/ |
| D | bcm53340-ubnt-unifi-switch8.dts | 22 memory@0 {
23 reg = <0x00000000 0x08000000>,
24 <0x68000000 0x08000000>;
34 bspi-sel = <0>;
36 flash: m25p80@0 {
38 reg = <0>;
45 partition@0 {
47 reg = <0x0 0xc0000>;
52 reg = <0xc0000 0x10000>;
57 reg = <0xd0000 0x10000>;
[all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | bcm53340-ubnt-unifi-switch8.dts | 22 memory@0 {
24 reg = <0x00000000 0x08000000>,
25 <0x68000000 0x08000000>;
35 bspi-sel = <0>;
37 flash: m25p80@0 {
39 reg = <0>;
46 partition@0 {
48 reg = <0x0 0xc0000>;
53 reg = <0xc0000 0x10000>;
58 reg = <0xd0000 0x10000>;
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/usb/ |
| D | octeon-usb.txt | 49 reg = <0x11800 0x68000000 0x0 0x1000>;
58 reg = <0x16f00 0x10000000 0x0 0x80000>;
59 interrupts = <0 56>;
|
| /kernel/linux/linux-4.19/arch/arm/mach-omap2/ |
| D | omap34xx.h | 30 #define L4_34XX_BASE 0x48000000
31 #define L4_WK_34XX_BASE 0x48300000
32 #define L4_PER_34XX_BASE 0x49000000
33 #define L4_EMU_34XX_BASE 0x54000000
34 #define L3_34XX_BASE 0x68000000
36 #define L4_WK_AM33XX_BASE 0x44C00000
38 #define OMAP3430_32KSYNCT_BASE 0x48320000
39 #define OMAP3430_CM_BASE 0x48004800
40 #define OMAP3430_PRM_BASE 0x48306800
41 #define OMAP343X_SMS_BASE 0x6C000000
[all …]
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| D | omap24xx.h | 33 #define L4_24XX_BASE 0x48000000
34 #define L4_WK_243X_BASE 0x49000000
35 #define L3_24XX_BASE 0x68000000
38 #define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000)
39 #define OMAP24XX_IVA_INTC_BASE 0x40000000
42 #define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000)
43 #define OMAP2420_PRCM_BASE (L4_24XX_BASE + 0x8000)
44 #define OMAP2420_CM_BASE (L4_24XX_BASE + 0x8000)
46 #define OMAP2420_SDRC_BASE (L3_24XX_BASE + 0x9000)
47 #define OMAP2420_SMS_BASE 0x68008000
[all …]
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| D | iomap.h | 33 #define OMAP2_L3_IO_OFFSET 0x90000000
36 #define OMAP2_L4_IO_OFFSET 0xb2000000
39 #define OMAP4_L3_IO_OFFSET 0xb4000000
42 #define AM33XX_L4_WK_IO_OFFSET 0xb5000000
45 #define OMAP4_L3_PER_IO_OFFSET 0xb1100000
48 #define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */
58 #define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/
61 #define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */
65 #define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */
70 /* 0x6e000000 --> 0xfe000000 */
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/mtd/ |
| D | davinci-nand.txt | 23 Can be in the range [0-3].
31 If not set equal to 0x08.
37 If not set equal to 0x10.
80 reg = <0x62000000 0x807ff
81 0x68000000 0x8000>;
83 ti,davinci-mask-ale = <0>;
84 ti,davinci-mask-cle = <0>;
85 ti,davinci-mask-chipsel = <0>;
92 reg = <0x180000 0x7e80000>;
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mtd/ |
| D | davinci-nand.txt | 23 Can be in the range [0-3].
31 If not set equal to 0x08.
37 If not set equal to 0x10.
80 reg = <0x62000000 0x807ff
81 0x68000000 0x8000>;
83 ti,davinci-mask-ale = <0>;
84 ti,davinci-mask-cle = <0>;
85 ti,davinci-mask-chipsel = <0>;
92 reg = <0x180000 0x7e80000>;
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| /kernel/linux/linux-5.10/arch/powerpc/boot/dts/ |
| D | a4m072.dts | 27 ranges = <0 0xf0000000 0x0000c000>;
28 reg = <0xf0000000 0x00000100>;
29 bus-frequency = <0>; /* From boot loader */
30 system-frequency = <0>; /* From boot loader */
33 fsl,init-ext-48mhz-en = <0x0>;
34 fsl,init-fd-enable = <0x01>;
35 fsl,init-fd-counters = <0x3333>;
44 reg = <0x2000 0x100>;
45 interrupts = <2 1 0>;
50 reg = <0x2200 0x100>;
[all …]
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| /kernel/linux/linux-4.19/arch/powerpc/boot/dts/ |
| D | a4m072.dts | 31 ranges = <0 0xf0000000 0x0000c000>;
32 reg = <0xf0000000 0x00000100>;
33 bus-frequency = <0>; /* From boot loader */
34 system-frequency = <0>; /* From boot loader */
37 fsl,init-ext-48mhz-en = <0x0>;
38 fsl,init-fd-enable = <0x01>;
39 fsl,init-fd-counters = <0x3333>;
48 reg = <0x2000 0x100>;
49 interrupts = <2 1 0>;
54 reg = <0x2200 0x100>;
[all …]
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| /kernel/linux/linux-4.19/arch/arm/mach-davinci/include/mach/ |
| D | da8xx.h | 52 #define DA8XX_CP_INTC_BASE 0xfffee000
56 #define DA8XX_SYSCFG0_BASE (IO_PHYS + 0x14000)
58 #define DA8XX_JTAG_ID_REG 0x18
59 #define DA8XX_HOST1CFG_REG 0x44
60 #define DA8XX_CHIPSIG_REG 0x174
61 #define DA8XX_CFGCHIP0_REG 0x17c
62 #define DA8XX_CFGCHIP1_REG 0x180
63 #define DA8XX_CFGCHIP2_REG 0x184
64 #define DA8XX_CFGCHIP3_REG 0x188
65 #define DA8XX_CFGCHIP4_REG 0x18c
[all …]
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| /kernel/linux/linux-5.10/arch/arm/mach-davinci/include/mach/ |
| D | da8xx.h | 52 #define DA8XX_CP_INTC_BASE 0xfffee000
56 #define DA8XX_SYSCFG0_BASE (IO_PHYS + 0x14000)
58 #define DA8XX_JTAG_ID_REG 0x18
59 #define DA8XX_HOST1CFG_REG 0x44
60 #define DA8XX_CHIPSIG_REG 0x174
61 #define DA8XX_CFGCHIP0_REG 0x17c
62 #define DA8XX_CFGCHIP1_REG 0x180
63 #define DA8XX_CFGCHIP2_REG 0x184
64 #define DA8XX_CFGCHIP3_REG 0x188
65 #define DA8XX_CFGCHIP4_REG 0x18c
[all …]
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/realtek/ |
| D | rtd139x.dtsi | 8 /memreserve/ 0x0000000000000000 0x000000000002f000;
9 /memreserve/ 0x000000000002f000 0x00000000000d1000;
25 reg = <0x2f000 0x1000>;
29 reg = <0x1ffe000 0x4000>;
33 reg = <0x10100000 0xf00000>;
46 #clock-cells = <0>;
54 ranges = <0x00000000 0x00000000 0x0001f000>, /* boot ROM */
55 <0x98000000 0x98000000 0x68000000>;
59 reg = <0x98000000 0x200000>;
62 ranges = <0x0 0x98000000 0x200000>;
[all …]
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