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/kernel/linux/linux-4.19/arch/sh/include/cpu-sh4a/cpu/
Ddma.h9 #define DMTE0_IRQ evt2irq(0x800)
10 #define DMTE4_IRQ evt2irq(0xb80)
11 #define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
12 #define SH_DMAC_BASE0 0xFE008020
14 #define DMTE0_IRQ evt2irq(0x800)
15 #define DMTE4_IRQ evt2irq(0xb80)
16 #define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
17 #define SH_DMAC_BASE0 0xFE008020
19 #define DMTE0_IRQ evt2irq(0x640)
20 #define DMTE4_IRQ evt2irq(0x780)
[all …]
/kernel/linux/linux-5.10/arch/sh/include/cpu-sh4a/cpu/
Ddma.h9 #define DMTE0_IRQ evt2irq(0x800)
10 #define DMTE4_IRQ evt2irq(0xb80)
11 #define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
12 #define SH_DMAC_BASE0 0xFE008020
14 #define DMTE0_IRQ evt2irq(0x800)
15 #define DMTE4_IRQ evt2irq(0xb80)
16 #define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
17 #define SH_DMAC_BASE0 0xFE008020
19 #define DMTE0_IRQ evt2irq(0x640)
20 #define DMTE4_IRQ evt2irq(0x780)
[all …]
/kernel/linux/linux-5.10/arch/sh/kernel/cpu/sh4/
Dsetup-sh4-202.c23 DEFINE_RES_MEM(0xffe80000, 0x100),
24 DEFINE_RES_IRQ(evt2irq(0x700)),
25 DEFINE_RES_IRQ(evt2irq(0x720)),
26 DEFINE_RES_IRQ(evt2irq(0x760)),
27 DEFINE_RES_IRQ(evt2irq(0x740)),
32 .id = 0,
45 DEFINE_RES_MEM(0xffd80000, 0x30),
46 DEFINE_RES_IRQ(evt2irq(0x400)),
47 DEFINE_RES_IRQ(evt2irq(0x420)),
48 DEFINE_RES_IRQ(evt2irq(0x440)),
[all …]
Dsetup-sh7750.c19 [0] = {
20 .start = 0xffc80000,
21 .end = 0xffc80000 + 0x58 - 1,
26 .start = evt2irq(0x480),
43 DEFINE_RES_MEM(0xffe00000, 0x20),
44 DEFINE_RES_IRQ(evt2irq(0x4e0)),
49 .id = 0,
63 DEFINE_RES_MEM(0xffe80000, 0x100),
64 DEFINE_RES_IRQ(evt2irq(0x700)),
82 DEFINE_RES_MEM(0xffd80000, 0x30),
[all …]
/kernel/linux/linux-4.19/arch/sh/kernel/cpu/sh4/
Dsetup-sh4-202.c25 DEFINE_RES_MEM(0xffe80000, 0x100),
26 DEFINE_RES_IRQ(evt2irq(0x700)),
27 DEFINE_RES_IRQ(evt2irq(0x720)),
28 DEFINE_RES_IRQ(evt2irq(0x760)),
29 DEFINE_RES_IRQ(evt2irq(0x740)),
34 .id = 0,
47 DEFINE_RES_MEM(0xffd80000, 0x30),
48 DEFINE_RES_IRQ(evt2irq(0x400)),
49 DEFINE_RES_IRQ(evt2irq(0x420)),
50 DEFINE_RES_IRQ(evt2irq(0x440)),
[all …]
Dsetup-sh7750.c21 [0] = {
22 .start = 0xffc80000,
23 .end = 0xffc80000 + 0x58 - 1,
28 .start = evt2irq(0x480),
45 DEFINE_RES_MEM(0xffe00000, 0x20),
46 DEFINE_RES_IRQ(evt2irq(0x4e0)),
51 .id = 0,
65 DEFINE_RES_MEM(0xffe80000, 0x100),
66 DEFINE_RES_IRQ(evt2irq(0x700)),
84 DEFINE_RES_MEM(0xffd80000, 0x30),
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/sound/
Damlogic,g12a-toacodec.yaml48 reg = <0x740 0x4>;
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/rtc/
Drtc-meson.txt27 reg = <0x740 0x14>;
/kernel/linux/linux-5.10/include/linux/usb/
Dusb338x.h30 #define SCRATCH 0x0b
47 #define USB3380_EP_CFG_MASK_IN ((0x3 << IN_ENDPOINT_TYPE) | \
49 #define USB3380_EP_CFG_MASK_OUT ((0x3 << OUT_ENDPOINT_TYPE) | \
56 #define DEVICE_CLASS 0
59 #define U1_SYSTEM_EXIT_LATENCY 0
62 #define U1_DEVICE_EXIT_LATENCY 0
66 #define USB_L1_LPM_SUPPORT 0
69 #define BEST_EFFORT_LATENCY_TOLERANCE 0
77 #define SERIAL_NUMBER_STRING_ENABLE 0
90 #define GPEP0_TIMEOUT_ENABLE 0
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/usb/
Dqcom,dwc3.yaml106 "^dwc3@[0-9a-f]+$":
137 reg = <0 0x0a6f8800 0 0x400>;
167 reg = <0 0x0a600000 0 0xcd00>;
169 iommus = <&apps_smmu 0x740 0>;
/kernel/linux/linux-5.10/arch/sh/kernel/cpu/sh4a/
Dsetup-shx3.c20 * This intentionally only registers SCIF ports 0, 1, and 3. SCIF 2
34 DEFINE_RES_MEM(0xffc30000, 0x100),
35 DEFINE_RES_IRQ(evt2irq(0x700)),
36 DEFINE_RES_IRQ(evt2irq(0x720)),
37 DEFINE_RES_IRQ(evt2irq(0x760)),
38 DEFINE_RES_IRQ(evt2irq(0x740)),
43 .id = 0,
57 DEFINE_RES_MEM(0xffc40000, 0x100),
58 DEFINE_RES_IRQ(evt2irq(0x780)),
59 DEFINE_RES_IRQ(evt2irq(0x7a0)),
[all …]
Dsetup-sh7786.c35 DEFINE_RES_MEM(0xffea0000, 0x100),
36 DEFINE_RES_IRQ(evt2irq(0x700)),
37 DEFINE_RES_IRQ(evt2irq(0x720)),
38 DEFINE_RES_IRQ(evt2irq(0x760)),
39 DEFINE_RES_IRQ(evt2irq(0x740)),
44 .id = 0,
62 DEFINE_RES_MEM(0xffeb0000, 0x100),
63 DEFINE_RES_IRQ(evt2irq(0x780)),
67 DEFINE_RES_MEM(0xffeb0000, 0x100),
69 DEFINE_RES_IRQ(0),
[all …]
/kernel/linux/linux-4.19/arch/sh/kernel/cpu/sh4a/
Dsetup-shx3.c22 * This intentionally only registers SCIF ports 0, 1, and 3. SCIF 2
36 DEFINE_RES_MEM(0xffc30000, 0x100),
37 DEFINE_RES_IRQ(evt2irq(0x700)),
38 DEFINE_RES_IRQ(evt2irq(0x720)),
39 DEFINE_RES_IRQ(evt2irq(0x760)),
40 DEFINE_RES_IRQ(evt2irq(0x740)),
45 .id = 0,
59 DEFINE_RES_MEM(0xffc40000, 0x100),
60 DEFINE_RES_IRQ(evt2irq(0x780)),
61 DEFINE_RES_IRQ(evt2irq(0x7a0)),
[all …]
Dsetup-sh7786.c37 DEFINE_RES_MEM(0xffea0000, 0x100),
38 DEFINE_RES_IRQ(evt2irq(0x700)),
39 DEFINE_RES_IRQ(evt2irq(0x720)),
40 DEFINE_RES_IRQ(evt2irq(0x760)),
41 DEFINE_RES_IRQ(evt2irq(0x740)),
46 .id = 0,
64 DEFINE_RES_MEM(0xffeb0000, 0x100),
65 DEFINE_RES_IRQ(evt2irq(0x780)),
69 DEFINE_RES_MEM(0xffeb0000, 0x100),
71 DEFINE_RES_IRQ(0),
[all …]
/kernel/linux/linux-5.10/arch/arm/include/asm/hardware/
Dcache-l2x0.h13 #define L2X0_CACHE_ID 0x000
14 #define L2X0_CACHE_TYPE 0x004
15 #define L2X0_CTRL 0x100
16 #define L2X0_AUX_CTRL 0x104
17 #define L310_TAG_LATENCY_CTRL 0x108
18 #define L310_DATA_LATENCY_CTRL 0x10C
19 #define L2X0_EVENT_CNT_CTRL 0x200
20 #define L2X0_EVENT_CNT1_CFG 0x204
21 #define L2X0_EVENT_CNT0_CFG 0x208
22 #define L2X0_EVENT_CNT1_VAL 0x20C
[all …]
/kernel/linux/linux-4.19/arch/arm/include/asm/hardware/
Dcache-l2x0.h25 #define L2X0_CACHE_ID 0x000
26 #define L2X0_CACHE_TYPE 0x004
27 #define L2X0_CTRL 0x100
28 #define L2X0_AUX_CTRL 0x104
29 #define L310_TAG_LATENCY_CTRL 0x108
30 #define L310_DATA_LATENCY_CTRL 0x10C
31 #define L2X0_EVENT_CNT_CTRL 0x200
32 #define L2X0_EVENT_CNT1_CFG 0x204
33 #define L2X0_EVENT_CNT0_CFG 0x208
34 #define L2X0_EVENT_CNT1_VAL 0x20C
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/apple/
Dbmac.h17 #define XIFC 0x000 /* low-level interface control */
18 # define TxOutputEnable 0x0001 /* output driver enable */
19 # define XIFLoopback 0x0002 /* Loopback-mode XIF enable */
20 # define MIILoopback 0x0004 /* Loopback-mode MII enable */
21 # define MIILoopbackBits 0x0006
22 # define MIIBuffDisable 0x0008 /* MII receive buffer disable */
23 # define SQETestEnable 0x0010 /* SQE test enable */
24 # define SQETimeWindow 0x03e0 /* SQE time window */
25 # define XIFLanceMode 0x0010 /* Lance mode enable */
26 # define XIFLanceIPG0 0x03e0 /* Lance mode IPG0 */
[all …]
/kernel/linux/linux-4.19/drivers/net/ethernet/apple/
Dbmac.h21 #define XIFC 0x000 /* low-level interface control */
22 # define TxOutputEnable 0x0001 /* output driver enable */
23 # define XIFLoopback 0x0002 /* Loopback-mode XIF enable */
24 # define MIILoopback 0x0004 /* Loopback-mode MII enable */
25 # define MIILoopbackBits 0x0006
26 # define MIIBuffDisable 0x0008 /* MII receive buffer disable */
27 # define SQETestEnable 0x0010 /* SQE test enable */
28 # define SQETimeWindow 0x03e0 /* SQE time window */
29 # define XIFLanceMode 0x0010 /* Lance mode enable */
30 # define XIFLanceIPG0 0x03e0 /* Lance mode IPG0 */
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dmeson.dtsi22 reg = <0xc1100000 0x200000>;
25 ranges = <0x0 0xc1100000 0x200000>;
31 reg = <0x4000 0x400>;
36 reg = <0x7c00 0x200>;
41 reg = <0x8100 0x8>;
46 reg = <0x84c0 0x18>;
53 reg = <0x84dc 0x18>;
60 reg = <0x8500 0x20>;
63 #size-cells = <0>;
69 reg = <0x8550 0x10>;
[all …]
Dimx6q-pinfunc.h13 #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0
15 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0
16 #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0
17 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0
18 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0
20 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0
21 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0
22 #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0
[all …]
/kernel/linux/linux-4.19/drivers/mtd/nand/raw/
Ddenali.h24 #define DEVICE_RESET 0x0
27 #define TRANSFER_SPARE_REG 0x10
28 #define TRANSFER_SPARE_REG__FLAG BIT(0)
30 #define LOAD_WAIT_CNT 0x20
31 #define LOAD_WAIT_CNT__VALUE GENMASK(15, 0)
33 #define PROGRAM_WAIT_CNT 0x30
34 #define PROGRAM_WAIT_CNT__VALUE GENMASK(15, 0)
36 #define ERASE_WAIT_CNT 0x40
37 #define ERASE_WAIT_CNT__VALUE GENMASK(15, 0)
39 #define INT_MON_CYCCNT 0x50
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
Drv6xxd.h27 #define SPLL_CNTL_MODE 0x60c
30 #define GENERAL_PWRMGT 0x618
31 # define GLOBAL_PWRMGT_EN (1 << 0)
47 #define MCLK_PWRMGT_CNTL 0x624
48 # define MPLL_PWRMGT_OFF (1 << 0)
78 #define MPLL_FREQ_LEVEL_0 0x6e8
79 # define LEVEL0_MPLL_POST_DIV(x) ((x) << 0)
80 # define LEVEL0_MPLL_POST_DIV_MASK (0xff << 0)
82 # define LEVEL0_MPLL_FB_DIV_MASK (0xfff << 8)
84 # define LEVEL0_MPLL_REF_DIV_MASK (0x3f << 20)
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/radeon/
Drv6xxd.h27 #define SPLL_CNTL_MODE 0x60c
30 #define GENERAL_PWRMGT 0x618
31 # define GLOBAL_PWRMGT_EN (1 << 0)
47 #define MCLK_PWRMGT_CNTL 0x624
48 # define MPLL_PWRMGT_OFF (1 << 0)
78 #define MPLL_FREQ_LEVEL_0 0x6e8
79 # define LEVEL0_MPLL_POST_DIV(x) ((x) << 0)
80 # define LEVEL0_MPLL_POST_DIV_MASK (0xff << 0)
82 # define LEVEL0_MPLL_FB_DIV_MASK (0xfff << 8)
84 # define LEVEL0_MPLL_REF_DIV_MASK (0x3f << 20)
[all …]
/kernel/linux/linux-4.19/arch/arm/boot/dts/
Dimx6q-pinfunc.h17 #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0
18 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0
19 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0
20 #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0
21 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0
22 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0
23 #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0
24 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0
25 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0
26 #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0
[all …]
/kernel/linux/linux-5.10/drivers/mtd/nand/raw/
Ddenali.h17 #define DEVICE_RESET 0x0
20 #define TRANSFER_SPARE_REG 0x10
21 #define TRANSFER_SPARE_REG__FLAG BIT(0)
23 #define LOAD_WAIT_CNT 0x20
24 #define LOAD_WAIT_CNT__VALUE GENMASK(15, 0)
26 #define PROGRAM_WAIT_CNT 0x30
27 #define PROGRAM_WAIT_CNT__VALUE GENMASK(15, 0)
29 #define ERASE_WAIT_CNT 0x40
30 #define ERASE_WAIT_CNT__VALUE GENMASK(15, 0)
32 #define INT_MON_CYCCNT 0x50
[all …]

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