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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/smu/
Dsmu_7_1_3_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define GCK_MCLK_FUSES__StartupMClkDid_MASK 0x7f
32 #define GCK_MCLK_FUSES__StartupMClkDid__SHIFT 0x0
33 #define GCK_MCLK_FUSES__MClkADCA_MASK 0x780
34 #define GCK_MCLK_FUSES__MClkADCA__SHIFT 0x7
35 #define GCK_MCLK_FUSES__MClkDDCA_MASK 0x1800
36 #define GCK_MCLK_FUSES__MClkDDCA__SHIFT 0xb
[all …]
Dsmu_7_1_0_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
Dsmu_7_1_2_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
Dsmu_7_1_1_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/amd/include/asic_reg/smu/
Dsmu_7_1_3_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define GCK_MCLK_FUSES__StartupMClkDid_MASK 0x7f
32 #define GCK_MCLK_FUSES__StartupMClkDid__SHIFT 0x0
33 #define GCK_MCLK_FUSES__MClkADCA_MASK 0x780
34 #define GCK_MCLK_FUSES__MClkADCA__SHIFT 0x7
35 #define GCK_MCLK_FUSES__MClkDDCA_MASK 0x1800
36 #define GCK_MCLK_FUSES__MClkDDCA__SHIFT 0xb
[all …]
Dsmu_7_1_0_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
Dsmu_7_1_2_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
/kernel/linux/linux-5.10/drivers/mtd/nand/raw/
Dpasemi_nand.c26 #define LBICTRL_LPCCTL_NR 0x00004000
37 while (len > 0x800) { in pasemi_read_buf()
38 memcpy_fromio(buf, chip->legacy.IO_ADDR_R, 0x800); in pasemi_read_buf()
39 buf += 0x800; in pasemi_read_buf()
40 len -= 0x800; in pasemi_read_buf()
48 while (len > 0x800) { in pasemi_write_buf()
49 memcpy_toio(chip->legacy.IO_ADDR_R, buf, 0x800); in pasemi_write_buf()
50 buf += 0x800; in pasemi_write_buf()
51 len -= 0x800; in pasemi_write_buf()
84 return 0; in pasemi_attach_chip()
[all …]
Dcs553x_nand.c11 * mtd-id for command line partitioning is cs553x_nand_cs[0-3]
12 * where 0-3 reflects the chip select for NAND.
30 #define MSR_DIVIL_GLD_CAP 0x51400000 /* DIVIL capabilitiies */
31 #define CAP_CS5535 0x2df000ULL
32 #define CAP_CS5536 0x5df500ULL
35 #define MSR_NANDF_DATA 0x5140001b /* NAND Flash Data Timing MSR */
36 #define MSR_NANDF_CTL 0x5140001c /* NAND Flash Control Timing */
37 #define MSR_NANDF_RSVD 0x5140001d /* Reserved */
40 #define MSR_DIVIL_LBAR_FLSH0 0x51400010 /* Flash Chip Select 0 */
41 #define MSR_DIVIL_LBAR_FLSH1 0x51400011 /* Flash Chip Select 1 */
[all …]
/kernel/linux/linux-4.19/drivers/mtd/nand/raw/
Dpasemi_nand.c38 #define LBICTRL_LPCCTL_NR 0x00004000
50 while (len > 0x800) { in pasemi_read_buf()
51 memcpy_fromio(buf, chip->IO_ADDR_R, 0x800); in pasemi_read_buf()
52 buf += 0x800; in pasemi_read_buf()
53 len -= 0x800; in pasemi_read_buf()
62 while (len > 0x800) { in pasemi_write_buf()
63 memcpy_toio(chip->IO_ADDR_R, buf, 0x800); in pasemi_write_buf()
64 buf += 0x800; in pasemi_write_buf()
65 len -= 0x800; in pasemi_write_buf()
100 int err = 0; in pasemi_nand_probe()
[all …]
Dcs553x_nand.c14 * mtd-id for command line partitioning is cs553x_nand_cs[0-3]
15 * where 0-3 reflects the chip select for NAND.
34 #define MSR_DIVIL_GLD_CAP 0x51400000 /* DIVIL capabilitiies */
35 #define CAP_CS5535 0x2df000ULL
36 #define CAP_CS5536 0x5df500ULL
39 #define MSR_NANDF_DATA 0x5140001b /* NAND Flash Data Timing MSR */
40 #define MSR_NANDF_CTL 0x5140001c /* NAND Flash Control Timing */
41 #define MSR_NANDF_RSVD 0x5140001d /* Reserved */
44 #define MSR_DIVIL_LBAR_FLSH0 0x51400010 /* Flash Chip Select 0 */
45 #define MSR_DIVIL_LBAR_FLSH1 0x51400011 /* Flash Chip Select 1 */
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/media/
Dmediatek-vcodec.txt29 reg = <0 0x16000000 0 0x100>, /*VDEC_SYS*/
30 <0 0x16020000 0 0x1000>, /*VDEC_MISC*/
31 <0 0x16021000 0 0x800>, /*VDEC_LD*/
32 <0 0x16021800 0 0x800>, /*VDEC_TOP*/
33 <0 0x16022000 0 0x1000>, /*VDEC_CM*/
34 <0 0x16023000 0 0x1000>, /*VDEC_AD*/
35 <0 0x16024000 0 0x1000>, /*VDEC_AV*/
36 <0 0x16025000 0 0x1000>, /*VDEC_PP*/
37 <0 0x16026800 0 0x800>, /*VP8_VD*/
38 <0 0x16027000 0 0x800>, /*VP6_VD*/
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/nouveau/nvkm/engine/disp/
Dgf119.c45 mask[head->id] = nvkm_rd32(device, 0x6101d4 + (head->id * 0x800)); in gf119_disp_super()
49 if (disp->super & 0x00000001) { in gf119_disp_super()
50 nv50_disp_chan_mthd(disp->chan[0], NV_DBG_DEBUG); in gf119_disp_super()
53 if (!(mask[head->id] & 0x00001000)) in gf119_disp_super()
58 if (disp->super & 0x00000002) { in gf119_disp_super()
60 if (!(mask[head->id] & 0x00001000)) in gf119_disp_super()
66 if (!(mask[head->id] & 0x00010000)) in gf119_disp_super()
71 if (!(mask[head->id] & 0x00001000)) in gf119_disp_super()
76 if (disp->super & 0x00000004) { in gf119_disp_super()
78 if (!(mask[head->id] & 0x00001000)) in gf119_disp_super()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/disp/
Dgf119.c45 mask[head->id] = nvkm_rd32(device, 0x6101d4 + (head->id * 0x800)); in gf119_disp_super()
49 if (disp->super & 0x00000001) { in gf119_disp_super()
50 nv50_disp_chan_mthd(disp->chan[0], NV_DBG_DEBUG); in gf119_disp_super()
53 if (!(mask[head->id] & 0x00001000)) in gf119_disp_super()
58 if (disp->super & 0x00000002) { in gf119_disp_super()
60 if (!(mask[head->id] & 0x00001000)) in gf119_disp_super()
66 if (!(mask[head->id] & 0x00010000)) in gf119_disp_super()
71 if (!(mask[head->id] & 0x00001000)) in gf119_disp_super()
76 if (disp->super & 0x00000004) { in gf119_disp_super()
78 if (!(mask[head->id] & 0x00001000)) in gf119_disp_super()
[all …]
/kernel/linux/linux-5.10/arch/riscv/kernel/
Dmodule.c24 return 0; in apply_r_riscv_32_rela()
30 return 0; in apply_r_riscv_64_rela()
37 u32 imm12 = (offset & 0x1000) << (31 - 12); in apply_r_riscv_branch_rela()
38 u32 imm11 = (offset & 0x800) >> (11 - 7); in apply_r_riscv_branch_rela()
39 u32 imm10_5 = (offset & 0x7e0) << (30 - 10); in apply_r_riscv_branch_rela()
40 u32 imm4_1 = (offset & 0x1e) << (11 - 4); in apply_r_riscv_branch_rela()
42 *location = (*location & 0x1fff07f) | imm12 | imm11 | imm10_5 | imm4_1; in apply_r_riscv_branch_rela()
43 return 0; in apply_r_riscv_branch_rela()
50 u32 imm20 = (offset & 0x100000) << (31 - 20); in apply_r_riscv_jal_rela()
51 u32 imm19_12 = (offset & 0xff000); in apply_r_riscv_jal_rela()
[all …]
/kernel/linux/linux-4.19/arch/riscv/kernel/
Dmodule.c32 return 0; in apply_r_riscv_32_rela()
38 return 0; in apply_r_riscv_64_rela()
45 u32 imm12 = (offset & 0x1000) << (31 - 12); in apply_r_riscv_branch_rela()
46 u32 imm11 = (offset & 0x800) >> (11 - 7); in apply_r_riscv_branch_rela()
47 u32 imm10_5 = (offset & 0x7e0) << (30 - 10); in apply_r_riscv_branch_rela()
48 u32 imm4_1 = (offset & 0x1e) << (11 - 4); in apply_r_riscv_branch_rela()
50 *location = (*location & 0x1fff07f) | imm12 | imm11 | imm10_5 | imm4_1; in apply_r_riscv_branch_rela()
51 return 0; in apply_r_riscv_branch_rela()
58 u32 imm20 = (offset & 0x100000) << (31 - 20); in apply_r_riscv_jal_rela()
59 u32 imm19_12 = (offset & 0xff000); in apply_r_riscv_jal_rela()
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/nouveau/
Dnouveau_reg.h3 #define NV04_PFB_BOOT_0 0x00100000
4 # define NV04_PFB_BOOT_0_RAM_AMOUNT 0x00000003
5 # define NV04_PFB_BOOT_0_RAM_AMOUNT_32MB 0x00000000
6 # define NV04_PFB_BOOT_0_RAM_AMOUNT_4MB 0x00000001
7 # define NV04_PFB_BOOT_0_RAM_AMOUNT_8MB 0x00000002
8 # define NV04_PFB_BOOT_0_RAM_AMOUNT_16MB 0x00000003
9 # define NV04_PFB_BOOT_0_RAM_WIDTH_128 0x00000004
10 # define NV04_PFB_BOOT_0_RAM_TYPE 0x00000028
11 # define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT 0x00000000
12 # define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT 0x00000008
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/
Dnouveau_reg.h3 #define NV04_PFB_BOOT_0 0x00100000
4 # define NV04_PFB_BOOT_0_RAM_AMOUNT 0x00000003
5 # define NV04_PFB_BOOT_0_RAM_AMOUNT_32MB 0x00000000
6 # define NV04_PFB_BOOT_0_RAM_AMOUNT_4MB 0x00000001
7 # define NV04_PFB_BOOT_0_RAM_AMOUNT_8MB 0x00000002
8 # define NV04_PFB_BOOT_0_RAM_AMOUNT_16MB 0x00000003
9 # define NV04_PFB_BOOT_0_RAM_WIDTH_128 0x00000004
10 # define NV04_PFB_BOOT_0_RAM_TYPE 0x00000028
11 # define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT 0x00000000
12 # define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT 0x00000008
[all …]
/kernel/linux/linux-4.19/arch/sh/include/cpu-sh4a/cpu/
Ddma.h9 #define DMTE0_IRQ evt2irq(0x800)
10 #define DMTE4_IRQ evt2irq(0xb80)
11 #define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
12 #define SH_DMAC_BASE0 0xFE008020
14 #define DMTE0_IRQ evt2irq(0x800)
15 #define DMTE4_IRQ evt2irq(0xb80)
16 #define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
17 #define SH_DMAC_BASE0 0xFE008020
19 #define DMTE0_IRQ evt2irq(0x640)
20 #define DMTE4_IRQ evt2irq(0x780)
[all …]
/kernel/linux/linux-5.10/arch/sh/include/cpu-sh4a/cpu/
Ddma.h9 #define DMTE0_IRQ evt2irq(0x800)
10 #define DMTE4_IRQ evt2irq(0xb80)
11 #define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
12 #define SH_DMAC_BASE0 0xFE008020
14 #define DMTE0_IRQ evt2irq(0x800)
15 #define DMTE4_IRQ evt2irq(0xb80)
16 #define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
17 #define SH_DMAC_BASE0 0xFE008020
19 #define DMTE0_IRQ evt2irq(0x640)
20 #define DMTE4_IRQ evt2irq(0x780)
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/media/
Dmediatek-vcodec.txt32 reg = <0 0x16000000 0 0x100>, /*VDEC_SYS*/
33 <0 0x16020000 0 0x1000>, /*VDEC_MISC*/
34 <0 0x16021000 0 0x800>, /*VDEC_LD*/
35 <0 0x16021800 0 0x800>, /*VDEC_TOP*/
36 <0 0x16022000 0 0x1000>, /*VDEC_CM*/
37 <0 0x16023000 0 0x1000>, /*VDEC_AD*/
38 <0 0x16024000 0 0x1000>, /*VDEC_AV*/
39 <0 0x16025000 0 0x1000>, /*VDEC_PP*/
40 <0 0x16026800 0 0x800>, /*VP8_VD*/
41 <0 0x16027000 0 0x800>, /*VP6_VD*/
[all …]
/kernel/linux/linux-5.10/drivers/staging/rtl8188eu/include/
Dhal8188e_phy_reg.h11 /* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF */
13 /* 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 */
14 /* 3. RF register 0x00-2E */
19 /* 3. Page8(0x800) */
20 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC RF BW Setting */
21 #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */
23 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */
24 #define rFPGA0_XA_HSSIParameter2 0x824
25 #define rFPGA0_XB_HSSIParameter1 0x828
26 #define rFPGA0_XB_HSSIParameter2 0x82c
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/hsi/
Domap-ssi.txt37 0 and 1 (in this order).
55 reg = <0x48058000 0x1000>,
56 <0x48059000 0x1000>;
77 reg = <0x4805a000 0x800>,
78 <0x4805a800 0x800>;
92 reg = <0x4805b000 0x800>,
93 <0x4805b800 0x800>;
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/hsi/
Domap-ssi.txt37 0 and 1 (in this order).
55 reg = <0x48058000 0x1000>,
56 <0x48059000 0x1000>;
77 reg = <0x4805a000 0x800>,
78 <0x4805a800 0x800>;
92 reg = <0x4805b000 0x800>,
93 <0x4805b800 0x800>;
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dsam9x60.dtsi36 #size-cells = <0>;
38 cpu@0 {
41 reg = <0>;
47 reg = <0x20000000 0x10000000>;
53 #clock-cells = <0>;
58 #clock-cells = <0>;
64 reg = <0x00300000 0x100000>;
67 ranges = <0 0x00300000 0x100000>;
78 #size-cells = <0>;
80 reg = <0x00500000 0x100000
[all …]

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