Searched +full:0 +full:xc000000 (Results 1 – 25 of 95) sorted by relevance
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| /kernel/linux/linux-4.19/drivers/staging/rtl8192e/rtl8192e/ |
| D | r8192E_phyreg.h | 19 #define RF_DATA 0x1d4
21 #define rPMAC_Reset 0x100
22 #define rPMAC_TxStart 0x104
23 #define rPMAC_TxLegacySIG 0x108
24 #define rPMAC_TxHTSIG1 0x10c
25 #define rPMAC_TxHTSIG2 0x110
26 #define rPMAC_PHYDebug 0x114
27 #define rPMAC_TxPacketNum 0x118
28 #define rPMAC_TxIdle 0x11c
29 #define rPMAC_TxMACHeader0 0x120
[all …]
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| /kernel/linux/linux-5.10/drivers/staging/rtl8192e/rtl8192e/ |
| D | r8192E_phyreg.h | 11 #define RF_DATA 0x1d4
13 #define rPMAC_Reset 0x100
14 #define rPMAC_TxStart 0x104
15 #define rPMAC_TxLegacySIG 0x108
16 #define rPMAC_TxHTSIG1 0x10c
17 #define rPMAC_TxHTSIG2 0x110
18 #define rPMAC_PHYDebug 0x114
19 #define rPMAC_TxPacketNum 0x118
20 #define rPMAC_TxIdle 0x11c
21 #define rPMAC_TxMACHeader0 0x120
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/interrupt-controller/ |
| D | sifive,plic-1.0.0.txt | 26 "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
31 - compatible : "sifive,plic-1.0.0" and a string identifying the actual
33 - #address-cells : should be <0> or more.
46 #address-cells = <0>;
48 compatible = "sifive,plic-1.0.0", "sifive,fu540-c000-plic";
56 reg = <0xc000000 0x4000000>;
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | sifive,plic-1.0.0.yaml | 5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
33 "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
46 - const: sifive,plic-1.0.0
52 const: 0
85 #address-cells = <0>;
87 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
95 reg = <0xc000000 0x4000000>;
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| /kernel/linux/linux-5.10/arch/riscv/boot/dts/kendryte/ |
| D | k210.dtsi | 29 #size-cells = <0>;
31 cpu0: cpu@0 {
33 reg = <0>;
37 i-cache-size = <0x8000>;
39 d-cache-size = <0x8000>;
55 i-cache-size = <0x8000>;
57 d-cache-size = <0x8000>;
71 reg = <0x80000000 0x400000>,
72 <0x80400000 0x200000>,
73 <0x80600000 0x200000>;
[all …]
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| /kernel/linux/linux-4.19/drivers/staging/rtl8188eu/include/ |
| D | hal8188e_phy_reg.h | 11 /* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF */
13 /* 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 */
14 /* 3. RF register 0x00-2E */
22 /* 1. Page1(0x100) */
24 #define rPMAC_Reset 0x100
25 #define rPMAC_TxStart 0x104
26 #define rPMAC_TxLegacySIG 0x108
27 #define rPMAC_TxHTSIG1 0x10c
28 #define rPMAC_TxHTSIG2 0x110
29 #define rPMAC_PHYDebug 0x114
[all …]
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| /kernel/linux/linux-4.19/drivers/staging/rtl8712/ |
| D | rtl871x_mp_phy_regdef.h | 37 * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
39 * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
40 * 3. RF register 0x00-2E
45 * 1. Page1(0x100)
47 #define rPMAC_Reset 0x100
48 #define rPMAC_TxStart 0x104
49 #define rPMAC_TxLegacySIG 0x108
50 #define rPMAC_TxHTSIG1 0x10c
51 #define rPMAC_TxHTSIG2 0x110
52 #define rPMAC_PHYDebug 0x114
[all …]
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| /kernel/linux/linux-5.10/drivers/staging/rtl8712/ |
| D | rtl871x_mp_phy_regdef.h | 37 * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
39 * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
40 * 3. RF register 0x00-2E
45 * 1. Page1(0x100)
47 #define rPMAC_Reset 0x100
48 #define rPMAC_TxStart 0x104
49 #define rPMAC_TxLegacySIG 0x108
50 #define rPMAC_TxHTSIG1 0x10c
51 #define rPMAC_TxHTSIG2 0x110
52 #define rPMAC_PHYDebug 0x114
[all …]
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| /kernel/linux/linux-4.19/drivers/staging/rtl8723bs/include/ |
| D | Hal8192CPhyReg.h | 41 /* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF */
43 /* 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 */
44 /* 3. RF register 0x00-2E */
52 /* 1. Page1(0x100) */
54 #define rPMAC_Reset 0x100
55 #define rPMAC_TxStart 0x104
56 #define rPMAC_TxLegacySIG 0x108
57 #define rPMAC_TxHTSIG1 0x10c
58 #define rPMAC_TxHTSIG2 0x110
59 #define rPMAC_PHYDebug 0x114
[all …]
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| /kernel/linux/linux-5.10/drivers/staging/rtl8723bs/include/ |
| D | Hal8192CPhyReg.h | 41 /* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF */
43 /* 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 */
44 /* 3. RF register 0x00-2E */
52 /* 1. Page1(0x100) */
54 #define rPMAC_Reset 0x100
55 #define rPMAC_TxStart 0x104
56 #define rPMAC_TxLegacySIG 0x108
57 #define rPMAC_TxHTSIG1 0x10c
58 #define rPMAC_TxHTSIG2 0x110
59 #define rPMAC_PHYDebug 0x114
[all …]
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| /kernel/linux/linux-5.10/arch/mips/boot/dts/ralink/ |
| D | mt7628a.dtsi | 10 #size-cells = <0>;
12 cpu@0 {
15 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10000000 0x200000>;
34 ranges = <0x0 0x10000000 0x1FFFFF>;
39 sysc: system-controller@0 {
41 reg = <0x0 0x60>;
46 reg = <0x60 0x8>;
48 #size-cells = <0>;
[all …]
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| /kernel/linux/linux-4.19/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| D | uvd_4_2_sh_mask.h | 27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
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| D | uvd_5_0_sh_mask.h | 27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| D | uvd_4_2_sh_mask.h | 27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
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| D | uvd_3_1_sh_mask.h | 27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
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| D | uvd_5_0_sh_mask.h | 27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
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| D | uvd_6_0_sh_mask.h | 27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
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| /kernel/linux/linux-4.19/drivers/staging/rtlwifi/rtl8822be/ |
| D | reg.h | 21 #define TXPKT_BUF_SELECT 0x69
22 #define RXPKT_BUF_SELECT 0xA5
23 #define DISABLE_TRXPKT_BUF_ACCESS 0x0
25 /* Page 0 */
26 #define REG_LEDCFG2_8822B 0x004E /* need review */
27 #define REG_SPS0_CTRL_8822B 0x0011 /* need review: swlps */
29 #define REG_EFUSE_ACCESS_8822B (REG_PMC_DBG_CTRL2_8822B + 3) /*0x00CF*/
37 /* for MSR 0x102 */
38 #define MSR_NOLINK 0x00
39 #define MSR_ADHOC 0x01
[all …]
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| /kernel/linux/linux-4.19/arch/arm/boot/dts/ |
| D | at91sam9m10g45ek.dts | 23 reg = <0x70000000 0x4000000>;
43 timer@0 {
45 reg = <0>, <1>;
55 pinctrl-0 =
71 reg = <0x30>;
73 pinctrl-0 = <&pinctrl_pck1_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>;
99 pinctrl-0 = <
104 slot@0 {
105 reg = <0>;
112 pinctrl-0 = <
[all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | at91sam9m10g45ek.dts | 22 reg = <0x70000000 0x4000000>;
42 timer@0 {
44 reg = <0>, <1>;
54 pinctrl-0 =
70 reg = <0x30>;
72 pinctrl-0 = <&pinctrl_pck1_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>;
98 pinctrl-0 = <
104 slot@0 {
105 reg = <0>;
112 pinctrl-0 = <
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/wireless/ |
| D | qcom,ath11k.yaml | 161 reg = <0xCD00000 0x4040>,
162 <0x4AB000 0x20>;
169 reg = <0xc000000 0x2000000>;
170 interrupts = <0 320 1>,
171 <0 319 1>,
172 <0 318 1>,
173 <0 317 1>,
174 <0 316 1>,
175 <0 315 1>,
176 <0 314 1>,
[all …]
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| /kernel/linux/linux-5.10/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/ |
| D | reg.h | 7 #define REG_SYS_ISO_CTRL 0x0000
8 #define REG_SYS_FUNC_EN 0x0002
9 #define REG_APS_FSMCO 0x0004
10 #define REG_SYS_CLKR 0x0008
11 #define REG_9346CR 0x000A
12 #define REG_EE_VPD 0x000C
13 #define REG_AFE_MISC 0x0010
14 #define REG_SPS0_CTRL 0x0011
15 #define REG_SPS_OCP_CFG 0x0018
16 #define REG_RSV_CTRL 0x001C
[all …]
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| /kernel/linux/linux-4.19/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/ |
| D | reg.h | 29 #define REG_SYS_ISO_CTRL 0x0000
30 #define REG_SYS_FUNC_EN 0x0002
31 #define REG_APS_FSMCO 0x0004
32 #define REG_SYS_CLKR 0x0008
33 #define REG_9346CR 0x000A
34 #define REG_EE_VPD 0x000C
35 #define REG_AFE_MISC 0x0010
36 #define REG_SPS0_CTRL 0x0011
37 #define REG_SPS_OCP_CFG 0x0018
38 #define REG_RSV_CTRL 0x001C
[all …]
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| /kernel/linux/linux-5.10/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/ |
| D | reg.h | 7 #define REG_SYS_ISO_CTRL 0x0000
8 #define REG_SYS_FUNC_EN 0x0002
9 #define REG_APS_FSMCO 0x0004
10 #define REG_SYS_CLKR 0x0008
11 #define REG_9346CR 0x000A
12 #define REG_EE_VPD 0x000C
13 #define REG_AFE_MISC 0x0010
14 #define REG_SPS0_CTRL 0x0011
15 #define REG_SPS_OCP_CFG 0x0018
16 #define REG_RSV_CTRL 0x001C
[all …]
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| /kernel/linux/linux-5.10/arch/riscv/boot/dts/sifive/ |
| D | fu540-c000.dtsi | 24 #size-cells = <0>;
25 cpu0: cpu@0 {
31 reg = <0>;
144 compatible = "sifive,plic-1.0.0";
145 reg = <0x0 0xc000000 0x0 0x4000000>;
149 &cpu0_intc 0xffffffff
150 &cpu1_intc 0xffffffff &cpu1_intc 9
151 &cpu2_intc 0xffffffff &cpu2_intc 9
152 &cpu3_intc 0xffffffff &cpu3_intc 9
153 &cpu4_intc 0xffffffff &cpu4_intc 9>;
[all …]
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