Searched +full:0 +full:xd4015000 (Results 1 – 8 of 8) sorted by relevance
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | marvell,mmp2-clock.yaml | 62 reg = <0xd4050000 0x1000>, 63 <0xd4282800 0x400>, 64 <0xd4015000 0x1000>;
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| /kernel/linux/linux-4.19/arch/arm/boot/dts/ |
| D | pxa168.dtsi | 33 reg = <0xd4200000 0x00200000>; 40 reg = <0xd4282000 0x1000>; 50 reg = <0xd4000000 0x00200000>; 55 reg = <0xd4014000 0x100>; 61 reg = <0xd4017000 0x1000>; 70 reg = <0xd4018000 0x1000>; 79 reg = <0xd4026000 0x1000>; 90 reg = <0xd4019000 0x1000>; 102 reg = <0xd4019000 0x4>; 106 reg = <0xd4019004 0x4>; [all …]
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| D | pxa910.dtsi | 31 marvell,tauros2-cache-features = <0x3>; 38 reg = <0xd4200000 0x00200000>; 45 reg = <0xd4282000 0x1000>; 55 reg = <0xd4000000 0x00200000>; 60 reg = <0xd4014000 0x100>; 66 reg = <0xd4016000 0x100>; 73 reg = <0xd4017000 0x1000>; 82 reg = <0xd4018000 0x1000>; 91 reg = <0xd4036000 0x1000>; 102 reg = <0xd4019000 0x1000>; [all …]
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| D | mmp2.dtsi | 32 marvell,tauros2-cache-features = <0x3>; 39 reg = <0xd4200000 0x00200000>; 46 reg = <0xd4282000 0x1000>; 55 reg = <0x150 0x4>, <0x168 0x4>; 65 reg = <0x154 0x4>, <0x16c 0x4>; 76 reg = <0x180 0x4>, <0x17c 0x4>; 86 reg = <0x158 0x4>, <0x170 0x4>; 96 reg = <0x15c 0x4>, <0x174 0x4>; 106 reg = <0x160 0x4>, <0x178 0x4>; 116 reg = <0x188 0x4>, <0x184 0x4>; [all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | pxa168.dtsi | 32 reg = <0xd4200000 0x00200000>; 39 reg = <0xd4282000 0x1000>; 49 reg = <0xd4000000 0x00200000>; 54 reg = <0xd4014000 0x100>; 60 reg = <0xd4017000 0x1000>; 70 reg = <0xd4018000 0x1000>; 80 reg = <0xd4026000 0x1000>; 92 reg = <0xd4019000 0x1000>; 104 reg = <0xd4019000 0x4>; 108 reg = <0xd4019004 0x4>; [all …]
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| D | pxa910.dtsi | 30 marvell,tauros2-cache-features = <0x3>; 37 reg = <0xd4200000 0x00200000>; 44 reg = <0xd4282000 0x1000>; 54 reg = <0xd4000000 0x00200000>; 59 reg = <0xd4014000 0x100>; 65 reg = <0xd4016000 0x100>; 72 reg = <0xd4017000 0x1000>; 82 reg = <0xd4018000 0x1000>; 92 reg = <0xd4036000 0x1000>; 104 reg = <0xd4019000 0x1000>; [all …]
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| D | mmp2.dtsi | 32 marvell,tauros2-cache-features = <0x3>; 39 reg = <0xd4200000 0x00200000>; 44 reg = <0xd420d000 0x4000>; 57 reg = <0xd4282000 0x1000>; 66 reg = <0x150 0x4>, <0x168 0x4>; 76 reg = <0x154 0x4>, <0x16c 0x4>; 87 reg = <0x180 0x4>, <0x17c 0x4>; 97 reg = <0x158 0x4>, <0x170 0x4>; 107 reg = <0x15c 0x4>, <0x174 0x4>; 117 reg = <0x160 0x4>, <0x178 0x4>; [all …]
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| D | mmp3.dtsi | 16 #size-cells = <0>; 19 cpu@0 { 23 reg = <0>; 45 reg = <0xd4200000 0x00200000>; 52 reg = <0xd4282000 0x1000>, 53 <0xd4284000 0x100>; 62 reg = <0x150 0x4>, <0x168 0x4>; 72 reg = <0x154 0x4>, <0x16c 0x4>; 82 reg = <0x1bc 0x4>, <0x1a4 0x4>; 92 reg = <0x1c0 0x4>, <0x1a8 0x4>; [all …]
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