| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | msi.txt | 86 reg = <0xa 0xf00>;
93 reg = <0xb 0xf00>;
101 reg = <0xc 0xf00>;
108 dev@0 {
109 reg = <0x0 0xf00>;
117 reg = <0x1 0xf00>;
123 msi-parent = <&msi_a>, <&msi_b 0x17>;
127 reg = <0x2 0xf00>;
133 msi-parent = <&msi_a>, <&msi_b 0x17>, <&msi_c 0x53>;
|
| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/interrupt-controller/ |
| D | msi.txt | 86 reg = <0xa 0xf00>;
93 reg = <0xb 0xf00>;
101 reg = <0xb 0xf00>;
108 dev@0 {
109 reg = <0x0 0xf00>;
117 reg = <0x1 0xf00>;
123 msi-parent = <&msi_a>, <&msi_b 0x17>;
127 reg = <0x2 0xf00>;
133 msi-parent = <&msi_a>, <&msi_b 0x17>, <&msi_c 0x53>;
|
| /kernel/linux/linux-5.10/drivers/pinctrl/mediatek/ |
| D | pinctrl-mt2701.c | 39 /* 0E4E8SR 4/8/12/16 */
41 /* 0E2E4SR 2/4/6/8 */
44 MTK_DRV_GRP(2, 16, 0, 2, 2)
48 MTK_PIN_DRV_GRP(0, 0xf50, 0, 1),
49 MTK_PIN_DRV_GRP(1, 0xf50, 0, 1),
50 MTK_PIN_DRV_GRP(2, 0xf50, 0, 1),
51 MTK_PIN_DRV_GRP(3, 0xf50, 0, 1),
52 MTK_PIN_DRV_GRP(4, 0xf50, 0, 1),
53 MTK_PIN_DRV_GRP(5, 0xf50, 0, 1),
54 MTK_PIN_DRV_GRP(6, 0xf50, 0, 1),
[all …]
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| /kernel/linux/linux-4.19/drivers/pinctrl/mediatek/ |
| D | pinctrl-mt2701.c | 47 /* 0E4E8SR 4/8/12/16 */
49 /* 0E2E4SR 2/4/6/8 */
52 MTK_DRV_GRP(2, 16, 0, 2, 2)
56 MTK_PIN_DRV_GRP(0, 0xf50, 0, 1),
57 MTK_PIN_DRV_GRP(1, 0xf50, 0, 1),
58 MTK_PIN_DRV_GRP(2, 0xf50, 0, 1),
59 MTK_PIN_DRV_GRP(3, 0xf50, 0, 1),
60 MTK_PIN_DRV_GRP(4, 0xf50, 0, 1),
61 MTK_PIN_DRV_GRP(5, 0xf50, 0, 1),
62 MTK_PIN_DRV_GRP(6, 0xf50, 0, 1),
[all …]
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| /kernel/linux/linux-5.10/drivers/regulator/ |
| D | mt6358-regulator.c | 16 #define MT6358_BUCK_MODE_AUTO 0
57 .enable_mask = BIT(0), \
61 .qi = BIT(0), \
112 .enable_mask = BIT(0), \
118 .qi = BIT(0), \
141 REGULATOR_LINEAR_RANGE(500000, 0, 0x7f, 6250),
145 REGULATOR_LINEAR_RANGE(500000, 0, 0x7f, 12500),
149 REGULATOR_LINEAR_RANGE(500000, 0, 0x3f, 50000),
153 REGULATOR_LINEAR_RANGE(1000000, 0, 0x7f, 12500),
204 0, 12,
[all …]
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| /kernel/linux/linux-5.10/drivers/net/ethernet/moxa/ |
| D | moxart_ether.h | 18 #define TX_REG_OFFSET_DESC0 0
23 #define RX_REG_OFFSET_DESC0 0
28 #define TX_DESC0_PKT_LATE_COL 0x1 /* abort, late collision */
29 #define TX_DESC0_RX_PKT_EXS_COL 0x2 /* abort, >16 collisions */
30 #define TX_DESC0_DMA_OWN 0x80000000 /* owned by controller */
31 #define TX_DESC1_BUF_SIZE_MASK 0x7ff
32 #define TX_DESC1_LTS 0x8000000 /* last TX packet */
33 #define TX_DESC1_FTS 0x10000000 /* first TX packet */
34 #define TX_DESC1_FIFO_COMPLETE 0x20000000
35 #define TX_DESC1_INTR_COMPLETE 0x40000000
[all …]
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| /kernel/linux/linux-4.19/drivers/net/ethernet/moxa/ |
| D | moxart_ether.h | 18 #define TX_REG_OFFSET_DESC0 0
23 #define RX_REG_OFFSET_DESC0 0
28 #define TX_DESC0_PKT_LATE_COL 0x1 /* abort, late collision */
29 #define TX_DESC0_RX_PKT_EXS_COL 0x2 /* abort, >16 collisions */
30 #define TX_DESC0_DMA_OWN 0x80000000 /* owned by controller */
31 #define TX_DESC1_BUF_SIZE_MASK 0x7ff
32 #define TX_DESC1_LTS 0x8000000 /* last TX packet */
33 #define TX_DESC1_FTS 0x10000000 /* first TX packet */
34 #define TX_DESC1_FIFO_COMPLETE 0x20000000
35 #define TX_DESC1_INTR_COMPLETE 0x40000000
[all …]
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| /kernel/linux/linux-5.10/arch/arm/mm/ |
| D | tlb-v4wbi.S | 34 mov r3, #0
35 mcr p15, 0, r3, c7, c10, 4 @ drain WB
37 bic r0, r0, #0x0ff
38 bic r0, r0, #0xf00
40 mcrne p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
41 mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
48 mov r3, #0
49 mcr p15, 0, r3, c7, c10, 4 @ drain WB
50 bic r0, r0, #0x0ff
51 bic r0, r0, #0xf00
[all …]
|
| D | tlb-v4wb.S | 36 mcr p15, 0, r3, c7, c10, 4 @ drain WB
38 mcrne p15, 0, r3, c8, c5, 0 @ invalidate I TLB
39 bic r0, r0, #0x0ff
40 bic r0, r0, #0xf00
41 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
57 mov r3, #0
58 mcr p15, 0, r3, c7, c10, 4 @ drain WB
59 bic r0, r0, #0x0ff
60 bic r0, r0, #0xf00
61 mcr p15, 0, r3, c8, c5, 0 @ invalidate I TLB
[all …]
|
| D | tlb-fa.S | 39 mov r3, #0
40 mcr p15, 0, r3, c7, c10, 4 @ drain WB
41 bic r0, r0, #0x0ff
42 bic r0, r0, #0xf00
43 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry
47 mcr p15, 0, r3, c7, c10, 4 @ data write barrier
52 mov r3, #0
53 mcr p15, 0, r3, c7, c10, 4 @ drain WB
54 bic r0, r0, #0x0ff
55 bic r0, r0, #0xf00
[all …]
|
| /kernel/linux/linux-4.19/arch/arm/mm/ |
| D | tlb-v4wbi.S | 37 mov r3, #0
38 mcr p15, 0, r3, c7, c10, 4 @ drain WB
40 bic r0, r0, #0x0ff
41 bic r0, r0, #0xf00
43 mcrne p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
44 mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
51 mov r3, #0
52 mcr p15, 0, r3, c7, c10, 4 @ drain WB
53 bic r0, r0, #0x0ff
54 bic r0, r0, #0xf00
[all …]
|
| D | tlb-fa.S | 42 mov r3, #0
43 mcr p15, 0, r3, c7, c10, 4 @ drain WB
44 bic r0, r0, #0x0ff
45 bic r0, r0, #0xf00
46 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry
50 mcr p15, 0, r3, c7, c10, 4 @ data write barrier
55 mov r3, #0
56 mcr p15, 0, r3, c7, c10, 4 @ drain WB
57 bic r0, r0, #0x0ff
58 bic r0, r0, #0xf00
[all …]
|
| D | tlb-v4wb.S | 39 mcr p15, 0, r3, c7, c10, 4 @ drain WB
41 mcrne p15, 0, r3, c8, c5, 0 @ invalidate I TLB
42 bic r0, r0, #0x0ff
43 bic r0, r0, #0xf00
44 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
60 mov r3, #0
61 mcr p15, 0, r3, c7, c10, 4 @ drain WB
62 bic r0, r0, #0x0ff
63 bic r0, r0, #0xf00
64 mcr p15, 0, r3, c8, c5, 0 @ invalidate I TLB
[all …]
|
| /kernel/linux/linux-5.10/drivers/media/pci/ddbridge/ |
| D | ddbridge-hw.c | 25 .base = 0x200,
26 .num = 0x08,
27 .size = 0x10,
31 .base = 0x280,
32 .num = 0x08,
33 .size = 0x10,
37 .base = 0x300,
38 .num = 0x08,
39 .size = 0x10,
43 .base = 0x2000,
[all …]
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| /kernel/linux/linux-4.19/drivers/media/pci/ddbridge/ |
| D | ddbridge-hw.c | 25 .base = 0x200,
26 .num = 0x08,
27 .size = 0x10,
31 .base = 0x280,
32 .num = 0x08,
33 .size = 0x10,
37 .base = 0x300,
38 .num = 0x08,
39 .size = 0x10,
43 .base = 0x2000,
[all …]
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/gmc/ |
| D | gmc_7_1_sh_mask.h | 27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
|
| D | gmc_8_1_sh_mask.h | 27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
|
| /kernel/linux/linux-4.19/drivers/gpu/drm/amd/include/asic_reg/gmc/ |
| D | gmc_7_1_sh_mask.h | 27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
|
| D | gmc_8_1_sh_mask.h | 27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| D | uvd_5_0_sh_mask.h | 27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
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| D | uvd_6_0_sh_mask.h | 27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
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| /kernel/linux/linux-4.19/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| D | uvd_5_0_sh_mask.h | 27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
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| D | uvd_6_0_sh_mask.h | 27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
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| /kernel/linux/linux-4.19/drivers/hwtracing/coresight/ |
| D | coresight-priv.h | 15 * Coresight management registers (0xf00-0xfcc)
16 * 0xfa0 - 0xfa4: Management registers in PFTv1.0
19 #define CORESIGHT_ITCTRL 0xf00
20 #define CORESIGHT_CLAIMSET 0xfa0
21 #define CORESIGHT_CLAIMCLR 0xfa4
22 #define CORESIGHT_LAR 0xfb0
23 #define CORESIGHT_LSR 0xfb4
24 #define CORESIGHT_AUTHSTATUS 0xfb8
25 #define CORESIGHT_DEVID 0xfc8
26 #define CORESIGHT_DEVTYPE 0xfcc
[all …]
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| /kernel/linux/linux-4.19/arch/microblaze/pci/ |
| D | indirect_pci.c | 27 u8 cfg_type = 0; in indirect_read_config()
33 if (devfn != 0) in indirect_read_config()
45 reg = ((offset & 0xf00) << 16) | (offset & 0xfc); in indirect_read_config()
47 reg = offset & 0xfc; /* Only 3 bits for function */ in indirect_read_config()
50 out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) | in indirect_read_config()
53 out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) | in indirect_read_config()
81 u8 cfg_type = 0; in indirect_write_config()
87 if (devfn != 0) in indirect_write_config()
99 reg = ((offset & 0xf00) << 16) | (offset & 0xfc); in indirect_write_config()
101 reg = offset & 0xfc; in indirect_write_config()
[all …]
|