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/kernel/linux/linux-5.10/arch/mips/boot/dts/loongson/
Dloongson64c-package.dtsi10 #address-cells = <0>;
20 ranges = <0 0x1fe00000 0 0x1fe00000 0x100000
21 0 0x3ff00000 0 0x3ff00000 0x100000
23 0xefd 0xfb000000 0xefd 0xfb000000 0x10000000
25 0x1efd 0xfb000000 0x1efd 0xfb000000 0x10000000>;
29 reg = <0 0x3ff01400 0x64>;
38 loongson,parent_int_map = <0xf0ffffff>, /* int0 */
39 <0x0f000000>, /* int1 */
40 <0x00000000>, /* int2 */
41 <0x00000000>; /* int3 */
[all …]
Dloongson64g-package.dtsi10 #address-cells = <0>;
20 ranges = <0 0x1fe00000 0 0x1fe00000 0x100000
21 0 0x3ff00000 0 0x3ff00000 0x100000
22 0xefd 0xfb000000 0xefd 0xfb000000 0x10000000>;
26 reg = <0 0x3ff01400 0x64>;
35 loongson,parent_int_map = <0x00ffffff>, /* int0 */
36 <0xff000000>, /* int1 */
37 <0x00000000>, /* int2 */
38 <0x00000000>; /* int3 */
44 reg = <0 0x1fe00100 0x10>;
[all …]
Dloongson64v_4core_virtio.dts12 #address-cells = <0>;
22 ranges = <0 0x1fe00000 0 0x1fe00000 0x100000
23 0 0x3ff00000 0 0x3ff00000 0x100000
24 0xefd 0xfb000000 0xefd 0xfb000000 0x10000000>;
28 reg = <0 0x3ff01400 0x64>;
37 loongson,parent_int_map = <0x00000001>, /* int0 */
38 <0xfffffffe>, /* int1 */
39 <0x00000000>, /* int2 */
40 <0x00000000>; /* int3 */
46 reg = <0 0x1fe001e0 0x8>;
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-footbridge/include/mach/
Dhardware.h13 * 0xff800000 0x40000000 1MB X-Bus
14 * 0xff000000 0x7c000000 1MB PCI I/O space
15 * 0xfe000000 0x42000000 1MB CSR
16 * 0xfd000000 0x78000000 1MB Outbound write flush (not supported)
17 * 0xfc000000 0x79000000 1MB PCI IACK/special space
18 * 0xfb000000 0x7a000000 16MB PCI Config type 1
19 * 0xfa000000 0x7b000000 16MB PCI Config type 0
20 * 0xf9000000 0x50000000 1MB Cache flush
21 * 0xf0000000 0x80000000 16MB ISA memory
30 #define XBUS_SIZE 0x00100000
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dmarvell,prestera.txt21 ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>;
23 packet-processor@0 {
25 reg = <0 0x4000000>;
45 ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
46 reg = <MBUS_ID(0x08, 0x00) 0 0x100000>;
73 that BAR2 is assigned to 0xf6000000 as base address from the PCI IO range:
76 ranges = <0x81000000 0x0 0xfb000000 0x0 0xfb000000 0x0 0xf0000
77 0x82000000 0x0 0xf6000000 0x0 0xf6000000 0x0 0x2000000
78 0x82000000 0x0 0xf9000000 0x0 0xf9000000 0x0 0x100000>;
79 phys = <&cp0_comphy0 0>;
/kernel/linux/linux-4.19/arch/arm/mach-footbridge/include/mach/
Dhardware.h16 * 0xff800000 0x40000000 1MB X-Bus
17 * 0xff000000 0x7c000000 1MB PCI I/O space
18 * 0xfe000000 0x42000000 1MB CSR
19 * 0xfd000000 0x78000000 1MB Outbound write flush (not supported)
20 * 0xfc000000 0x79000000 1MB PCI IACK/special space
21 * 0xfb000000 0x7a000000 16MB PCI Config type 1
22 * 0xfa000000 0x7b000000 16MB PCI Config type 0
23 * 0xf9000000 0x50000000 1MB Cache flush
24 * 0xf0000000 0x80000000 16MB ISA memory
33 #define XBUS_SIZE 0x00100000
[all …]
/kernel/linux/linux-5.10/Documentation/x86/
Dmtrr.rst73 reg00: base=0x00000000 ( 0MB), size= 128MB: write-back, count=1
74 reg01: base=0x08000000 ( 128MB), size= 64MB: write-back, count=1
78 # echo "base=0xf8000000 size=0x400000 type=write-combining" >! /proc/mtrr
82 # echo "base=0xf8000000 size=0x400000 type=write-combining" >| /proc/mtrr
87 reg00: base=0x00000000 ( 0MB), size= 128MB: write-back, count=1
88 reg01: base=0x08000000 ( 128MB), size= 64MB: write-back, count=1
89 reg02: base=0xf8000000 (3968MB), size= 4MB: write-combining, count=1
91 This is for video RAM at base address 0xf8000000 and size 4 megabytes. To
96 (--) S3: PCI: 968 rev 0, Linear FB @ 0xf8000000
107 That's 4 megabytes, which is 0x400000 bytes (in hexadecimal).
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/dispnv50/
Dhandles.h10 #define NV50_DISP_HANDLE_SYNCBUF 0xf0000000
11 #define NV50_DISP_HANDLE_VRAM 0xf0000001
13 #define NV50_DISP_HANDLE_WNDW_CTX(kind) (0xfb000000 | kind)
14 #define NV50_DISP_HANDLE_CRC_CTX(head, i) (0xfc000000 | head->base.index << 1 | i)
/kernel/linux/linux-4.19/Documentation/x86/
Dmtrr.txt68 reg00: base=0x00000000 ( 0MB), size= 128MB: write-back, count=1
69 reg01: base=0x08000000 ( 128MB), size= 64MB: write-back, count=1
72 # echo "base=0xf8000000 size=0x400000 type=write-combining" >! /proc/mtrr
74 # echo "base=0xf8000000 size=0x400000 type=write-combining" >| /proc/mtrr
78 reg00: base=0x00000000 ( 0MB), size= 128MB: write-back, count=1
79 reg01: base=0x08000000 ( 128MB), size= 64MB: write-back, count=1
80 reg02: base=0xf8000000 (3968MB), size= 4MB: write-combining, count=1
82 This is for video RAM at base address 0xf8000000 and size 4 megabytes. To
87 (--) S3: PCI: 968 rev 0, Linear FB @ 0xf8000000
98 That's 4 megabytes, which is 0x400000 bytes (in hexadecimal).
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-omap2/
Diomap.h33 #define OMAP2_L3_IO_OFFSET 0x90000000
36 #define OMAP2_L4_IO_OFFSET 0xb2000000
39 #define OMAP4_L3_IO_OFFSET 0xb4000000
42 #define AM33XX_L4_WK_IO_OFFSET 0xb5000000
45 #define OMAP4_L3_PER_IO_OFFSET 0xb1100000
48 #define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */
58 #define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/
61 #define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */
65 #define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */
70 /* 0x6e000000 --> 0xfe000000 */
[all …]
/kernel/linux/linux-4.19/arch/arm/mach-omap2/
Diomap.h33 #define OMAP2_L3_IO_OFFSET 0x90000000
36 #define OMAP2_L4_IO_OFFSET 0xb2000000
39 #define OMAP4_L3_IO_OFFSET 0xb4000000
42 #define AM33XX_L4_WK_IO_OFFSET 0xb5000000
45 #define OMAP4_L3_PER_IO_OFFSET 0xb1100000
48 #define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */
58 #define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/
61 #define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */
65 #define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */
70 /* 0x6e000000 --> 0xfe000000 */
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/spi/
Dnuvoton,npcm-fiu.txt12 - #size-cells : should be 0.
20 - pinctrl-0 : phandle referencing pin configuration of the device.
29 fiu0 represent fiu 0 controller
37 #size-cells = <0>;
38 reg = <0xfb000000 0x1000>, <0x80000000 0x10000000>;
42 pinctrl-0 = <&spi3_pins>;
43 spi-nor@0 {
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/
Dcdns,cdns-pcie-host.yaml47 bus-range = <0x0 0xff>;
48 linux,pci-domain = <0>;
49 vendor-id = <0x17cd>;
50 device-id = <0x0200>;
52 reg = <0x0 0xfb000000 0x0 0x01000000>,
53 <0x0 0x41000000 0x0 0x00001000>;
56 ranges = <0x02000000 0x0 0x42000000 0x0 0x42000000 0x0 0x1000000>,
57 <0x01000000 0x0 0x43000000 0x0 0x43000000 0x0 0x0010000>;
58 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x1 0x00000000>;
60 #interrupt-cells = <0x1>;
[all …]
/kernel/linux/linux-4.19/arch/arm/mach-spear/include/mach/
Dspear.h21 #define SPEAR_ICM1_2_BASE UL(0xD0000000)
22 #define VA_SPEAR_ICM1_2_BASE IOMEM(0xFD000000)
23 #define SPEAR_ICM1_UART_BASE UL(0xD0000000)
25 #define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000)
28 #define SPEAR_ICM3_ML1_2_BASE UL(0xF0000000)
29 #define VA_SPEAR6XX_ML_CPU_BASE IOMEM(0xF0000000)
32 #define SPEAR_ICM3_SMI_CTRL_BASE UL(0xFC000000)
33 #define VA_SPEAR_ICM3_SMI_CTRL_BASE IOMEM(0xFC000000)
34 #define SPEAR_ICM3_DMA_BASE UL(0xFC400000)
35 #define SPEAR_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-spear/include/mach/
Dspear.h21 #define SPEAR_ICM1_2_BASE UL(0xD0000000)
22 #define VA_SPEAR_ICM1_2_BASE IOMEM(0xFD000000)
23 #define SPEAR_ICM1_UART_BASE UL(0xD0000000)
25 #define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000)
28 #define SPEAR_ICM3_ML1_2_BASE UL(0xF0000000)
29 #define VA_SPEAR6XX_ML_CPU_BASE IOMEM(0xF0000000)
32 #define SPEAR_ICM3_SMI_CTRL_BASE UL(0xFC000000)
33 #define VA_SPEAR_ICM3_SMI_CTRL_BASE IOMEM(0xFC000000)
34 #define SPEAR_ICM3_DMA_BASE UL(0xFC400000)
35 #define SPEAR_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/pci/
Dcdns,cdns-pcie-host.txt38 bus-range = <0x0 0xff>;
39 linux,pci-domain = <0>;
42 vendor-id = /bits/ 16 <0x17cd>;
43 device-id = /bits/ 16 <0x0200>;
45 reg = <0x0 0xfb000000 0x0 0x01000000>,
46 <0x0 0x41000000 0x0 0x00001000>,
47 <0x0 0x40000000 0x0 0x04000000>;
50 ranges = <0x02000000 0x0 0x42000000 0x0 0x42000000 0x0 0x1000000>,
51 <0x01000000 0x0 0x43000000 0x0 0x43000000 0x0 0x0010000>;
53 #interrupt-cells = <0x1>;
[all …]
/kernel/linux/linux-4.19/arch/arm/mach-spear/
Dspear13xx.c41 writel_relaxed(0x06, VA_L2CC_BASE + L310_PREFETCH_CTRL); in spear13xx_l2x0_init()
47 writel_relaxed(0x221, VA_L2CC_BASE + L310_TAG_LATENCY_CTRL); in spear13xx_l2x0_init()
48 writel_relaxed(0x441, VA_L2CC_BASE + L310_DATA_LATENCY_CTRL); in spear13xx_l2x0_init()
49 l2x0_init(VA_L2CC_BASE, 0x30a00001, 0xfe0fffff); in spear13xx_l2x0_init()
55 * 0xB3000000 0xF9000000
56 * 0xE0000000 0xFD000000
57 * 0xEC000000 0xFC000000
58 * 0xED000000 0xFB000000
/kernel/linux/linux-5.10/arch/arm/mach-spear/
Dspear13xx.c41 writel_relaxed(0x06, VA_L2CC_BASE + L310_PREFETCH_CTRL); in spear13xx_l2x0_init()
47 writel_relaxed(0x221, VA_L2CC_BASE + L310_TAG_LATENCY_CTRL); in spear13xx_l2x0_init()
48 writel_relaxed(0x441, VA_L2CC_BASE + L310_DATA_LATENCY_CTRL); in spear13xx_l2x0_init()
49 l2x0_init(VA_L2CC_BASE, 0x30a00001, 0xfe0fffff); in spear13xx_l2x0_init()
55 * 0xB3000000 0xF9000000
56 * 0xE0000000 0xFD000000
57 * 0xEC000000 0xFC000000
58 * 0xED000000 0xFB000000
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/bridge/
Dcdns,mhdp8546.yaml69 const: 0
71 port@0:
97 - port@0
142 reg = <0xf0 0xfb000000 0x0 0x1000000>;
151 #size-cells = <0>;
153 port@0 {
154 reg = <0>;
/kernel/linux/linux-4.19/arch/powerpc/boot/dts/fsl/
Dkmcoge4.dts34 size = <0 0x1000000>;
35 alignment = <0 0x1000000>;
38 size = <0 0x400000>;
39 alignment = <0 0x400000>;
42 size = <0 0x2000000>;
43 alignment = <0 0x2000000>;
48 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
52 ranges = <0x0 0xf 0xf4000000 0x200000>;
56 ranges = <0x0 0xf 0xf4200000 0x200000>;
60 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
[all …]
/kernel/linux/linux-5.10/arch/powerpc/boot/dts/fsl/
Dkmcoge4.dts30 size = <0 0x1000000>;
31 alignment = <0 0x1000000>;
34 size = <0 0x400000>;
35 alignment = <0 0x400000>;
38 size = <0 0x2000000>;
39 alignment = <0 0x2000000>;
44 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
48 ranges = <0x0 0xf 0xf4000000 0x200000>;
52 ranges = <0x0 0xf 0xf4200000 0x200000>;
56 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
[all …]
/kernel/linux/linux-4.19/arch/powerpc/platforms/embedded6xx/
Dmpc7448_hpc2.c49 #define DBG(fmt...) do { printk(fmt); } while(0)
51 #define DBG(fmt...) do { } while(0)
54 #define MPC7448HPC2_PCI_CFG_PHYS 0xfb000000
59 if (bus == 0 && PCI_SLOT(devfn) == 0) in mpc7448_hpc2_exclude_device()
69 ppc_md.progress("mpc7448_hpc2_setup_arch():set_bridge", 0); in mpc7448_hpc2_setup_arch()
76 tsi108_setup_pci(np, MPC7448HPC2_PCI_CFG_PHYS, 0); in mpc7448_hpc2_setup_arch()
80 ppc_md.progress("tsi108: resources set", 0x100); in mpc7448_hpc2_setup_arch()
96 * TSI108:PB_INT[0] -> CPU0:INT#
110 mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN | in mpc7448_hpc2_init_IRQ()
112 24, 0, in mpc7448_hpc2_init_IRQ()
[all …]
/kernel/linux/linux-5.10/arch/powerpc/platforms/embedded6xx/
Dmpc7448_hpc2.c45 #define DBG(fmt...) do { printk(fmt); } while(0)
47 #define DBG(fmt...) do { } while(0)
50 #define MPC7448HPC2_PCI_CFG_PHYS 0xfb000000
55 if (bus == 0 && PCI_SLOT(devfn) == 0) in mpc7448_hpc2_exclude_device()
65 ppc_md.progress("mpc7448_hpc2_setup_arch():set_bridge", 0); in mpc7448_hpc2_setup_arch()
72 tsi108_setup_pci(np, MPC7448HPC2_PCI_CFG_PHYS, 0); in mpc7448_hpc2_setup_arch()
76 ppc_md.progress("tsi108: resources set", 0x100); in mpc7448_hpc2_setup_arch()
92 * TSI108:PB_INT[0] -> CPU0:INT#
106 mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN | in mpc7448_hpc2_init_IRQ()
108 24, 0, in mpc7448_hpc2_init_IRQ()
[all …]
/kernel/linux/linux-5.10/arch/sh/kernel/cpu/sh2/
Dsetup-sh7619.c18 UNUSED = 0,
49 { 0xf8140006, 0, 16, 4, /* IPRA */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
50 { 0xf8140008, 0, 16, 4, /* IPRB */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
51 { 0xf8080000, 0, 16, 4, /* IPRC */ { WDT, EDMAC, CMT0, CMT1 } },
52 { 0xf8080002, 0, 16, 4, /* IPRD */ { SCIF0, SCIF1, SCIF2 } },
53 { 0xf8080004, 0, 16, 4, /* IPRE */ { HIF_HIFI, HIF_HIFBI } },
54 { 0xf8080006, 0, 16, 4, /* IPRF */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
55 { 0xf8080008, 0, 16, 4, /* IPRG */ { SIOF } },
67 DEFINE_RES_MEM(0xf8400000, 0x100),
73 .id = 0,
[all …]
/kernel/linux/linux-4.19/arch/sh/kernel/cpu/sh2/
Dsetup-sh7619.c20 UNUSED = 0,
51 { 0xf8140006, 0, 16, 4, /* IPRA */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
52 { 0xf8140008, 0, 16, 4, /* IPRB */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
53 { 0xf8080000, 0, 16, 4, /* IPRC */ { WDT, EDMAC, CMT0, CMT1 } },
54 { 0xf8080002, 0, 16, 4, /* IPRD */ { SCIF0, SCIF1, SCIF2 } },
55 { 0xf8080004, 0, 16, 4, /* IPRE */ { HIF_HIFI, HIF_HIFBI } },
56 { 0xf8080006, 0, 16, 4, /* IPRF */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
57 { 0xf8080008, 0, 16, 4, /* IPRG */ { SIOF } },
69 DEFINE_RES_MEM(0xf8400000, 0x100),
75 .id = 0,
[all …]

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