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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/fpga/
Daltera-hps2fpga-bridge.txt17 reg = <0xff400000 0x100000>;
20 bridge-enable = <0>;
25 reg = <0xff500000 0x10000>;
33 reg = <0xff600000 0x100000>;
Dfpga-region.txt210 bridge's region (0xff200000) and the hps bridge's region (0xc0000000) for use by
218 reg = <0xff706000 0x1000
219 0xffb90000 0x20>;
220 interrupts = <0 175 4>;
225 reg = <0xff400000 0x100000>;
241 reg = <0xff500000 0x10000>;
250 fragment@0 {
260 ranges = <0x20000 0xff200000 0x100000>,
261 <0x0 0xc0000000 0x20000000>;
265 reg = <0x10040 0x20>;
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/fpga/
Daltera-hps2fpga-bridge.txt13 - bridge-enable : 0 if driver should disable bridge at startup.
20 reg = <0xff400000 0x100000>;
23 bridge-enable = <0>;
28 reg = <0xff500000 0x10000>;
36 reg = <0xff600000 0x100000>;
Dfpga-region.txt210 bridge's region (0xff200000) and the hps bridge's region (0xc0000000) for use by
218 reg = <0xff706000 0x1000
219 0xffb90000 0x20>;
220 interrupts = <0 175 4>;
225 reg = <0xff400000 0x100000>;
241 reg = <0xff500000 0x10000>;
250 fragment@0 {
260 ranges = <0x20000 0xff200000 0x100000>,
261 <0x0 0xc0000000 0x20000000>;
265 reg = <0x10040 0x20>;
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/nouveau/nvkm/engine/gr/
Dctxnv40.h45 ctx->ctxprog_reg = (reg - 0x00400000) >> 2; in cp_ctx()
52 length = 0; in cp_ctx()
68 for (i = 0; i < ctx->ctxprog_len; i++) { in cp_name()
69 if ((ctxprog[i] & 0xfff00000) != 0xff400000) in cp_name()
73 ctxprog[i] = (ctxprog[i] & 0x00ff00ff) | in cp_name()
81 int ip = 0; in _cp_bra()
85 if (ip == 0) in _cp_bra()
86 ip = 0xff000000 | (name << CP_BRA_IP_SHIFT); in _cp_bra()
90 (state ? 0 : CP_BRA_IF_CLEAR)); in _cp_bra()
92 #define cp_bra(c, f, s, n) _cp_bra((c), 0, CP_FLAG_##f, CP_FLAG_##f##_##s, n)
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/gr/
Dctxnv40.h45 ctx->ctxprog_reg = (reg - 0x00400000) >> 2; in cp_ctx()
52 length = 0; in cp_ctx()
68 for (i = 0; i < ctx->ctxprog_len; i++) { in cp_name()
69 if ((ctxprog[i] & 0xfff00000) != 0xff400000) in cp_name()
73 ctxprog[i] = (ctxprog[i] & 0x00ff00ff) | in cp_name()
81 int ip = 0; in _cp_bra()
85 if (ip == 0) in _cp_bra()
86 ip = 0xff000000 | (name << CP_BRA_IP_SHIFT); in _cp_bra()
90 (state ? 0 : CP_BRA_IF_CLEAR)); in _cp_bra()
92 #define cp_bra(c, f, s, n) _cp_bra((c), 0, CP_FLAG_##f, CP_FLAG_##f##_##s, n)
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/usb/
Damlogic,meson-g12a-usb-ctrl.yaml81 "^usb@[0-9a-f]+$":
199 reg = <0xffe09000 0xa0>;
215 reg = <0xff400000 0x40000>;
228 reg = <0xff500000 0x100000>;
/kernel/linux/linux-5.10/arch/mips/kernel/
Dbmips_vec.S35 * it to resume execution at 0x8000_0200 (!BEV IV vector) when it is
37 * it to a more convenient place: BMIPS_WARM_RESTART_VEC @ 0x8000_0380.
54 /* set up CPU1 CBR; move BASE to 0xa000_0000 */
55 li k0, 0xff400000
60 andi k1, 0x8000
63 li k1, 0xa0080000
64 sw k1, 0(k0)
78 * entire function gets copied to 0x8000_0000.
100 /* if we're not on core 0, this must be the SMP boot signal */
134 andi k0, 0xff00
[all …]
/kernel/linux/linux-4.19/arch/mips/kernel/
Dbmips_vec.S35 * it to resume execution at 0x8000_0200 (!BEV IV vector) when it is
37 * it to a more convenient place: BMIPS_WARM_RESTART_VEC @ 0x8000_0380.
54 /* set up CPU1 CBR; move BASE to 0xa000_0000 */
55 li k0, 0xff400000
60 andi k1, 0x8000
63 li k1, 0xa0080000
64 sw k1, 0(k0)
78 * entire function gets copied to 0x8000_0000.
100 /* if we're not on core 0, this must be the SMP boot signal */
134 andi k0, 0xff00
[all …]
/kernel/linux/linux-4.19/arch/arm/mach-pxa/
Dcm-x2xx.c53 #define CMX2XX_VIRT_BASE (void __iomem *)(0xe8000000)
69 #define CMX255_GPIO_IT8152_IRQ (0)
77 [0] = {
95 [0] = {
118 .id = 0,
155 [0] = {
183 cmx2xx_leds[0].gpio = CMX255_GPIO_RED; in cmx2xx_init_leds()
186 cmx2xx_leds[0].gpio = CMX270_GPIO_RED; in cmx2xx_init_leds()
201 #define MTYPE_STN320x240 0
216 .upper_margin = 0,
[all …]
/kernel/linux/linux-5.10/drivers/mtd/maps/
Dichxrom.c30 #define BIOS_CNTL 0x4e
31 #define FWH_DEC_EN1 0xE3
32 #define FWH_DEC_EN2 0xF0
33 #define FWH_SEL1 0xE8
34 #define FWH_SEL2 0xEE
83 window->phys = 0; in ichxrom_cleanup()
84 window->size = 0; in ichxrom_cleanup()
113 window->phys = 0; in ichxrom_init_one()
115 if (byte == 0xff) { in ichxrom_init_one()
116 window->phys = 0xffc00000; in ichxrom_init_one()
[all …]
Desb2rom.c34 #define BIOS_CNTL 0xDC
35 #define BIOS_LOCK_ENABLE 0x02
36 #define BIOS_WRITE_ENABLE 0x01
39 #define FWH_DEC_EN1 0xD8
40 #define FWH_F8_EN 0x8000
41 #define FWH_F0_EN 0x4000
42 #define FWH_E8_EN 0x2000
43 #define FWH_E0_EN 0x1000
44 #define FWH_D8_EN 0x0800
45 #define FWH_D0_EN 0x0400
[all …]
/kernel/linux/linux-4.19/drivers/mtd/maps/
Dichxrom.c29 #define BIOS_CNTL 0x4e
30 #define FWH_DEC_EN1 0xE3
31 #define FWH_DEC_EN2 0xF0
32 #define FWH_SEL1 0xE8
33 #define FWH_SEL2 0xEE
82 window->phys = 0; in ichxrom_cleanup()
83 window->size = 0; in ichxrom_cleanup()
112 window->phys = 0; in ichxrom_init_one()
114 if (byte == 0xff) { in ichxrom_init_one()
115 window->phys = 0xffc00000; in ichxrom_init_one()
[all …]
Desb2rom.c33 #define BIOS_CNTL 0xDC
34 #define BIOS_LOCK_ENABLE 0x02
35 #define BIOS_WRITE_ENABLE 0x01
38 #define FWH_DEC_EN1 0xD8
39 #define FWH_F8_EN 0x8000
40 #define FWH_F0_EN 0x4000
41 #define FWH_E8_EN 0x2000
42 #define FWH_E0_EN 0x1000
43 #define FWH_D8_EN 0x0800
44 #define FWH_D0_EN 0x0400
[all …]
/kernel/linux/linux-4.19/arch/powerpc/platforms/83xx/
Dsuspend-asm.S17 #define SS_MEMSAVE 0x00 /* First 8 bytes of RAM */
18 #define SS_HID 0x08 /* 3 HIDs */
19 #define SS_IABR 0x14 /* 2 IABRs */
20 #define SS_IBCR 0x1c
21 #define SS_DABR 0x20 /* 2 DABRs */
22 #define SS_DBCR 0x28
23 #define SS_SP 0x2c
24 #define SS_SR 0x30 /* 16 segment registers */
25 #define SS_R2 0x70
26 #define SS_MSR 0x74
[all …]
/kernel/linux/linux-5.10/arch/powerpc/platforms/83xx/
Dsuspend-asm.S14 #define SS_MEMSAVE 0x00 /* First 8 bytes of RAM */
15 #define SS_HID 0x08 /* 3 HIDs */
16 #define SS_IABR 0x14 /* 2 IABRs */
17 #define SS_IBCR 0x1c
18 #define SS_DABR 0x20 /* 2 DABRs */
19 #define SS_DBCR 0x28
20 #define SS_SP 0x2c
21 #define SS_SR 0x30 /* 16 segment registers */
22 #define SS_R2 0x70
23 #define SS_MSR 0x74
[all …]
/kernel/linux/linux-5.10/arch/m68k/include/asm/
Dio_mm.h47 #define q40_isa_io_base 0xff400000
48 #define q40_isa_mem_base 0xff800000
55 #define MULTI_ISA 0
65 #define MULTI_ISA 0
74 #define enec_isa_read_base 0xfffa0000
75 #define enec_isa_write_base 0xfffb0000
77 #define ENEC_ISA_IO_B(ioaddr) (enec_isa_read_base+((((unsigned long)(ioaddr))&0x7F)<<9))
78 #define ENEC_ISA_IO_W(ioaddr) (enec_isa_read_base+((((unsigned long)(ioaddr))&0x7F)<<9))
79 #define ENEC_ISA_MEM_B(madr) (enec_isa_read_base+((((unsigned long)(madr))&0x7F)<<9))
80 #define ENEC_ISA_MEM_W(madr) (enec_isa_read_base+((((unsigned long)(madr))&0x7F)<<9))
[all …]
/kernel/linux/linux-4.19/arch/m68k/include/asm/
Dio_mm.h47 #define q40_isa_io_base 0xff400000
48 #define q40_isa_mem_base 0xff800000
55 #define MULTI_ISA 0
65 #define MULTI_ISA 0
74 #define enec_isa_read_base 0xfffa0000
75 #define enec_isa_write_base 0xfffb0000
77 #define ENEC_ISA_IO_B(ioaddr) (enec_isa_read_base+((((unsigned long)(ioaddr))&0x7F)<<9))
78 #define ENEC_ISA_IO_W(ioaddr) (enec_isa_read_base+((((unsigned long)(ioaddr))&0x7F)<<9))
79 #define ENEC_ISA_MEM_B(madr) (enec_isa_read_base+((((unsigned long)(madr))&0x7F)<<9))
80 #define ENEC_ISA_MEM_W(madr) (enec_isa_read_base+((((unsigned long)(madr))&0x7F)<<9))
[all …]
/kernel/linux/linux-4.19/drivers/staging/wlan-ng/
Dprism2fw.c65 #define S3ADDR_PLUG (0xff000000UL)
66 #define S3ADDR_CRC (0xff100000UL)
67 #define S3ADDR_INFO (0xff200000UL)
68 #define S3ADDR_START (0xff400000UL)
204 * 0 - success
205 * ~0 - failure
215 PRISM2_USB_FWFILE, &udev->dev) != 0) { in prism2_fwtry()
229 return 0; in prism2_fwtry()
242 * 0 - success
243 * ~0 - failure
[all …]
/kernel/linux/linux-5.10/drivers/staging/wlan-ng/
Dprism2fw.c65 #define S3ADDR_PLUG (0xff000000UL)
66 #define S3ADDR_CRC (0xff100000UL)
67 #define S3ADDR_INFO (0xff200000UL)
68 #define S3ADDR_START (0xff400000UL)
204 * 0 - success
205 * ~0 - failure
215 PRISM2_USB_FWFILE, &udev->dev) != 0) { in prism2_fwtry()
229 return 0; in prism2_fwtry()
242 * 0 - success
243 * ~0 - failure
[all …]
/kernel/linux/linux-4.19/arch/arm/boot/dts/
Dsocfpga.dtsi37 #size-cells = <0>;
40 cpu0: cpu@0 {
43 reg = <0>;
57 interrupts = <0 176 4>, <0 177 4>;
59 reg = <0xff111000 0x1000>,
60 <0xff113000 0x1000>;
67 reg = <0xfffed000 0x1000>,
68 <0xfffec100 0x100>;
87 reg = <0xffe01000 0x1000>;
88 interrupts = <0 104 4>,
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dsocfpga.dtsi23 #size-cells = <0>;
26 cpu0: cpu@0 {
29 reg = <0>;
43 interrupts = <0 176 4>, <0 177 4>;
45 reg = <0xff111000 0x1000>,
46 <0xff113000 0x1000>;
53 reg = <0xfffed000 0x1000>,
54 <0xfffec100 0x100>;
73 reg = <0xffe01000 0x1000>;
74 interrupts = <0 104 4>,
[all …]
/kernel/linux/linux-5.10/arch/arm/probes/
Ddecode-thumb.c20 DECODE_REJECT (0xfe4f0000, 0xe80f0000),
24 DECODE_REJECT (0xffc00000, 0xe8000000),
27 DECODE_REJECT (0xffc00000, 0xe9800000),
30 DECODE_REJECT (0xfe508000, 0xe8008000),
32 DECODE_REJECT (0xfe50c000, 0xe810c000),
34 DECODE_REJECT (0xfe402000, 0xe8002000),
40 DECODE_CUSTOM (0xfe400000, 0xe8000000, PROBES_T32_LDMSTM),
50 DECODE_OR (0xff600000, 0xe8600000),
53 DECODE_EMULATEX (0xff400000, 0xe9400000, PROBES_T32_LDRDSTRD,
54 REGS(NOPCWB, NOSPPC, NOSPPC, 0, 0)),
[all …]
/kernel/linux/linux-4.19/arch/arm/probes/
Ddecode-thumb.c23 DECODE_REJECT (0xfe4f0000, 0xe80f0000),
27 DECODE_REJECT (0xffc00000, 0xe8000000),
30 DECODE_REJECT (0xffc00000, 0xe9800000),
33 DECODE_REJECT (0xfe508000, 0xe8008000),
35 DECODE_REJECT (0xfe50c000, 0xe810c000),
37 DECODE_REJECT (0xfe402000, 0xe8002000),
43 DECODE_CUSTOM (0xfe400000, 0xe8000000, PROBES_T32_LDMSTM),
53 DECODE_OR (0xff600000, 0xe8600000),
56 DECODE_EMULATEX (0xff400000, 0xe9400000, PROBES_T32_LDRDSTRD,
57 REGS(NOPCWB, NOSPPC, NOSPPC, 0, 0)),
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/amlogic/
Dmeson-axg.dtsi23 tdmif_a: audio-controller-0 {
25 #sound-dai-cells = <0>;
36 #sound-dai-cells = <0>;
47 #sound-dai-cells = <0>;
66 #address-cells = <0x2>;
67 #size-cells = <0x0>;
69 cpu0: cpu@0 {
72 reg = <0x0 0x0>;
75 clocks = <&scpi_dvfs 0>;
81 reg = <0x0 0x1>;
[all …]

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