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/kernel/linux/linux-4.19/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x_dump.h22 #define DRV_DUMP_XSTORM_WAITP_ADDRESS 0x2b8a80
23 #define DRV_DUMP_TSTORM_WAITP_ADDRESS 0x1b8a80
24 #define DRV_DUMP_USTORM_WAITP_ADDRESS 0x338a80
25 #define DRV_DUMP_CSTORM_WAITP_ADDRESS 0x238a80
45 #define BNX2X_DUMP_VERSION 0x61111111
65 static const u32 page_vals_e2[] = {0, 128};
68 {0x58000, 4608, DUMP_CHIP_E2, 0x30}
74 static const u32 page_vals_e3[] = {0, 128};
77 {0x58000, 4608, DUMP_CHIP_E3A0 | DUMP_CHIP_E3B0, 0x30}
81 { 0x2000, 1, 0x1f, 0xfff},
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x_dump.h22 #define DRV_DUMP_XSTORM_WAITP_ADDRESS 0x2b8a80
23 #define DRV_DUMP_TSTORM_WAITP_ADDRESS 0x1b8a80
24 #define DRV_DUMP_USTORM_WAITP_ADDRESS 0x338a80
25 #define DRV_DUMP_CSTORM_WAITP_ADDRESS 0x238a80
45 #define BNX2X_DUMP_VERSION 0x61111111
65 static const u32 page_vals_e2[] = {0, 128};
68 {0x58000, 4608, DUMP_CHIP_E2, 0x30}
74 static const u32 page_vals_e3[] = {0, 128};
77 {0x58000, 4608, DUMP_CHIP_E3A0 | DUMP_CHIP_E3B0, 0x30}
81 { 0x2000, 1, 0x1f, 0xfff},
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/mediatek/
Dmtk_dpi_regs.h9 #define DPI_EN 0x00
10 #define EN BIT(0)
12 #define DPI_RET 0x04
13 #define RST BIT(0)
15 #define DPI_INTEN 0x08
16 #define INT_VSYNC_EN BIT(0)
20 #define DPI_INTSTA 0x0C
21 #define INT_VSYNC_STA BIT(0)
25 #define DPI_CON 0x10
26 #define BG_ENABLE BIT(0)
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/mediatek/
Dmtk_dpi_regs.h17 #define DPI_EN 0x00
18 #define EN BIT(0)
20 #define DPI_RET 0x04
21 #define RST BIT(0)
23 #define DPI_INTEN 0x08
24 #define INT_VSYNC_EN BIT(0)
28 #define DPI_INTSTA 0x0C
29 #define INT_VSYNC_STA BIT(0)
33 #define DPI_CON 0x10
34 #define BG_ENABLE BIT(0)
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/radeon/
Drs780d.h26 #define CG_SPLL_FUNC_CNTL 0x600
27 # define SPLL_RESET (1 << 0)
33 # define SPLL_FB_DIV_MASK (0xff << 2)
39 # define SPLL_SW_HILEN_MASK (0xf << 16)
42 # define SPLL_SW_LOLEN_MASK (0xf << 20)
51 #define FVTHROT_CNTRL_REG 0x3000
52 #define DONT_WAIT_FOR_FBDIV_WRAP (1 << 0)
55 #define MINIMUM_CIP_MASK 0x1fffffe
58 #define REFRESH_RATE_DIVISOR_MASK (0x3 << 25)
64 #define FVTHROT_TARGET_REG 0x3004
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
Drs780d.h26 #define CG_SPLL_FUNC_CNTL 0x600
27 # define SPLL_RESET (1 << 0)
33 # define SPLL_FB_DIV_MASK (0xff << 2)
39 # define SPLL_SW_HILEN_MASK (0xf << 16)
42 # define SPLL_SW_LOLEN_MASK (0xf << 20)
51 #define FVTHROT_CNTRL_REG 0x3000
52 #define DONT_WAIT_FOR_FBDIV_WRAP (1 << 0)
55 #define MINIMUM_CIP_MASK 0x1fffffe
58 #define REFRESH_RATE_DIVISOR_MASK (0x3 << 25)
64 #define FVTHROT_TARGET_REG 0x3004
[all …]
/kernel/linux/linux-5.10/drivers/media/dvb-frontends/drx39xyj/
Ddrxj_map.h37 * Generated by: IDF:x 1.3.0
56 #define ATV_COMM_EXEC__A 0xC00000
58 #define ATV_COMM_EXEC__M 0x3
59 #define ATV_COMM_EXEC__PRE 0x0
60 #define ATV_COMM_EXEC_STOP 0x0
61 #define ATV_COMM_EXEC_ACTIVE 0x1
62 #define ATV_COMM_EXEC_HOLD 0x2
64 #define ATV_COMM_STATE__A 0xC00001
66 #define ATV_COMM_STATE__M 0xFFFF
67 #define ATV_COMM_STATE__PRE 0x0
[all …]
/kernel/linux/linux-4.19/drivers/media/dvb-frontends/drx39xyj/
Ddrxj_map.h37 * Generated by: IDF:x 1.3.0
56 #define ATV_COMM_EXEC__A 0xC00000
58 #define ATV_COMM_EXEC__M 0x3
59 #define ATV_COMM_EXEC__PRE 0x0
60 #define ATV_COMM_EXEC_STOP 0x0
61 #define ATV_COMM_EXEC_ACTIVE 0x1
62 #define ATV_COMM_EXEC_HOLD 0x2
64 #define ATV_COMM_STATE__A 0xC00001
66 #define ATV_COMM_STATE__M 0xFFFF
67 #define ATV_COMM_STATE__PRE 0x0
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/sun4i/
Dsun4i_tcon.h23 #define SUN4I_TCON_GCTL_REG 0x0
25 #define SUN4I_TCON_GCTL_IOMAP_MASK BIT(0)
26 #define SUN4I_TCON_GCTL_IOMAP_TCON1 (1 << 0)
27 #define SUN4I_TCON_GCTL_IOMAP_TCON0 (0 << 0)
29 #define SUN4I_TCON_GINT0_REG 0x4
37 #define SUN4I_TCON_GINT1_REG 0x8
39 #define SUN4I_TCON_FRM_CTL_REG 0x10
42 #define SUN4I_TCON_FRM_SEED_PR_REG 0x14
43 #define SUN4I_TCON_FRM_SEED_PG_REG 0x18
44 #define SUN4I_TCON_FRM_SEED_PB_REG 0x1c
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/sun4i/
Dsun4i_tcon.h19 #define SUN4I_TCON_GCTL_REG 0x0
21 #define SUN4I_TCON_GCTL_IOMAP_MASK BIT(0)
22 #define SUN4I_TCON_GCTL_IOMAP_TCON1 (1 << 0)
23 #define SUN4I_TCON_GCTL_IOMAP_TCON0 (0 << 0)
25 #define SUN4I_TCON_GINT0_REG 0x4
33 #define SUN4I_TCON_GINT1_REG 0x8
35 #define SUN4I_TCON_FRM_CTL_REG 0x10
41 #define SUN4I_TCON0_FRM_SEED_PR_REG 0x14
42 #define SUN4I_TCON0_FRM_SEED_PG_REG 0x18
43 #define SUN4I_TCON0_FRM_SEED_PB_REG 0x1c
[all …]
/kernel/linux/linux-5.10/drivers/media/platform/s5p-g2d/
Dg2d-hw.c27 w(0, SRC_SELECT_REG); in g2d_set_src_size()
28 w(f->stride & 0xFFFF, SRC_STRIDE_REG); in g2d_set_src_size()
30 n = f->o_height & 0xFFF; in g2d_set_src_size()
32 n |= f->o_width & 0xFFF; in g2d_set_src_size()
35 n = f->bottom & 0xFFF; in g2d_set_src_size()
37 n |= f->right & 0xFFF; in g2d_set_src_size()
52 w(0, DST_SELECT_REG); in g2d_set_dst_size()
53 w(f->stride & 0xFFFF, DST_STRIDE_REG); in g2d_set_dst_size()
55 n = f->o_height & 0xFFF; in g2d_set_dst_size()
57 n |= f->o_width & 0xFFF; in g2d_set_dst_size()
[all …]
/kernel/linux/linux-4.19/drivers/media/platform/s5p-g2d/
Dg2d-hw.c31 w(0, SRC_SELECT_REG); in g2d_set_src_size()
32 w(f->stride & 0xFFFF, SRC_STRIDE_REG); in g2d_set_src_size()
34 n = f->o_height & 0xFFF; in g2d_set_src_size()
36 n |= f->o_width & 0xFFF; in g2d_set_src_size()
39 n = f->bottom & 0xFFF; in g2d_set_src_size()
41 n |= f->right & 0xFFF; in g2d_set_src_size()
56 w(0, DST_SELECT_REG); in g2d_set_dst_size()
57 w(f->stride & 0xFFFF, DST_STRIDE_REG); in g2d_set_dst_size()
59 n = f->o_height & 0xFFF; in g2d_set_dst_size()
61 n |= f->o_width & 0xFFF; in g2d_set_dst_size()
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/amd/include/asic_reg/smu/
Dsmu_8_0_sh_mask.h27 #define THM_TCON_CSR_CONFIG__TCC_ADDR_MASK 0x3ff
28 #define THM_TCON_CSR_CONFIG__TCC_ADDR__SHIFT 0x0
29 #define THM_TCON_CSR_CONFIG__TCC_READ_OP_MASK 0x400
30 #define THM_TCON_CSR_CONFIG__TCC_READ_OP__SHIFT 0xa
31 #define THM_TCON_CSR_DATA__TCC_DATA_MASK 0xfff
32 #define THM_TCON_CSR_DATA__TCC_DATA__SHIFT 0x0
33 #define THM_TCON_CSR_DATA__TCC_REQ_DONE_MASK 0x1000
34 #define THM_TCON_CSR_DATA__TCC_REQ_DONE__SHIFT 0xc
35 #define THM_TCON_HTC__HTC_EN_MASK 0x1
36 #define THM_TCON_HTC__HTC_EN__SHIFT 0x0
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/smu/
Dsmu_8_0_sh_mask.h27 #define THM_TCON_CSR_CONFIG__TCC_ADDR_MASK 0x3ff
28 #define THM_TCON_CSR_CONFIG__TCC_ADDR__SHIFT 0x0
29 #define THM_TCON_CSR_CONFIG__TCC_READ_OP_MASK 0x400
30 #define THM_TCON_CSR_CONFIG__TCC_READ_OP__SHIFT 0xa
31 #define THM_TCON_CSR_DATA__TCC_DATA_MASK 0xfff
32 #define THM_TCON_CSR_DATA__TCC_DATA__SHIFT 0x0
33 #define THM_TCON_CSR_DATA__TCC_REQ_DONE_MASK 0x1000
34 #define THM_TCON_CSR_DATA__TCC_REQ_DONE__SHIFT 0xc
35 #define THM_TCON_HTC__HTC_EN_MASK 0x1
36 #define THM_TCON_HTC__HTC_EN__SHIFT 0x0
[all …]
/kernel/linux/linux-5.10/drivers/input/touchscreen/
Dmc13783_ts.c30 "is supposed to be wrong and is discarded. Set to 0 to "
53 schedule_delayed_work(&priv->work, 0); in mc13783_ts_handler()
75 * bits are for future 12 bit use and reading yields 0 in mc13783_ts_report_sample()
77 x0 = priv->sample[0] & 0xfff; in mc13783_ts_report_sample()
78 x1 = priv->sample[1] & 0xfff; in mc13783_ts_report_sample()
79 x2 = priv->sample[2] & 0xfff; in mc13783_ts_report_sample()
80 y0 = priv->sample[3] & 0xfff; in mc13783_ts_report_sample()
81 y1 = (priv->sample[0] >> 12) & 0xfff; in mc13783_ts_report_sample()
82 y2 = (priv->sample[1] >> 12) & 0xfff; in mc13783_ts_report_sample()
83 cr0 = (priv->sample[2] >> 12) & 0xfff; in mc13783_ts_report_sample()
[all …]
/kernel/linux/linux-4.19/drivers/input/touchscreen/
Dmc13783_ts.c33 "is supposed to be wrong and is discarded. Set to 0 to "
56 schedule_delayed_work(&priv->work, 0); in mc13783_ts_handler()
78 * bits are for future 12 bit use and reading yields 0 in mc13783_ts_report_sample()
80 x0 = priv->sample[0] & 0xfff; in mc13783_ts_report_sample()
81 x1 = priv->sample[1] & 0xfff; in mc13783_ts_report_sample()
82 x2 = priv->sample[2] & 0xfff; in mc13783_ts_report_sample()
83 y0 = priv->sample[3] & 0xfff; in mc13783_ts_report_sample()
84 y1 = (priv->sample[0] >> 12) & 0xfff; in mc13783_ts_report_sample()
85 y2 = (priv->sample[1] >> 12) & 0xfff; in mc13783_ts_report_sample()
86 cr0 = (priv->sample[2] >> 12) & 0xfff; in mc13783_ts_report_sample()
[all …]
/kernel/linux/linux-4.19/arch/arm/mach-mmp/
Dcputype.h10 * PXA168 S0 0x56158400 0x0000C910
11 * PXA168 A0 0x56158400 0x00A0A168
12 * PXA910 Y1 0x56158400 0x00F2C920
13 * PXA910 A0 0x56158400 0x00F2C910
14 * PXA910 A1 0x56158400 0x00A0C910
15 * PXA920 Y0 0x56158400 0x00F2C920
16 * PXA920 A0 0x56158400 0x00A0C920
17 * PXA920 A1 0x56158400 0x00A1C920
18 * MMP2 Z0 0x560f5811 0x00F00410
19 * MMP2 Z1 0x560f5811 0x00E00410
[all …]
/kernel/linux/linux-5.10/drivers/gpu/host1x/hw/
Dhw_host1x06_hypervisor.h6 #define HOST1X_HV_SYNCPT_PROT_EN 0x1ac4
8 #define HOST1X_HV_CH_KERNEL_FILTER_GBUFFER(x) (0x2020 + (x * 4))
9 #define HOST1X_HV_CMDFIFO_PEEK_CTRL 0x233c
13 #define HOST1X_HV_CMDFIFO_PEEK_READ 0x2340
14 #define HOST1X_HV_CMDFIFO_PEEK_PTRS 0x2344
15 #define HOST1X_HV_CMDFIFO_PEEK_PTRS_WR_PTR_V(x) (((x) >> 16) & 0xfff)
16 #define HOST1X_HV_CMDFIFO_PEEK_PTRS_RD_PTR_V(x) ((x) & 0xfff)
17 #define HOST1X_HV_CMDFIFO_SETUP(x) (0x2588 + (x * 4))
18 #define HOST1X_HV_CMDFIFO_SETUP_LIMIT_V(x) (((x) >> 16) & 0xfff)
19 #define HOST1X_HV_CMDFIFO_SETUP_BASE_V(x) ((x) & 0xfff)
[all …]
Dhw_host1x07_hypervisor.h6 #define HOST1X_HV_SYNCPT_PROT_EN 0x1ac4
8 #define HOST1X_HV_CH_KERNEL_FILTER_GBUFFER(x) (0x2020 + (x * 4))
9 #define HOST1X_HV_CMDFIFO_PEEK_CTRL 0x233c
13 #define HOST1X_HV_CMDFIFO_PEEK_READ 0x2340
14 #define HOST1X_HV_CMDFIFO_PEEK_PTRS 0x2344
15 #define HOST1X_HV_CMDFIFO_PEEK_PTRS_WR_PTR_V(x) (((x) >> 16) & 0xfff)
16 #define HOST1X_HV_CMDFIFO_PEEK_PTRS_RD_PTR_V(x) ((x) & 0xfff)
17 #define HOST1X_HV_CMDFIFO_SETUP(x) (0x2588 + (x * 4))
18 #define HOST1X_HV_CMDFIFO_SETUP_LIMIT_V(x) (((x) >> 16) & 0xfff)
19 #define HOST1X_HV_CMDFIFO_SETUP_BASE_V(x) ((x) & 0xfff)
[all …]
/kernel/linux/linux-5.10/include/linux/soc/mmp/
Dcputype.h12 * PXA168 S0 0x56158400 0x0000C910
13 * PXA168 A0 0x56158400 0x00A0A168
14 * PXA910 Y1 0x56158400 0x00F2C920
15 * PXA910 A0 0x56158400 0x00F2C910
16 * PXA910 A1 0x56158400 0x00A0C910
17 * PXA920 Y0 0x56158400 0x00F2C920
18 * PXA920 A0 0x56158400 0x00A0C920
19 * PXA920 A1 0x56158400 0x00A1C920
20 * MMP2 Z0 0x560f5811 0x00F00410
21 * MMP2 Z1 0x560f5811 0x00E00410
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/huawei/hinic/
Dhinic_hw_qp_ctxt.h17 #define HINIC_SQ_CTXT_CEQ_ATTR_GLOBAL_SQ_ID_MASK 0x3FF
18 #define HINIC_SQ_CTXT_CEQ_ATTR_EN_MASK 0x1
27 #define HINIC_SQ_CTXT_CI_IDX_MASK 0xFFF
28 #define HINIC_SQ_CTXT_CI_WRAPPED_MASK 0x1
34 #define HINIC_SQ_CTXT_WQ_PAGE_HI_PFN_SHIFT 0
37 #define HINIC_SQ_CTXT_WQ_PAGE_HI_PFN_MASK 0xFFFFF
38 #define HINIC_SQ_CTXT_WQ_PAGE_PI_MASK 0xFFF
44 #define HINIC_SQ_CTXT_PREF_CACHE_THRESHOLD_SHIFT 0
48 #define HINIC_SQ_CTXT_PREF_CACHE_THRESHOLD_MASK 0x3FFF
49 #define HINIC_SQ_CTXT_PREF_CACHE_MAX_MASK 0x7FF
[all …]
/kernel/linux/linux-4.19/drivers/gpu/host1x/hw/
Dhw_host1x06_hypervisor.h18 #define HOST1X_HV_SYNCPT_PROT_EN 0x1ac4
20 #define HOST1X_HV_CH_KERNEL_FILTER_GBUFFER(x) (0x2020 + (x * 4))
21 #define HOST1X_HV_CMDFIFO_PEEK_CTRL 0x233c
25 #define HOST1X_HV_CMDFIFO_PEEK_READ 0x2340
26 #define HOST1X_HV_CMDFIFO_PEEK_PTRS 0x2344
27 #define HOST1X_HV_CMDFIFO_PEEK_PTRS_WR_PTR_V(x) (((x) >> 16) & 0xfff)
28 #define HOST1X_HV_CMDFIFO_PEEK_PTRS_RD_PTR_V(x) ((x) & 0xfff)
29 #define HOST1X_HV_CMDFIFO_SETUP(x) (0x2588 + (x * 4))
30 #define HOST1X_HV_CMDFIFO_SETUP_LIMIT_V(x) (((x) >> 16) & 0xfff)
31 #define HOST1X_HV_CMDFIFO_SETUP_BASE_V(x) ((x) & 0xfff)
[all …]
/kernel/linux/linux-4.19/drivers/net/ethernet/huawei/hinic/
Dhinic_hw_qp_ctxt.h26 #define HINIC_SQ_CTXT_CEQ_ATTR_GLOBAL_SQ_ID_MASK 0x3FF
27 #define HINIC_SQ_CTXT_CEQ_ATTR_EN_MASK 0x1
36 #define HINIC_SQ_CTXT_CI_IDX_MASK 0xFFF
37 #define HINIC_SQ_CTXT_CI_WRAPPED_MASK 0x1
43 #define HINIC_SQ_CTXT_WQ_PAGE_HI_PFN_SHIFT 0
46 #define HINIC_SQ_CTXT_WQ_PAGE_HI_PFN_MASK 0xFFFFF
47 #define HINIC_SQ_CTXT_WQ_PAGE_PI_MASK 0xFFF
53 #define HINIC_SQ_CTXT_PREF_CACHE_THRESHOLD_SHIFT 0
57 #define HINIC_SQ_CTXT_PREF_CACHE_THRESHOLD_MASK 0x3FFF
58 #define HINIC_SQ_CTXT_PREF_CACHE_MAX_MASK 0x7FF
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
Dshadowacpi.c49 u32 limit = (offset + length + 0xfff) & ~0xfff; in acpi_read_fast()
50 u32 start = offset & ~0x00000fff; in acpi_read_fast()
53 if (nvbios_extend(bios, limit) >= 0) { in acpi_read_fast()
59 return 0; in acpi_read_fast()
70 u32 limit = (offset + length + 0xfff) & ~0xfff; in acpi_read_slow()
71 u32 start = offset & ~0xfff; in acpi_read_slow()
72 u32 fetch = 0; in acpi_read_slow()
74 if (nvbios_extend(bios, limit) >= 0) { in acpi_read_slow()
78 0x1000); in acpi_read_slow()
79 if (ret != 0x1000) in acpi_read_slow()
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/exynos/
Dregs-decon5433.h13 #define DECON_VIDCON0 0x0000
14 #define DECON_VIDOUTCON0 0x0010
15 #define DECON_WINCONx(n) (0x0020 + ((n) * 4))
16 #define DECON_VIDOSDxH(n) (0x0080 + ((n) * 4))
17 #define DECON_SHADOWCON 0x00A0
18 #define DECON_VIDOSDxA(n) (0x00B0 + ((n) * 0x20))
19 #define DECON_VIDOSDxB(n) (0x00B4 + ((n) * 0x20))
20 #define DECON_VIDOSDxC(n) (0x00B8 + ((n) * 0x20))
21 #define DECON_VIDOSDxD(n) (0x00BC + ((n) * 0x20))
22 #define DECON_VIDOSDxE(n) (0x00C0 + ((n) * 0x20))
[all …]

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