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/kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_pingpong.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
48 for (i = 0; i < m->pingpong_count; i++) { in _pingpong_offset()
49 if (pp == m->pingpong[i].id) { in _pingpong_offset()
50 b->base_off = addr; in _pingpong_offset()
51 b->blk_off = m->pingpong[i].base; in _pingpong_offset()
52 b->length = m->pingpong[i].len; in _pingpong_offset()
53 b->hwversion = m->hwversion; in _pingpong_offset()
54 b->log_mask = DPU_DBG_MASK_PINGPONG; in _pingpong_offset()
55 return &m->pingpong[i]; in _pingpong_offset()
[all …]
Ddpu_encoder_phys_cmd.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015-2018 The Linux Foundation. All rights reserved.
14 (e) && (e)->base.parent ? \
15 (e)->base.parent->base.id : -1, \
16 (e) ? (e)->base.intf_idx - INTF_0 : -1, ##__VA_ARGS__)
19 (e) && (e)->base.parent ? \
20 (e)->base.parent->base.id : -1, \
21 (e) ? (e)->base.intf_idx - INTF_0 : -1, ##__VA_ARGS__)
24 container_of(x, struct dpu_encoder_phys_cmd, base)
26 #define PP_TIMEOUT_MAX_TRIALS 10
[all …]
Ddpu_hw_catalog.h1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
76 * @DPU_MDP_10BIT_SUPPORT, Chipset supports 10 bit pixel formats
94 * SSPP sub-blocks/features
101 * @DPU_SSPP_CSC_10BIT, Support of 10-bit Color space conversion
104 * @DPU_SSPP_QOS_8LVL, SSPP support 8-level QoS control
134 * MIXER sub-blocks/features
136 * @DPU_MIXER_SOURCESPLIT Layer mixer supports source-split configuration
150 * DSPP sub-blocks
161 * PINGPONG sub-blocks
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/kernel/linux/linux-4.19/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_pingpong.c1 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
47 for (i = 0; i < m->pingpong_count; i++) { in _pingpong_offset()
48 if (pp == m->pingpong[i].id) { in _pingpong_offset()
49 b->base_off = addr; in _pingpong_offset()
50 b->blk_off = m->pingpong[i].base; in _pingpong_offset()
51 b->length = m->pingpong[i].len; in _pingpong_offset()
52 b->hwversion = m->hwversion; in _pingpong_offset()
53 b->log_mask = DPU_DBG_MASK_PINGPONG; in _pingpong_offset()
54 return &m->pingpong[i]; in _pingpong_offset()
58 return ERR_PTR(-EINVAL); in _pingpong_offset()
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Ddpu_encoder_phys_cmd.c2 * Copyright (c) 2015-2018 The Linux Foundation. All rights reserved.
23 (e) && (e)->base.parent ? \
24 (e)->base.parent->base.id : -1, \
25 (e) ? (e)->base.intf_idx - INTF_0 : -1, ##__VA_ARGS__)
28 (e) && (e)->base.parent ? \
29 (e)->base.parent->base.id : -1, \
30 (e) ? (e)->base.intf_idx - INTF_0 : -1, ##__VA_ARGS__)
33 container_of(x, struct dpu_encoder_phys_cmd, base)
35 #define PP_TIMEOUT_MAX_TRIALS 10
56 return (phys_enc->split_role != ENC_ROLE_SLAVE) ? true : false; in dpu_encoder_phys_cmd_is_master()
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Ddpu_hw_catalog.h1 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
82 * @DPU_MDP_10BIT_SUPPORT, Chipset supports 10 bit pixel formats
100 * SSPP sub-blocks/features
106 * @DPU_SSPP_CSC_10BIT, Support of 10-bit Color space conversion
109 * @DPU_SSPP_QOS_8LVL, SSPP support 8-level QoS control
138 * MIXER sub-blocks/features
140 * @DPU_MIXER_SOURCESPLIT Layer mixer supports source-split configuration
154 * PINGPONG sub-blocks
172 * CTL sub-blocks
182 * VBIF sub-blocks and features
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/kernel/linux/linux-4.19/arch/s390/kernel/
Dperf_cpum_sf.c1 // SPDX-License-Identifier: GPL-2.0
3 * Performance event support for the System z CPU-measurement Sampling Facility
26 /* Minimum number of sample-data-block-tables:
28 * A single table contains up to 511 pointers to sample-data-blocks.
32 /* Number of sample-data-blocks per sample-data-block-table (SDBT):
33 * A table contains SDB pointers (8 bytes) and one table-link entry
36 #define CPUM_SF_SDB_PER_TABLE ((PAGE_SIZE - 8) / 8)
38 /* Maximum page offset for an SDBT table-link entry:
39 * If this page offset is reached, a table-link entry to the next SDBT
51 * the number of sample-data-block-tables into account. Note that these
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/kernel/linux/linux-5.10/arch/s390/kernel/
Dperf_cpum_sf.c1 // SPDX-License-Identifier: GPL-2.0
3 * Performance event support for the System z CPU-measurement Sampling Facility
26 /* Minimum number of sample-data-block-tables:
28 * A single table contains up to 511 pointers to sample-data-blocks.
32 /* Number of sample-data-blocks per sample-data-block-table (SDBT):
33 * A table contains SDB pointers (8 bytes) and one table-link entry
36 #define CPUM_SF_SDB_PER_TABLE ((PAGE_SIZE - 8) / 8)
38 /* Maximum page offset for an SDBT table-link entry:
39 * If this page offset is reached, a table-link entry to the next SDBT
51 * the number of sample-data-block-tables into account. Note that these
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dti,dp83869.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - $ref: "ethernet-phy.yaml#"
14 - Dan Murphy <dmurphy@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
23 the DP83869HM can run 1000BASE-X-to-1000BASE-T and 100BASE-FX-to-100BASE-TX
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Dti,dp83867.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - $ref: "ethernet-controller.yaml#"
14 - Dan Murphy <dmurphy@ti.com>
18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
19 and 1000BASE-T Ethernet protocols.
21 The DP83867 is designed for easy implementation of 10/100/1000 Mbps Ethernet
34 ti,min-output-impedance:
40 ti,max-output-impedance:
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/kernel/linux/linux-4.19/drivers/net/ethernet/intel/ice/
Dice_lan_tx_rx.h1 /* SPDX-License-Identifier: GPL-2.0 */
44 u32 ptype:10;
118 __le16 ptype_flex_flags0; /* ptype=[9:0], ff0=[15:10] */
120 __le16 hdr_len_sph_flex_flags1; /* header=[10:0] */
187 * profiles 2-63 are flex profiles that can be programmed
229 #define ICE_RX_FLEX_DESC_PTYPE_M (0x3FF) /* 10-bits */
232 #define ICE_RX_FLX_DESC_PKT_LEN_M (0x3FFF) /* 14-bits */
269 u64 base; member
329 /* DESC_DONE - HW has completed write-back of descriptor */
413 u64 base; /* base is defined in 128-byte units */ member
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/kernel/linux/linux-4.19/crypto/
Dchacha20_generic.c2 * ChaCha20 256-bit cipher algorithm, RFC7539
30 bytes -= CHACHA20_BLOCK_SIZE; in chacha20_docrypt()
43 state[2] = 0x79622d32; /* "2-by" */ in crypto_chacha20_init()
44 state[3] = 0x6b206574; /* "te k" */ in crypto_chacha20_init()
45 state[4] = ctx->key[0]; in crypto_chacha20_init()
46 state[5] = ctx->key[1]; in crypto_chacha20_init()
47 state[6] = ctx->key[2]; in crypto_chacha20_init()
48 state[7] = ctx->key[3]; in crypto_chacha20_init()
49 state[8] = ctx->key[4]; in crypto_chacha20_init()
50 state[9] = ctx->key[5]; in crypto_chacha20_init()
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/kernel/linux/linux-5.10/arch/x86/events/intel/
Dpt.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2013-2014, Intel Corporation.
8 * http://software.intel.com/en-us/intel-isa-extensions
23 #include <asm/intel-family.h>
40 * width encoded in IP-related packets), and event configuration (bitmasks with
74 u32 c = caps[cd->leaf * PT_CPUID_REGS_NUM + cd->reg]; in intel_pt_validate_cap()
75 unsigned int shift = __ffs(cd->mask); in intel_pt_validate_cap()
77 return (c & cd->mask) >> shift; in intel_pt_validate_cap()
93 enum pt_capabilities cap = (long)ea->var; in pt_cap_show()
107 PMU_FORMAT_ATTR(tsc, "config:10" );
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/kernel/linux/linux-5.10/tools/perf/Documentation/
Dsecurity.txt6 https://www.kernel.org/doc/html/latest/admin-guide/perf-security.html
15 1. Download selinux-policy SRPM package (e.g. selinux-policy-3.14.4-48.fc31.src.rpm on FC31)
18 # rpm -Uhv selinux-policy-3.14.4-48.fc31.src.rpm
22 # rpmbuild -bp selinux-policy.spec
24 3. Place patch below at rpmbuild/BUILD/selinux-policy-b86eaaf4dbcf2d51dd4432df7185c0eaf3cbcc02
27 # patch -p1 < selinux-policy-perf-events-perfmon.patch
30 # cat selinux-policy-perf-events-perfmon.patch
31 diff -Nura a/policy/flask/access_vectors b/policy/flask/access_vectors
32 --- a/policy/flask/access_vectors 2020-02-04 18:19:53.000000000 +0300
33 +++ b/policy/flask/access_vectors 2020-02-28 23:37:25.000000000 +0300
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/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
Dicl_dsi.c58 drm_err(&dev_priv->drm, "DSI header credits not released\n"); in wait_for_header_credits()
66 drm_err(&dev_priv->drm, "DSI payload credits not released\n"); in wait_for_payload_credits()
79 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in wait_for_cmds_dispatched_to_panel()
87 for_each_dsi_port(port, intel_dsi->ports) { in wait_for_cmds_dispatched_to_panel()
94 for_each_dsi_port(port, intel_dsi->ports) { in wait_for_cmds_dispatched_to_panel()
95 dsi = intel_dsi->dsi_hosts[port]->device; in wait_for_cmds_dispatched_to_panel()
96 dsi->mode_flags |= MIPI_DSI_MODE_LPM; in wait_for_cmds_dispatched_to_panel()
97 dsi->channel = 0; in wait_for_cmds_dispatched_to_panel()
100 drm_err(&dev_priv->drm, in wait_for_cmds_dispatched_to_panel()
105 for_each_dsi_port(port, intel_dsi->ports) { in wait_for_cmds_dispatched_to_panel()
[all …]
Dintel_display_types.h3 * Copyright (c) 2007-2008 Intel Corporation
44 #include <media/cec-notifier.h>
56 /* these are outputs from the chip - integrated only
69 INTEL_OUTPUT_DDI = 10,
74 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
88 struct drm_framebuffer base; member
96 /* for each plane in the rotated GTT view for no-CCS formats */
129 struct drm_encoder base; member
185 * state. This must be called _after_ display->get_pipe_config has
186 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
[all …]
/kernel/linux/linux-5.10/sound/soc/fsl/
Dfsl_sai.c1 // SPDX-License-Identifier: GPL-2.0+
5 // Copyright 2012-2015 Freescale Semiconductor, Inc.
21 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
24 #include "imx-pcm.h"
41 * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream
55 return !sai->synchronous[dir] && sai->synchronous[adir]; in fsl_sai_dir_is_synced()
61 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_isr()
62 struct device *dev = &sai->pdev->dev; in fsl_sai_isr()
74 regmap_read(sai->regmap, FSL_SAI_TCSR(ofs), &xcsr); in fsl_sai_isr()
104 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), flags | xcsr); in fsl_sai_isr()
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/kernel/linux/linux-5.10/include/linux/fsl/
Dptp_qoriq.h1 // SPDX-License-Identifier: GPL-2.0
83 #define ESFDE (1<<10) /* External Tx/Rx SFD Enable. */
90 #define TE (1<<2) /* 1588 timer enable. */ macro
142 void __iomem *base; member
186 int ptp_qoriq_init(struct ptp_qoriq *ptp_qoriq, void __iomem *base,
/kernel/linux/linux-4.19/include/linux/fsl/
Dptp_qoriq.h1 // SPDX-License-Identifier: GPL-2.0
82 #define ESFDE (1<<10) /* External Tx/Rx SFD Enable. */
89 #define TE (1<<2) /* 1588 timer enable. */ macro
138 void __iomem *base; member
/kernel/linux/linux-5.10/drivers/net/wan/
Dpc300too.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2000-2008 Krzysztof Halasa <khc@pm.waw.pl>
10 * Hitachi HD64572 SCA-II User's Manual
44 #define MAX_TX_BUFFERS 10
59 * PLX PCI9050-1 local configuration and shared runtime registers.
63 u32 loc_addr_range[4]; /* 00-0Ch : Local Address Ranges */
64 u32 loc_rom_range; /* 10h : Local ROM Range */
65 u32 loc_addr_base[4]; /* 14-20h : Local Address Base Addrs */
66 u32 loc_rom_base; /* 24h : Local ROM Base */
67 u32 loc_bus_descr[4]; /* 28-34h : Local Bus Descriptors */
[all …]
/kernel/linux/linux-4.19/drivers/net/wan/
Dpc300too.c4 * Copyright (C) 2000-2008 Krzysztof Halasa <khc@pm.waw.pl>
13 * Hitachi HD64572 SCA-II User's Manual
47 #define MAX_TX_BUFFERS 10
62 * PLX PCI9050-1 local configuration and shared runtime registers.
66 u32 loc_addr_range[4]; /* 00-0Ch : Local Address Ranges */
67 u32 loc_rom_range; /* 10h : Local ROM Range */
68 u32 loc_addr_base[4]; /* 14-20h : Local Address Base Addrs */
69 u32 loc_rom_base; /* 24h : Local ROM Base */
70 u32 loc_bus_descr[4]; /* 28-34h : Local Bus Descriptors */
72 u32 cs_base[4]; /* 3C-48h : Chip Select Base Addrs */
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/intel/ice/
Dice_lan_tx_rx.h1 /* SPDX-License-Identifier: GPL-2.0 */
142 u32 ptype:10;
216 __le16 ptype_flex_flags0; /* ptype=[9:0], ff0=[15:10] */
218 __le16 hdr_len_sph_flex_flags1; /* header=[10:0] */
285 * profiles 2-63 are flex profiles that can be programmed
337 #define ICE_RX_FLEX_DESC_PTYPE_M (0x3FF) /* 10-bits */
340 #define ICE_RX_FLX_DESC_PKT_LEN_M (0x3FFF) /* 14-bits */
386 u64 base; member
448 /* DESC_DONE - HW has completed write-back of descriptor */
554 u64 base; /* base is defined in 128-byte units */ member
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/kernel/linux/linux-5.10/drivers/message/fusion/
Dmptbase.h8 * Copyright (c) 1999-2008 LSI Corporation
9 * (mailto:DL-MPTFusionLinux@lsi.com)
12 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
26 LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
45 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
50 /*{-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
69 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
76 #define COPYRIGHT "Copyright (c) 1999-2008 " MODULEAUTHOR
80 #define MPT_LINUX_PACKAGE_NAME "@(#)mptlinux-3.04.20"
86 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
[all …]
/kernel/linux/linux-4.19/drivers/message/fusion/
Dmptbase.h8 * Copyright (c) 1999-2008 LSI Corporation
9 * (mailto:DL-MPTFusionLinux@lsi.com)
12 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
26 LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
45 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
50 /*{-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
69 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
76 #define COPYRIGHT "Copyright (c) 1999-2008 " MODULEAUTHOR
80 #define MPT_LINUX_PACKAGE_NAME "@(#)mptlinux-3.04.20"
86 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
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/kernel/linux/linux-4.19/drivers/gpu/drm/i915/
Dintel_engine_cs.c35 * on HSW) - so the final size, including the extra state required for the
92 u32 base : 24; member
103 { .gen = 1, .base = RENDER_RING_BASE }
112 { .gen = 6, .base = BLT_RING_BASE }
121 { .gen = 11, .base = GEN11_BSD_RING_BASE },
122 { .gen = 6, .base = GEN6_BSD_RING_BASE },
123 { .gen = 4, .base = BSD_RING_BASE }
132 { .gen = 11, .base = GEN11_BSD2_RING_BASE },
133 { .gen = 8, .base = GEN8_BSD2_RING_BASE }
142 { .gen = 11, .base = GEN11_BSD3_RING_BASE }
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