Home
last modified time | relevance | path

Searched +full:11 +full:- +full:bit (Results 1 – 25 of 1058) sorted by relevance

12345678910>>...43

/kernel/linux/linux-5.10/Documentation/devicetree/bindings/media/i2c/
Dtda1997x.txt1 Device-Tree bindings for the NXP TDA1997x HDMI receiver
6 - RGB 8bit per color (24 bits total): R[11:4] B[11:4] G[11:4]
7 - YUV444 8bit per color (24 bits total): Y[11:4] Cr[11:4] Cb[11:4]
8 - YUV422 semi-planar 8bit per component (16 bits total): Y[11:4] CbCr[11:4]
9 - YUV422 semi-planar 10bit per component (20 bits total): Y[11:2] CbCr[11:2]
10 - YUV422 semi-planar 12bit per component (24 bits total): - Y[11:0] CbCr[11:0]
11 - YUV422 BT656 8bit per component (8 bits total): YCbCr[11:4] (2-cycles)
12 - YUV422 BT656 10bit per component (10 bits total): YCbCr[11:2] (2-cycles)
13 - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
16 - RGB 12bit per color (36 bits total): R[11:0] B[11:0] G[11:0]
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/media/i2c/
Dtda1997x.txt1 Device-Tree bindings for the NXP TDA1997x HDMI receiver
6 - RGB 8bit per color (24 bits total): R[11:4] B[11:4] G[11:4]
7 - YUV444 8bit per color (24 bits total): Y[11:4] Cr[11:4] Cb[11:4]
8 - YUV422 semi-planar 8bit per component (16 bits total): Y[11:4] CbCr[11:4]
9 - YUV422 semi-planar 10bit per component (20 bits total): Y[11:2] CbCr[11:2]
10 - YUV422 semi-planar 12bit per component (24 bits total): - Y[11:0] CbCr[11:0]
11 - YUV422 BT656 8bit per component (8 bits total): YCbCr[11:4] (2-cycles)
12 - YUV422 BT656 10bit per component (10 bits total): YCbCr[11:2] (2-cycles)
13 - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
16 - RGB 12bit per color (36 bits total): R[11:0] B[11:0] G[11:0]
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/mediatek/mt76/mt7615/
Dmac.h1 /* SPDX-License-Identifier: ISC */
15 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
16 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
17 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
18 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
19 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
20 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
36 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
37 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)
41 #define MT_RXD1_NORMAL_BEACON_UC BIT(5)
[all …]
/kernel/linux/linux-4.19/drivers/net/ethernet/mscc/
Docelot_hsio.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
11 #define HSIO_PLL5G_CFG0_ENA_ROT BIT(31)
12 #define HSIO_PLL5G_CFG0_ENA_LANE BIT(30)
13 #define HSIO_PLL5G_CFG0_ENA_CLKTREE BIT(29)
14 #define HSIO_PLL5G_CFG0_DIV4 BIT(28)
15 #define HSIO_PLL5G_CFG0_ENA_LOCK_FINE BIT(27)
25 #define HSIO_PLL5G_CFG0_ENA_VCO_CONTRH BIT(15)
26 #define HSIO_PLL5G_CFG0_ENA_CP1 BIT(14)
27 #define HSIO_PLL5G_CFG0_ENA_VCO_BUF BIT(13)
28 #define HSIO_PLL5G_CFG0_ENA_BIAS BIT(12)
[all …]
Docelot_ana.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
11 #define ANA_ANAGEFIL_B_DOM_EN BIT(22)
12 #define ANA_ANAGEFIL_B_DOM_VAL BIT(21)
13 #define ANA_ANAGEFIL_AGE_LOCKED BIT(20)
14 #define ANA_ANAGEFIL_PID_EN BIT(19)
18 #define ANA_ANAGEFIL_VID_EN BIT(13)
27 #define ANA_STORMLIMIT_CFG_STORM_UNIT BIT(2)
31 #define ANA_AUTOAGE_AGE_FAST BIT(21)
35 #define ANA_AUTOAGE_AUTOAGE_LOCKED BIT(0)
37 #define ANA_MACTOPTIONS_REDUCED_TABLE BIT(1)
[all …]
/kernel/linux/linux-5.10/include/soc/mscc/
Docelot_hsio.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
85 #define HSIO_PLL5G_CFG0_ENA_ROT BIT(31)
86 #define HSIO_PLL5G_CFG0_ENA_LANE BIT(30)
87 #define HSIO_PLL5G_CFG0_ENA_CLKTREE BIT(29)
88 #define HSIO_PLL5G_CFG0_DIV4 BIT(28)
89 #define HSIO_PLL5G_CFG0_ENA_LOCK_FINE BIT(27)
99 #define HSIO_PLL5G_CFG0_ENA_VCO_CONTRH BIT(15)
100 #define HSIO_PLL5G_CFG0_ENA_CP1 BIT(14)
101 #define HSIO_PLL5G_CFG0_ENA_VCO_BUF BIT(13)
102 #define HSIO_PLL5G_CFG0_ENA_BIAS BIT(12)
[all …]
Docelot_ana.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
11 #define ANA_ANAGEFIL_B_DOM_EN BIT(22)
12 #define ANA_ANAGEFIL_B_DOM_VAL BIT(21)
13 #define ANA_ANAGEFIL_AGE_LOCKED BIT(20)
14 #define ANA_ANAGEFIL_PID_EN BIT(19)
18 #define ANA_ANAGEFIL_VID_EN BIT(13)
27 #define ANA_STORMLIMIT_CFG_STORM_UNIT BIT(2)
31 #define ANA_AUTOAGE_AGE_FAST BIT(21)
35 #define ANA_AUTOAGE_AUTOAGE_LOCKED BIT(0)
37 #define ANA_MACTOPTIONS_REDUCED_TABLE BIT(1)
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/mediatek/mt76/mt7603/
Dmac.h1 /* SPDX-License-Identifier: ISC */
10 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
11 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
12 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
13 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
14 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
15 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
29 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
30 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)
34 #define MT_RXD1_NORMAL_BEACON_UC BIT(5)
[all …]
/kernel/liteos_m/targets/riscv_nuclei_gd32vf103_soc_gcc/SoC/gd32vf103/Common/Include/
Dgd32vf103_gpio.h5 \version 2019-06-5, V1.0.0, firmware for GD32VF103
59 #define GPIO_BOP(gpiox) REG32((gpiox) + 0x10U) /*!< GPIO port bit operation register …
60 #define GPIO_BC(gpiox) REG32((gpiox) + 0x14U) /*!< GPIO bit clear register */
79 #define GPIO_CTL0_CTL2 BITS(10, 11) /*!< pin 2 configuration bits */
97 #define GPIO_CTL1_CTL10 BITS(10, 11) /*!< pin 10 configuration bits */
98 #define GPIO_CTL1_MD11 BITS(12, 13) /*!< port 11 mode bits */
99 #define GPIO_CTL1_CTL11 BITS(14, 15) /*!< pin 11 configuration bits */
110 #define GPIO_ISTAT_ISTAT0 BIT(0) /*!< pin 0 input status */
111 #define GPIO_ISTAT_ISTAT1 BIT(1) /*!< pin 1 input status */
112 #define GPIO_ISTAT_ISTAT2 BIT(2) /*!< pin 2 input status */
[all …]
Dgd32vf103_exti.h5 \version 2019-6-5, V1.0.0, firmware for GD32VF103
56 #define EXTI_INTEN_INTEN0 BIT(0) /*!< interrupt from line 0 */
57 #define EXTI_INTEN_INTEN1 BIT(1) /*!< interrupt from line 1 */
58 #define EXTI_INTEN_INTEN2 BIT(2) /*!< interrupt from line 2 */
59 #define EXTI_INTEN_INTEN3 BIT(3) /*!< interrupt from line 3 */
60 #define EXTI_INTEN_INTEN4 BIT(4) /*!< interrupt from line 4 */
61 #define EXTI_INTEN_INTEN5 BIT(5) /*!< interrupt from line 5 */
62 #define EXTI_INTEN_INTEN6 BIT(6) /*!< interrupt from line 6 */
63 #define EXTI_INTEN_INTEN7 BIT(7) /*!< interrupt from line 7 */
64 #define EXTI_INTEN_INTEN8 BIT(8) /*!< interrupt from line 8 */
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/stmicro/stmmac/
Ddescs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
18 #define RDES0_PAYLOAD_CSUM_ERR BIT(0)
19 #define RDES0_CRC_ERROR BIT(1)
20 #define RDES0_DRIBBLING BIT(2)
21 #define RDES0_MII_ERROR BIT(3)
22 #define RDES0_RECEIVE_WATCHDOG BIT(4)
23 #define RDES0_FRAME_TYPE BIT(5)
24 #define RDES0_COLLISION BIT(6)
25 #define RDES0_IPC_CSUM_ERROR BIT(7)
26 #define RDES0_LAST_DESCRIPTOR BIT(8)
[all …]
/kernel/linux/linux-5.10/drivers/staging/comedi/drivers/
Dni_stc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Register descriptions for NI DAQ-STC chip
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 1998-9 David A. Schleef <ds@schleef.org>
11 * DAQ-STC Technical Reference Manual
21 * Registers in the National Instruments DAQ-STC chip
25 #define NISTC_INTA_ACK_G0_GATE BIT(15)
26 #define NISTC_INTA_ACK_G0_TC BIT(14)
27 #define NISTC_INTA_ACK_AI_ERR BIT(13)
28 #define NISTC_INTA_ACK_AI_STOP BIT(12)
[all …]
/kernel/linux/linux-5.10/drivers/mmc/host/
Dmeson-mx-sdhc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
15 #define MESON_SDHC_SEND_CMD_HAS_RESP BIT(6)
16 #define MESON_SDHC_SEND_CMD_HAS_DATA BIT(7)
17 #define MESON_SDHC_SEND_RESP_LEN BIT(8)
18 #define MESON_SDHC_SEND_RESP_NO_CRC BIT(9)
19 #define MESON_SDHC_SEND_DATA_DIR BIT(10)
20 #define MESON_SDHC_SEND_DATA_STOP BIT(11)
21 #define MESON_SDHC_SEND_R1B BIT(12)
26 #define MESON_SDHC_CTRL_DDR_MODE BIT(2)
27 #define MESON_SDHC_CTRL_TX_CRC_NOCHECK BIT(3)
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/mediatek/mt76/mt7915/
Dmac.h1 /* SPDX-License-Identifier: ISC */
14 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
15 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
30 #define MT_RXD1_NORMAL_GROUP_1 BIT(11)
31 #define MT_RXD1_NORMAL_GROUP_2 BIT(12)
32 #define MT_RXD1_NORMAL_GROUP_3 BIT(13)
33 #define MT_RXD1_NORMAL_GROUP_4 BIT(14)
34 #define MT_RXD1_NORMAL_GROUP_5 BIT(15)
37 #define MT_RXD1_NORMAL_CM BIT(23)
38 #define MT_RXD1_NORMAL_CLM BIT(24)
[all …]
/kernel/linux/linux-4.19/drivers/staging/comedi/drivers/
Dni_stc.h1 // SPDX-License-Identifier: GPL-2.0+
3 * Register descriptions for NI DAQ-STC chip
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 1998-9 David A. Schleef <ds@schleef.org>
11 * DAQ-STC Technical Reference Manual
20 * Registers in the National Instruments DAQ-STC chip
24 #define NISTC_INTA_ACK_G0_GATE BIT(15)
25 #define NISTC_INTA_ACK_G0_TC BIT(14)
26 #define NISTC_INTA_ACK_AI_ERR BIT(13)
27 #define NISTC_INTA_ACK_AI_STOP BIT(12)
[all …]
/kernel/linux/linux-5.10/drivers/power/supply/
Dbd99954-charger.h1 /* SPDX-License-Identifier: GPL-2.0-only */
500 [F_PP_BOTH_THRU] = REG_FIELD(VIN_CTRL_SET, 11, 11),
510 [F_VCC_BC_DISEN] = REG_FIELD(CHGOP_SET1, 11, 11),
550 [F_PROCHOT_ICRIT_DG_SET] = REG_FIELD(PROCHOT_CTRL_SET, 10, 11),
565 [F_IOUT_DACIN_VAL] = REG_FIELD(IOUT_DACIN_VAL, 0, 11),
577 [F_VCC_PUPDET] = REG_FIELD(VCC_UCD_STATUS, 11, 11),
621 [F_VBUS_PUPDET] = REG_FIELD(VBUS_UCD_STATUS, 11, 11),
657 [F_ONE_CELL_MODE] = REG_FIELD(IC_SET1, 11, 11),
674 [F_ADCTMOD] = REG_FIELD(VM_CTRL_SET, 10, 11),
704 [F_EXTIADP_TH_SET] = REG_FIELD(EXTIADP_TH_SET, 0, 11),
[all …]
/kernel/linux/linux-5.10/drivers/net/dsa/b53/
Db53_serdes.h1 /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
11 /* Non-standard page used to access SerDes PHY registers on NorthStar Plus */
18 #define SERDES_ID0_REV_NUM_SHIFT 11
27 #define FIBER_MODE_1000X BIT(0)
28 #define TBI_INTERFACE BIT(1)
29 #define SIGNAL_DETECT_EN BIT(2)
30 #define INVERT_SIGNAL_DETECT BIT(3)
31 #define AUTODET_EN BIT(4)
32 #define SGMII_MASTER_MODE BIT(5)
33 #define DISABLE_DLL_PWRDOWN BIT(6)
[all …]
/kernel/linux/linux-4.19/drivers/staging/sm750fb/
Dddk750_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 #define DE_STATE1_DE_ABORT BIT(0)
10 #define DE_STATE2_DE_FIFO_EMPTY BIT(3)
11 #define DE_STATE2_DE_STATUS_BUSY BIT(2)
12 #define DE_STATE2_DE_MEM_FIFO_EMPTY BIT(1)
20 #define SYSTEM_CTRL_PCI_BURST BIT(29)
21 #define SYSTEM_CTRL_PCI_MASTER BIT(25)
22 #define SYSTEM_CTRL_LATENCY_TIMER_OFF BIT(24)
23 #define SYSTEM_CTRL_DE_FIFO_EMPTY BIT(23)
24 #define SYSTEM_CTRL_DE_STATUS_BUSY BIT(22)
[all …]
/kernel/linux/linux-5.10/drivers/staging/sm750fb/
Dddk750_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 #define DE_STATE1_DE_ABORT BIT(0)
10 #define DE_STATE2_DE_FIFO_EMPTY BIT(3)
11 #define DE_STATE2_DE_STATUS_BUSY BIT(2)
12 #define DE_STATE2_DE_MEM_FIFO_EMPTY BIT(1)
20 #define SYSTEM_CTRL_PCI_BURST BIT(29)
21 #define SYSTEM_CTRL_PCI_MASTER BIT(25)
22 #define SYSTEM_CTRL_LATENCY_TIMER_OFF BIT(24)
23 #define SYSTEM_CTRL_DE_FIFO_EMPTY BIT(23)
24 #define SYSTEM_CTRL_DE_STATUS_BUSY BIT(22)
[all …]
/kernel/linux/linux-5.10/drivers/staging/media/atomisp/pci/css_2401_system/hrt/
Dmipi_backend_common_defs.h1 /* SPDX-License-Identifier: GPL-2.0 */
28 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8 24 /* 01 1000 YUV420 8-bit …
29 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_10 25 /* 01 1001 YUV420 10-bit …
30 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8L 26 /* 01 1010 YUV420 8-bit lega…
31 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV422_8 30 /* 01 1110 YUV422 8-bit …
32 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV422_10 31 /* 01 1111 YUV422 10-bit …
44 …CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_1 48 /* 11 0000 JPEG [User Defined 8-bit Dat…
45 …RT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_2 49 /* 11 0001 User Defined 8-bit Data T…
46 …RT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_3 50 /* 11 0010 User Defined 8-bit Data T…
47 …RT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_4 51 /* 11 0011 User Defined 8-bit Data T…
[all …]
/kernel/linux/linux-5.10/include/linux/amba/
Dpl080.h1 /* SPDX-License-Identifier: GPL-2.0-only */
17 * the ability to move more than 2^11 counts of data and some extra
38 #define PL080_CONFIG_M2_BE BIT(2)
39 #define PL080_CONFIG_M1_BE BIT(1)
40 #define PL080_CONFIG_ENABLE BIT(0)
72 #define PL080_LLI_LM_AHB2 BIT(0)
74 #define PL080_CONTROL_TC_IRQ_EN BIT(31)
77 #define PL080_CONTROL_PROT_CACHE BIT(30)
78 #define PL080_CONTROL_PROT_BUFF BIT(29)
79 #define PL080_CONTROL_PROT_SYS BIT(28)
[all …]
/kernel/linux/linux-5.10/include/linux/
Dfsl-diu-fb.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
7 * Authors: Hongjun Chen <hong-jun.chen@freescale.com>
68 /* Word 0(32-bit) in DDR memory */
81 /* Word 1(32-bit) in DDR memory */
84 /* Word 2(32-bit) in DDR memory */
85 /* __u32 delta_xs:11; */
87 /* __u32 delta_ys:11; */
92 /* Word 3(32-bit) in DDR memory */
93 /* __u32 delta_xi:11; */
95 /* __u32 delta_yi:11; */
[all …]
/kernel/linux/linux-4.19/include/linux/
Dfsl-diu-fb.h6 * Authors: Hongjun Chen <hong-jun.chen@freescale.com>
73 /* Word 0(32-bit) in DDR memory */
86 /* Word 1(32-bit) in DDR memory */
89 /* Word 2(32-bit) in DDR memory */
90 /* __u32 delta_xs:11; */
92 /* __u32 delta_ys:11; */
97 /* Word 3(32-bit) in DDR memory */
98 /* __u32 delta_xi:11; */
100 /* __u32 delta_yi:11; */
105 /* Word 4(32-bit) in DDR memory */
[all …]
/kernel/linux/linux-5.10/drivers/thunderbolt/
Dtb_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Thunderbolt driver - Port/Switch config area registers
65 * struct tb_cap_extended_short - Switch extended short capability
80 * struct tb_cap_extended_long - Switch extended long capability
98 * struct tb_cap_any - Structure capable of hold every capability
130 u32 unknown3:11;
136 bool clock:1; /* send pulse to transfer one bit */
156 u32 drom_offset; /* 32 bit register, but eeprom addresses are 16 bit */
195 #define ROUTER_CS_5_SLP BIT(0)
196 #define ROUTER_CS_5_WOP BIT(1)
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/v3d/
Dv3d_regs.h1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2017-2018 Broadcom */
30 # define V3D_HUB_IDENT1_WITH_MSO BIT(19)
31 # define V3D_HUB_IDENT1_WITH_TSY BIT(18)
32 # define V3D_HUB_IDENT1_WITH_TFU BIT(17)
33 # define V3D_HUB_IDENT1_WITH_L3C BIT(16)
36 # define V3D_HUB_IDENT1_NCORES_MASK V3D_MASK(11, 8)
44 # define V3D_HUB_IDENT2_WITH_MMU BIT(8)
60 # define V3D_HUB_INT_MMU_WRV BIT(5)
61 # define V3D_HUB_INT_MMU_PTI BIT(4)
[all …]

12345678910>>...43